1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/{ 8 reserved-memory { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 ranges; 12 13 drm_vehicle: drm-vehicle@20000000{ 14 compatible = "shared-dma-pool"; 15 inactive; 16 reusable; 17 reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M 18 linux,cma-default; 19 }; 20 }; 21 22 gpio_det: gpio-det { 23 compatible = "gpio-detection"; 24 status = "okay"; 25 26 pinctrl-names = "default"; 27 pinctrl-0 = <&vehicle_gpios>; 28 29 car-reverse { 30 car-reverse-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 31 linux,debounce-ms = <5>; 32 label = "car-reverse"; 33 gpio,wakeup; 34 }; 35 36 }; 37 38 vehicle: vehicle { 39 compatible = "rockchip,vehicle"; 40 status = "okay"; 41 42 // pinctrl-names = "default"; 43 // pinctrl-0 = <&mipim1_camera1_clk>; 44 45 clocks = <&cru ACLK_VICAP>, 46 <&cru HCLK_VICAP>, 47 <&cru DCLK_VICAP>; 48 clock-names = "aclk_cif", 49 "hclk_cif", 50 "dclk_cif"; 51 resets = <&cru SRST_A_VICAP>, 52 <&cru SRST_H_VICAP>, 53 <&cru SRST_D_VICAP>; 54 reset-names = "rst_cif_a", 55 "rst_cif_h", 56 "rst_cif_d"; 57 assigned-clocks = <&cru DCLK_VICAP>; 58 assigned-clock-rates = <600000000>; 59 power-domains = <&power RK3588_PD_VI>; 60 cif,drop-frames = <4>; //frames to drop 61 cif,chip-id = <1>; /*0:rk3568 1:rk3588*/ 62 rockchip,grf = <&sys_grf>; 63 rockchip,cru = <&cru>; 64 rockchip,cif = <&rkcif>; 65 rockchip,gpio-det = <&gpio_det>; 66 rockchip,cif-sensor = <&cif_sensor>; 67 rockchip,cif-phy = <&cif_phy>; 68 ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 69 /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ 70 vehicle,rotate-mirror = <0x00>; 71 vehicle,crtc_name = "video_port3"; 72 vehicle,plane_name = "Esmart3-win0"; 73 }; 74 75 cif_phy: cif_phy { 76 status = "okay"; 77 78 csi2_dcphy0 { 79 status = "disabled"; 80 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>, 81 <&cru PCLK_MIPI_DCPHY0>, 82 <&cru PCLK_CSI_HOST_0>, 83 <&cru ICLK_CSIHOST0>; 84 clock-names = "xvclk", 85 "pclk", 86 "pclk_csi2host", 87 "iclk_csi2host"; 88 resets = <&cru SRST_P_CSI_HOST_0>, 89 <&cru SRST_CSIHOST0_VICAP>; 90 reset-names = "srst_csihost_p", 91 "srst_csihost_vicap"; 92 csihost-idx = <0>; 93 rockchip,csi2 = <&mipi0_csi2>; 94 phys = <&mipi_dcphy0>; 95 phy-names = "dcphy"; 96 }; 97 csi2_dcphy1 { 98 status = "disabled"; 99 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, 100 <&cru PCLK_MIPI_DCPHY1>, 101 <&cru PCLK_CSI_HOST_1>, 102 <&cru ICLK_CSIHOST1>; 103 clock-names = "xvclk", 104 "pclk", 105 "pclk_csi2host", 106 "iclk_csi2host"; 107 resets = <&cru SRST_P_CSI_HOST_1>, 108 <&cru SRST_CSIHOST1_VICAP>; 109 reset-names = "srst_csihost_p", 110 "srst_csihost_vicap"; 111 csihost-idx = <1>; 112 rockchip,csi2 = <&mipi1_csi2>; 113 phys = <&mipi_dcphy1>; 114 phy-names = "dcphy"; 115 }; 116 csi2_dphy0 { 117 status = "okay"; 118 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, 119 <&cru PCLK_CSIPHY0>, 120 <&cru PCLK_CSI_HOST_2>; 121 clock-names = "xvclk", 122 "pclk", 123 "pclk_csi2host"; 124 resets = <&cru SRST_CSIPHY0>, 125 <&cru SRST_P_CSIPHY0>, 126 <&cru SRST_P_CSI_HOST_2>, 127 <&cru SRST_CSIHOST2_VICAP>; 128 reset-names = "srst_csiphy", 129 "srst_p_csiphy", 130 "srst_csihost_p", 131 "srst_csihost_vicap"; 132 csihost-idx = <2>; 133 rockchip,dphy-grf = <&mipidphy0_grf>; 134 rockchip,csi2-dphy = <&csi2_dphy0_hw>; 135 rockchip,csi2 = <&mipi2_csi2>; 136 }; 137 /* only rk3588 */ 138 csi2_dphy3 { 139 status = "disabled"; 140 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>, 141 <&cru PCLK_CSIPHY1>, 142 <&cru PCLK_CSI_HOST_4>; 143 clock-names = "xvclk", 144 "pclk", 145 "pclk_csi2host"; 146 resets = <&cru SRST_CSIPHY1>, 147 <&cru SRST_P_CSIPHY1>, 148 <&cru SRST_P_CSI_HOST_4>, 149 <&cru SRST_CSIHOST4_VICAP>; 150 reset-names = "srst_csiphy", 151 "srst_p_csiphy", 152 "srst_csihost_p", 153 "srst_csihost_vicap"; 154 csihost-idx = <4>; 155 rockchip,dphy-grf = <&mipidphy1_grf>; 156 rockchip,csi2-dphy = <&csi2_dphy1_hw>; 157 rockchip,csi2 = <&mipi4_csi2>; 158 }; 159 rkcif_dvp { 160 status = "disabled"; 161 clocks = <&cru CLK_CIFOUT_OUT>; 162 clock-names = "xvclk"; 163 }; 164 }; 165 166 cif_sensor: cif_sensor { 167 compatible = "rockchip,sensor"; 168 status = "okay"; 169 170 nvp6188 { 171 is_front = <0>; 172 status = "okay"; 173 174 /*dphy0*/ 175 powerdown-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; 176 pwdn_active = <1>; 177 mir = <0>; 178 flash_attach = <0>; 179 orientation = <90>; 180 i2c_add = <0x66>; 181 i2c_chl = <7>; 182 cif_chl = <0>; 183 ad_chl = <0>; 184 mclk_rate = <24>; 185 rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; 186 rockchip,camera-module-interface0 = "bt601_8"; 187 rockchip,camera-module-defrect1 = <1280 720 0 0 1280 720>; 188 rockchip,camera-module-interface1 = "bt601_8"; 189 }; 190 }; 191}; 192 193&display_subsystem { 194 memory-region = <&drm_logo>, <&drm_vehicle>; 195 memory-region-names = "drm-logo", "drm-vehicle"; 196}; 197 198&i2c7 { 199 status = "okay"; 200}; 201 202&pinctrl { 203 vehicle { 204 vehicle_gpios: vehicle-gpios { 205 /* gpios */ 206 rockchip,pins = 207 /* car-reverse */ 208 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 209 }; 210 }; 211}; 212