xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 *
 */

/{
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		drm_vehicle: drm-vehicle@20000000{
			compatible = "shared-dma-pool";
			inactive;
			reusable;
			reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M
			linux,cma-default;
		};
	};

	gpio_det: gpio-det {
		compatible = "gpio-detection";
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&vehicle_gpios>;

		car-reverse {
			car-reverse-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
			linux,debounce-ms = <5>;
			label = "car-reverse";
			gpio,wakeup;
		};

	};

	vehicle: vehicle {
		compatible = "rockchip,vehicle";
		status = "okay";

		// pinctrl-names = "default";
		// pinctrl-0 = <&mipim1_camera1_clk>;

		clocks = <&cru ACLK_VICAP>,
			<&cru HCLK_VICAP>,
			<&cru DCLK_VICAP>;
		clock-names = "aclk_cif",
			      "hclk_cif",
			      "dclk_cif";
		resets = <&cru SRST_A_VICAP>,
			<&cru SRST_H_VICAP>,
			<&cru SRST_D_VICAP>;
		reset-names = "rst_cif_a",
			      "rst_cif_h",
			      "rst_cif_d";
		assigned-clocks = <&cru DCLK_VICAP>;
		assigned-clock-rates = <600000000>;
		power-domains = <&power RK3588_PD_VI>;
		cif,drop-frames = <4>; //frames to drop
		cif,chip-id = <1>; /*0:rk3568 1:rk3588*/
		rockchip,grf = <&sys_grf>;
		rockchip,cru = <&cru>;
		rockchip,cif = <&rkcif>;
		rockchip,gpio-det = <&gpio_det>;
		rockchip,cif-sensor = <&cif_sensor>;
		rockchip,cif-phy = <&cif_phy>;
		ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25
		/*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/
		vehicle,rotate-mirror = <0x00>;
		vehicle,crtc_name = "video_port3";
		vehicle,plane_name = "Esmart3-win0";
	};

	cif_phy: cif_phy {
		status = "okay";

		csi2_dcphy0 {
			status = "disabled";
			clocks = <&cru CLK_MIPI_CAMARAOUT_M1>,
				<&cru PCLK_MIPI_DCPHY0>,
				<&cru PCLK_CSI_HOST_0>,
				<&cru ICLK_CSIHOST0>;
			clock-names = "xvclk",
				      "pclk",
				      "pclk_csi2host",
				      "iclk_csi2host";
			resets = <&cru SRST_P_CSI_HOST_0>,
				<&cru SRST_CSIHOST0_VICAP>;
			reset-names = "srst_csihost_p",
				      "srst_csihost_vicap";
			csihost-idx = <0>;
			rockchip,csi2 = <&mipi0_csi2>;
			phys = <&mipi_dcphy0>;
			phy-names = "dcphy";
		};
		csi2_dcphy1 {
			status = "disabled";
			clocks = <&cru CLK_MIPI_CAMARAOUT_M2>,
				<&cru PCLK_MIPI_DCPHY1>,
				<&cru PCLK_CSI_HOST_1>,
				<&cru ICLK_CSIHOST1>;
			clock-names = "xvclk",
				      "pclk",
				      "pclk_csi2host",
				      "iclk_csi2host";
			resets = <&cru SRST_P_CSI_HOST_1>,
				<&cru SRST_CSIHOST1_VICAP>;
			reset-names = "srst_csihost_p",
				      "srst_csihost_vicap";
			csihost-idx = <1>;
			rockchip,csi2 = <&mipi1_csi2>;
			phys = <&mipi_dcphy1>;
			phy-names = "dcphy";
		};
		csi2_dphy0 {
			status = "okay";
			clocks = <&cru CLK_MIPI_CAMARAOUT_M2>,
				 <&cru PCLK_CSIPHY0>,
				 <&cru PCLK_CSI_HOST_2>;
			clock-names = "xvclk",
				      "pclk",
				      "pclk_csi2host";
			resets = <&cru SRST_CSIPHY0>,
				 <&cru SRST_P_CSIPHY0>,
				 <&cru SRST_P_CSI_HOST_2>,
				 <&cru SRST_CSIHOST2_VICAP>;
			reset-names = "srst_csiphy",
				      "srst_p_csiphy",
				      "srst_csihost_p",
				      "srst_csihost_vicap";
			csihost-idx = <2>;
			rockchip,dphy-grf = <&mipidphy0_grf>;
			rockchip,csi2-dphy = <&csi2_dphy0_hw>;
			rockchip,csi2 = <&mipi2_csi2>;
		};
		/* only rk3588 */
		csi2_dphy3 {
			status = "disabled";
			clocks = <&cru CLK_MIPI_CAMARAOUT_M4>,
				<&cru PCLK_CSIPHY1>,
				<&cru PCLK_CSI_HOST_4>;
			clock-names = "xvclk",
				      "pclk",
				      "pclk_csi2host";
			resets = <&cru SRST_CSIPHY1>,
				 <&cru SRST_P_CSIPHY1>,
				 <&cru SRST_P_CSI_HOST_4>,
				 <&cru SRST_CSIHOST4_VICAP>;
			reset-names = "srst_csiphy",
				      "srst_p_csiphy",
				      "srst_csihost_p",
				      "srst_csihost_vicap";
			csihost-idx = <4>;
			rockchip,dphy-grf = <&mipidphy1_grf>;
			rockchip,csi2-dphy = <&csi2_dphy1_hw>;
			rockchip,csi2 = <&mipi4_csi2>;
		};
		rkcif_dvp {
			status = "disabled";
			clocks = <&cru CLK_CIFOUT_OUT>;
			clock-names = "xvclk";
		};
	};

	cif_sensor: cif_sensor {
		compatible = "rockchip,sensor";
		status = "okay";

		nvp6188 {
			is_front = <0>;
			status = "okay";

			/*dphy0*/
			powerdown-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
			pwdn_active = <1>;
			mir = <0>;
			flash_attach = <0>;
			orientation = <90>;
			i2c_add = <0x66>;
			i2c_chl = <7>;
			cif_chl = <0>;
			ad_chl = <0>;
			mclk_rate = <24>;
			rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>;
			rockchip,camera-module-interface0 = "bt601_8";
			rockchip,camera-module-defrect1 = <1280 720 0 0 1280 720>;
			rockchip,camera-module-interface1 = "bt601_8";
		};
	};
};

&display_subsystem {
	memory-region = <&drm_logo>, <&drm_vehicle>;
	memory-region-names = "drm-logo", "drm-vehicle";
};

&i2c7 {
	status = "okay";
};

&pinctrl {
	vehicle {
		vehicle_gpios: vehicle-gpios {
			/* gpios */
			rockchip,pins =
				/* car-reverse */
				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};