1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/suspend/rockchip-rk3288.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 compatible = "rockchip,rk3288"; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 dsi0 = &dsi0; 23 dsi1 = &dsi1; 24 ethernet0 = &gmac; 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 gpio2 = &gpio2; 28 gpio3 = &gpio3; 29 gpio4 = &gpio4; 30 gpio5 = &gpio5; 31 gpio6 = &gpio6; 32 gpio7 = &gpio7; 33 gpio8 = &gpio8; 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 mshc0 = &emmc; 41 mshc1 = &sdmmc; 42 mshc2 = &sdio0; 43 mshc3 = &sdio1; 44 serial0 = &uart0; 45 serial1 = &uart1; 46 serial2 = &uart2; 47 serial3 = &uart3; 48 serial4 = &uart4; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 }; 53 54 arm-pmu { 55 compatible = "arm,cortex-a12-pmu"; 56 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 enable-method = "rockchip,rk3066-smp"; 72 rockchip,pmu = <&pmu>; 73 74 cpu0: cpu@500 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a12"; 77 reg = <0x500>; 78 enable-method = "psci"; 79 resets = <&cru SRST_CORE0>; 80 operating-points-v2 = <&cpu_opp_table>; 81 #cooling-cells = <2>; /* min followed by max */ 82 clock-latency = <40000>; 83 clocks = <&cru ARMCLK>; 84 dynamic-power-coefficient = <370>; 85 }; 86 cpu1: cpu@501 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a12"; 89 reg = <0x501>; 90 enable-method = "psci"; 91 resets = <&cru SRST_CORE1>; 92 operating-points-v2 = <&cpu_opp_table>; 93 #cooling-cells = <2>; /* min followed by max */ 94 clock-latency = <40000>; 95 clocks = <&cru ARMCLK>; 96 dynamic-power-coefficient = <370>; 97 }; 98 cpu2: cpu@502 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a12"; 101 reg = <0x502>; 102 enable-method = "psci"; 103 resets = <&cru SRST_CORE2>; 104 operating-points-v2 = <&cpu_opp_table>; 105 #cooling-cells = <2>; /* min followed by max */ 106 clock-latency = <40000>; 107 clocks = <&cru ARMCLK>; 108 dynamic-power-coefficient = <370>; 109 }; 110 cpu3: cpu@503 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a12"; 113 reg = <0x503>; 114 enable-method = "psci"; 115 resets = <&cru SRST_CORE3>; 116 operating-points-v2 = <&cpu_opp_table>; 117 #cooling-cells = <2>; /* min followed by max */ 118 clock-latency = <40000>; 119 clocks = <&cru ARMCLK>; 120 dynamic-power-coefficient = <370>; 121 }; 122 }; 123 124 cpu_opp_table: cpu-opp-table { 125 compatible = "operating-points-v2"; 126 opp-shared; 127 128 clocks = <&cru PLL_APLL>; 129 rockchip,avs-scale = <17>; 130 rockchip,max-volt = <1350000>; 131 nvmem-cells = <&cpu_leakage>, <&special_function>, 132 <&performance>, <&process_version>, 133 <&performance_w>, <&package_info>; 134 nvmem-cell-names = "leakage", "special", 135 "performance", "process", 136 "performance-w", "package"; 137 rockchip,bin-scaling-sel = < 138 0 17 139 1 25 140 2 27 141 3 31 142 >; 143 rockchip,pvtm-voltage-sel = < 144 0 15300 0 145 15301 16000 1 146 16001 17000 2 147 17001 99999 3 148 >; 149 rockchip,pvtm-freq = <408000>; 150 rockchip,pvtm-volt = <1000000>; 151 rockchip,pvtm-ch = <0 0>; 152 rockchip,pvtm-sample-time = <1000>; 153 rockchip,pvtm-number = <10>; 154 rockchip,pvtm-error = <1000>; 155 rockchip,pvtm-ref-temp = <35>; 156 rockchip,pvtm-temp-prop = <(-18) (-18)>; 157 rockchip,thermal-zone = "cpu-thermal"; 158 159 opp-126000000 { 160 opp-hz = /bits/ 64 <126000000>; 161 opp-microvolt = <950000 950000 1350000>; 162 opp-microvolt-L0 = <950000 950000 1350000>; 163 opp-microvolt-L1 = <950000 950000 1350000>; 164 opp-microvolt-L2 = <950000 950000 1350000>; 165 opp-microvolt-L3 = <950000 950000 1350000>; 166 clock-latency-ns = <40000>; 167 }; 168 opp-216000000 { 169 opp-hz = /bits/ 64 <216000000>; 170 opp-microvolt = <950000 950000 1350000>; 171 opp-microvolt-L0 = <950000 950000 1350000>; 172 opp-microvolt-L1 = <950000 950000 1350000>; 173 opp-microvolt-L2 = <950000 950000 1350000>; 174 opp-microvolt-L3 = <950000 950000 1350000>; 175 clock-latency-ns = <40000>; 176 }; 177 opp-408000000 { 178 opp-hz = /bits/ 64 <408000000>; 179 opp-microvolt = <975000 975000 1350000>; 180 opp-microvolt-L0 = <975000 975000 1350000>; 181 opp-microvolt-L1 = <950000 950000 1350000>; 182 opp-microvolt-L2 = <950000 950000 1350000>; 183 opp-microvolt-L3 = <950000 950000 1350000>; 184 clock-latency-ns = <40000>; 185 }; 186 opp-600000000 { 187 opp-hz = /bits/ 64 <600000000>; 188 opp-microvolt = <975000 975000 1350000>; 189 opp-microvolt-L0 = <975000 975000 1350000>; 190 opp-microvolt-L1 = <950000 950000 1350000>; 191 opp-microvolt-L2 = <950000 950000 1350000>; 192 opp-microvolt-L3 = <950000 950000 1350000>; 193 clock-latency-ns = <40000>; 194 }; 195 opp-696000000 { 196 opp-hz = /bits/ 64 <696000000>; 197 opp-microvolt = <975000 975000 1350000>; 198 opp-microvolt-L0 = <975000 975000 1350000>; 199 opp-microvolt-L1 = <950000 950000 1350000>; 200 opp-microvolt-L2 = <950000 950000 1350000>; 201 opp-microvolt-L3 = <950000 950000 1350000>; 202 clock-latency-ns = <40000>; 203 }; 204 opp-816000000 { 205 opp-hz = /bits/ 64 <816000000>; 206 opp-microvolt = <1075000 1075000 1350000>; 207 opp-microvolt-L0 = <1075000 1075000 1350000>; 208 opp-microvolt-L1 = <1050000 1050000 1350000>; 209 opp-microvolt-L2 = <1000000 1000000 1350000>; 210 opp-microvolt-L3 = <950000 950000 1350000>; 211 clock-latency-ns = <40000>; 212 opp-suspend; 213 }; 214 opp-1008000000 { 215 opp-hz = /bits/ 64 <1008000000>; 216 opp-microvolt = <1150000 1150000 1350000>; 217 opp-microvolt-L0 = <1150000 1150000 1350000>; 218 opp-microvolt-L1 = <1100000 1100000 1350000>; 219 opp-microvolt-L2 = <1050000 1050000 1350000>; 220 opp-microvolt-L3 = <1000000 1000000 1350000>; 221 clock-latency-ns = <40000>; 222 }; 223 opp-1200000000 { 224 opp-hz = /bits/ 64 <1200000000>; 225 opp-microvolt = <1200000 1200000 1350000>; 226 opp-microvolt-L0 = <1200000 1200000 1350000>; 227 opp-microvolt-L1 = <1150000 1150000 1350000>; 228 opp-microvolt-L2 = <1100000 1100000 1350000>; 229 opp-microvolt-L3 = <1050000 1050000 1350000>; 230 clock-latency-ns = <40000>; 231 }; 232 opp-1416000000 { 233 opp-hz = /bits/ 64 <1416000000>; 234 opp-microvolt = <1300000 1300000 1350000>; 235 opp-microvolt-L0 = <1300000 1300000 1350000>; 236 opp-microvolt-L1 = <1250000 1250000 1350000>; 237 opp-microvolt-L2 = <1200000 1200000 1350000>; 238 opp-microvolt-L3 = <1150000 1150000 1350000>; 239 clock-latency-ns = <40000>; 240 }; 241 opp-1512000000 { 242 opp-hz = /bits/ 64 <1512000000>; 243 opp-microvolt = <1350000 1350000 1350000>; 244 opp-microvolt-L0 = <1350000 1350000 1350000>; 245 opp-microvolt-L1 = <1300000 1300000 1350000>; 246 opp-microvolt-L2 = <1250000 1250000 1350000>; 247 opp-microvolt-L3 = <1200000 1200000 1350000>; 248 clock-latency-ns = <40000>; 249 }; 250 opp-1608000000 { 251 opp-hz = /bits/ 64 <1608000000>; 252 opp-microvolt = <1350000 1350000 1350000>; 253 opp-microvolt-L0 = <1350000 1350000 1350000>; 254 opp-microvolt-L1 = <1350000 1350000 1350000>; 255 opp-microvolt-L2 = <1300000 1300000 1350000>; 256 opp-microvolt-L3 = <1250000 1250000 1350000>; 257 clock-latency-ns = <40000>; 258 }; 259 }; 260 261 amba: bus { 262 compatible = "simple-bus"; 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges; 266 267 dmac_peri: dma-controller@ff250000 { 268 compatible = "arm,pl330", "arm,primecell"; 269 reg = <0x0 0xff250000 0x0 0x4000>; 270 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 272 #dma-cells = <1>; 273 arm,pl330-broken-no-flushp; 274 arm,pl330-periph-burst; 275 clocks = <&cru ACLK_DMAC2>; 276 clock-names = "apb_pclk"; 277 }; 278 279 dmac_bus_ns: dma-controller@ff600000 { 280 compatible = "arm,pl330", "arm,primecell"; 281 reg = <0x0 0xff600000 0x0 0x4000>; 282 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 284 #dma-cells = <1>; 285 arm,pl330-broken-no-flushp; 286 arm,pl330-periph-burst; 287 clocks = <&cru ACLK_DMAC1>; 288 clock-names = "apb_pclk"; 289 status = "disabled"; 290 }; 291 292 dmac_bus_s: dma-controller@ffb20000 { 293 compatible = "arm,pl330", "arm,primecell"; 294 reg = <0x0 0xffb20000 0x0 0x4000>; 295 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 297 #dma-cells = <1>; 298 arm,pl330-broken-no-flushp; 299 arm,pl330-periph-burst; 300 clocks = <&cru ACLK_DMAC1>; 301 clock-names = "apb_pclk"; 302 }; 303 }; 304 305 firmware { 306 optee: optee { 307 compatible = "linaro,optee-tz"; 308 method = "smc"; 309 }; 310 }; 311 312 reserved-memory { 313 #address-cells = <2>; 314 #size-cells = <2>; 315 ranges; 316 317 /* 318 * The rk3288 cannot use the memory area above 0xfe000000 319 * for dma operations for some reason. While there is 320 * probably a better solution available somewhere, we 321 * haven't found it yet and while devices with 2GB of ram 322 * are not affected, this issue prevents 4GB from booting. 323 * So to make these devices at least bootable, block 324 * this area for the time being until the real solution 325 * is found. 326 */ 327 dma-unusable@fe000000 { 328 reg = <0x0 0xfe000000 0x0 0x1000000>; 329 }; 330 }; 331 332 xin24m: oscillator { 333 compatible = "fixed-clock"; 334 clock-frequency = <24000000>; 335 clock-output-names = "xin24m"; 336 #clock-cells = <0>; 337 }; 338 339 timer { 340 compatible = "arm,armv7-timer"; 341 arm,cpu-registers-not-fw-configured; 342 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 343 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 344 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 345 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 346 clock-frequency = <24000000>; 347 arm,no-tick-in-suspend; 348 }; 349 350 display-subsystem { 351 compatible = "rockchip,display-subsystem"; 352 ports = <&vopl_out>, <&vopb_out>; 353 }; 354 355 sdmmc: mmc@ff0c0000 { 356 compatible = "rockchip,rk3288-dw-mshc"; 357 max-frequency = <150000000>; 358 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 359 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 360 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 361 fifo-depth = <0x100>; 362 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 363 reg = <0x0 0xff0c0000 0x0 0x4000>; 364 resets = <&cru SRST_MMC0>; 365 reset-names = "reset"; 366 status = "disabled"; 367 }; 368 369 sdio0: mmc@ff0d0000 { 370 compatible = "rockchip,rk3288-dw-mshc"; 371 max-frequency = <150000000>; 372 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 373 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 374 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 375 fifo-depth = <0x100>; 376 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 377 reg = <0x0 0xff0d0000 0x0 0x4000>; 378 resets = <&cru SRST_SDIO0>; 379 reset-names = "reset"; 380 status = "disabled"; 381 }; 382 383 sdio1: mmc@ff0e0000 { 384 compatible = "rockchip,rk3288-dw-mshc"; 385 max-frequency = <150000000>; 386 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 387 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 388 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 389 fifo-depth = <0x100>; 390 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0x0 0xff0e0000 0x0 0x4000>; 392 resets = <&cru SRST_SDIO1>; 393 reset-names = "reset"; 394 status = "disabled"; 395 }; 396 397 emmc: mmc@ff0f0000 { 398 compatible = "rockchip,rk3288-dw-mshc"; 399 max-frequency = <150000000>; 400 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 401 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 402 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 403 fifo-depth = <0x100>; 404 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 405 reg = <0x0 0xff0f0000 0x0 0x4000>; 406 resets = <&cru SRST_EMMC>; 407 reset-names = "reset"; 408 status = "disabled"; 409 }; 410 411 saradc: saradc@ff100000 { 412 compatible = "rockchip,saradc"; 413 reg = <0x0 0xff100000 0x0 0x100>; 414 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 415 #io-channel-cells = <1>; 416 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 417 clock-names = "saradc", "apb_pclk"; 418 resets = <&cru SRST_SARADC>; 419 reset-names = "saradc-apb"; 420 status = "disabled"; 421 }; 422 423 spi0: spi@ff110000 { 424 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 425 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 426 clock-names = "spiclk", "apb_pclk"; 427 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 428 dma-names = "tx", "rx"; 429 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 432 reg = <0x0 0xff110000 0x0 0x1000>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 status = "disabled"; 436 }; 437 438 spi1: spi@ff120000 { 439 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 440 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 441 clock-names = "spiclk", "apb_pclk"; 442 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 443 dma-names = "tx", "rx"; 444 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 447 reg = <0x0 0xff120000 0x0 0x1000>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 status = "disabled"; 451 }; 452 453 spi2: spi@ff130000 { 454 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 455 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 456 clock-names = "spiclk", "apb_pclk"; 457 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 458 dma-names = "tx", "rx"; 459 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 462 reg = <0x0 0xff130000 0x0 0x1000>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c0: i2c@ff650000 { 469 compatible = "rockchip,rk3288-i2c"; 470 reg = <0x0 0xff650000 0x0 0x1000>; 471 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 clock-names = "i2c"; 475 clocks = <&cru PCLK_I2C0>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&i2c0_xfer>; 478 status = "disabled"; 479 }; 480 481 i2c1: i2c@ff140000 { 482 compatible = "rockchip,rk3288-i2c"; 483 reg = <0x0 0xff140000 0x0 0x1000>; 484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clock-names = "i2c"; 488 clocks = <&cru PCLK_I2C1>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&i2c1_xfer>; 491 status = "disabled"; 492 }; 493 494 i2c3: i2c@ff150000 { 495 compatible = "rockchip,rk3288-i2c"; 496 reg = <0x0 0xff150000 0x0 0x1000>; 497 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clock-names = "i2c"; 501 clocks = <&cru PCLK_I2C3>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&i2c3_xfer>; 504 status = "disabled"; 505 }; 506 507 i2c4: i2c@ff160000 { 508 compatible = "rockchip,rk3288-i2c"; 509 reg = <0x0 0xff160000 0x0 0x1000>; 510 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clock-names = "i2c"; 514 clocks = <&cru PCLK_I2C4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2c4_xfer>; 517 status = "disabled"; 518 }; 519 520 i2c5: i2c@ff170000 { 521 compatible = "rockchip,rk3288-i2c"; 522 reg = <0x0 0xff170000 0x0 0x1000>; 523 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clock-names = "i2c"; 527 clocks = <&cru PCLK_I2C5>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&i2c5_xfer>; 530 status = "disabled"; 531 }; 532 533 uart0: serial@ff180000 { 534 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 535 reg = <0x0 0xff180000 0x0 0x100>; 536 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 537 reg-shift = <2>; 538 reg-io-width = <4>; 539 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 540 clock-names = "baudclk", "apb_pclk"; 541 dmas = <&dmac_peri 1>, <&dmac_peri 2>; 542 dma-names = "tx", "rx"; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&uart0_xfer>; 545 status = "disabled"; 546 }; 547 548 uart1: serial@ff190000 { 549 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 550 reg = <0x0 0xff190000 0x0 0x100>; 551 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 552 reg-shift = <2>; 553 reg-io-width = <4>; 554 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 555 clock-names = "baudclk", "apb_pclk"; 556 dmas = <&dmac_peri 3>, <&dmac_peri 4>; 557 dma-names = "tx", "rx"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&uart1_xfer>; 560 status = "disabled"; 561 }; 562 563 uart2: serial@ff690000 { 564 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 565 reg = <0x0 0xff690000 0x0 0x100>; 566 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 567 reg-shift = <2>; 568 reg-io-width = <4>; 569 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 570 clock-names = "baudclk", "apb_pclk"; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&uart2_xfer>; 573 status = "disabled"; 574 }; 575 576 uart3: serial@ff1b0000 { 577 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 578 reg = <0x0 0xff1b0000 0x0 0x100>; 579 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 580 reg-shift = <2>; 581 reg-io-width = <4>; 582 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 583 clock-names = "baudclk", "apb_pclk"; 584 dmas = <&dmac_peri 7>, <&dmac_peri 8>; 585 dma-names = "tx", "rx"; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&uart3_xfer>; 588 status = "disabled"; 589 }; 590 591 uart4: serial@ff1c0000 { 592 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 593 reg = <0x0 0xff1c0000 0x0 0x100>; 594 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 595 reg-shift = <2>; 596 reg-io-width = <4>; 597 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 598 clock-names = "baudclk", "apb_pclk"; 599 dmas = <&dmac_peri 9>, <&dmac_peri 10>; 600 dma-names = "tx", "rx"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&uart4_xfer>; 603 status = "disabled"; 604 }; 605 606 thermal-zones { 607 reserve_thermal: reserve_thermal { 608 polling-delay-passive = <1000>; /* milliseconds */ 609 polling-delay = <5000>; /* milliseconds */ 610 611 thermal-sensors = <&tsadc 0>; 612 }; 613 614 cpu_thermal: cpu-thermal { 615 polling-delay-passive = <100>; /* milliseconds */ 616 polling-delay = <5000>; /* milliseconds */ 617 618 thermal-sensors = <&tsadc 1>; 619 620 trips { 621 cpu_alert0: cpu_alert0 { 622 temperature = <70000>; /* millicelsius */ 623 hysteresis = <2000>; /* millicelsius */ 624 type = "passive"; 625 }; 626 cpu_alert1: cpu_alert1 { 627 temperature = <75000>; /* millicelsius */ 628 hysteresis = <2000>; /* millicelsius */ 629 type = "passive"; 630 }; 631 cpu_crit: cpu_crit { 632 temperature = <90000>; /* millicelsius */ 633 hysteresis = <2000>; /* millicelsius */ 634 type = "critical"; 635 }; 636 }; 637 638 cooling-maps { 639 map0 { 640 trip = <&cpu_alert0>; 641 cooling-device = 642 <&cpu0 THERMAL_NO_LIMIT 6>, 643 <&cpu1 THERMAL_NO_LIMIT 6>, 644 <&cpu2 THERMAL_NO_LIMIT 6>, 645 <&cpu3 THERMAL_NO_LIMIT 6>; 646 }; 647 map1 { 648 trip = <&cpu_alert1>; 649 cooling-device = 650 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 651 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 652 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 653 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 654 }; 655 }; 656 }; 657 658 gpu_thermal: gpu-thermal { 659 polling-delay-passive = <100>; /* milliseconds */ 660 polling-delay = <5000>; /* milliseconds */ 661 662 thermal-sensors = <&tsadc 2>; 663 664 trips { 665 gpu_alert0: gpu_alert0 { 666 temperature = <70000>; /* millicelsius */ 667 hysteresis = <2000>; /* millicelsius */ 668 type = "passive"; 669 }; 670 gpu_crit: gpu_crit { 671 temperature = <90000>; /* millicelsius */ 672 hysteresis = <2000>; /* millicelsius */ 673 type = "critical"; 674 }; 675 }; 676 677 cooling-maps { 678 map0 { 679 trip = <&gpu_alert0>; 680 cooling-device = 681 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 682 }; 683 }; 684 }; 685 }; 686 687 tsadc: tsadc@ff280000 { 688 compatible = "rockchip,rk3288-tsadc"; 689 reg = <0x0 0xff280000 0x0 0x100>; 690 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 692 clock-names = "tsadc", "apb_pclk"; 693 assigned-clocks = <&cru SCLK_TSADC>; 694 assigned-clock-rates = <5000>; 695 resets = <&cru SRST_TSADC>; 696 reset-names = "tsadc-apb"; 697 pinctrl-names = "gpio", "otpout"; 698 pinctrl-0 = <&otp_pin>; 699 pinctrl-1 = <&otp_out>; 700 #thermal-sensor-cells = <1>; 701 rockchip,grf = <&grf>; 702 rockchip,hw-tshut-temp = <95000>; 703 status = "disabled"; 704 }; 705 706 gmac: ethernet@ff290000 { 707 compatible = "rockchip,rk3288-gmac"; 708 reg = <0x0 0xff290000 0x0 0x10000>; 709 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 711 interrupt-names = "macirq", "eth_wake_irq"; 712 rockchip,grf = <&grf>; 713 clocks = <&cru SCLK_MAC>, 714 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 715 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 716 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 717 clock-names = "stmmaceth", 718 "mac_clk_rx", "mac_clk_tx", 719 "clk_mac_ref", "clk_mac_refout", 720 "aclk_mac", "pclk_mac"; 721 resets = <&cru SRST_MAC>; 722 reset-names = "stmmaceth"; 723 status = "disabled"; 724 }; 725 726 usb_host0_ehci: usb@ff500000 { 727 compatible = "generic-ehci"; 728 reg = <0x0 0xff500000 0x0 0x100>; 729 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cru HCLK_USBHOST0>, <&usbphy1>; 731 clock-names = "usbhost", "utmi"; 732 phys = <&usbphy1>; 733 phy-names = "usb"; 734 status = "disabled"; 735 }; 736 737 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 738 usb_host0_ohci: usb@ff520000 { 739 compatible = "generic-ohci"; 740 reg = <0x0 0xff520000 0x0 0x100>; 741 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&cru HCLK_USBHOST0>, <&usbphy1>; 743 clock-names = "usbhost", "utmi"; 744 phys = <&usbphy1>; 745 phy-names = "usb"; 746 status = "disabled"; 747 }; 748 749 usb_host1: usb@ff540000 { 750 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 751 "snps,dwc2"; 752 reg = <0x0 0xff540000 0x0 0x40000>; 753 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cru HCLK_USBHOST1>; 755 clock-names = "otg"; 756 dr_mode = "host"; 757 phys = <&usbphy2>; 758 phy-names = "usb2-phy"; 759 snps,reset-phy-on-wake; 760 status = "disabled"; 761 }; 762 763 usb_otg: usb@ff580000 { 764 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 765 "snps,dwc2"; 766 reg = <0x0 0xff580000 0x0 0x40000>; 767 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cru HCLK_OTG0>; 769 clock-names = "otg"; 770 dr_mode = "otg"; 771 g-np-tx-fifo-size = <16>; 772 g-rx-fifo-size = <280>; 773 g-tx-fifo-size = <256 128 128 64 32 16>; 774 phys = <&usbphy0>; 775 phy-names = "usb2-phy"; 776 status = "disabled"; 777 }; 778 779 usb_hsic: usb@ff5c0000 { 780 compatible = "generic-ehci"; 781 reg = <0x0 0xff5c0000 0x0 0x100>; 782 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&cru HCLK_HSIC>; 784 status = "disabled"; 785 }; 786 787 i2c2: i2c@ff660000 { 788 compatible = "rockchip,rk3288-i2c"; 789 reg = <0x0 0xff660000 0x0 0x1000>; 790 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 clock-names = "i2c"; 794 clocks = <&cru PCLK_I2C2>; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&i2c2_xfer>; 797 status = "disabled"; 798 }; 799 800 pwm0: pwm@ff680000 { 801 compatible = "rockchip,rk3288-pwm"; 802 reg = <0x0 0xff680000 0x0 0x10>; 803 #pwm-cells = <3>; 804 pinctrl-names = "active"; 805 pinctrl-0 = <&pwm0_pin>; 806 clocks = <&cru PCLK_RKPWM>; 807 clock-names = "pwm"; 808 status = "disabled"; 809 }; 810 811 pwm1: pwm@ff680010 { 812 compatible = "rockchip,rk3288-pwm"; 813 reg = <0x0 0xff680010 0x0 0x10>; 814 #pwm-cells = <3>; 815 pinctrl-names = "active"; 816 pinctrl-0 = <&pwm1_pin>; 817 clocks = <&cru PCLK_RKPWM>; 818 clock-names = "pwm"; 819 status = "disabled"; 820 }; 821 822 pwm2: pwm@ff680020 { 823 compatible = "rockchip,rk3288-pwm"; 824 reg = <0x0 0xff680020 0x0 0x10>; 825 #pwm-cells = <3>; 826 pinctrl-names = "active"; 827 pinctrl-0 = <&pwm2_pin>; 828 clocks = <&cru PCLK_RKPWM>; 829 clock-names = "pwm"; 830 status = "disabled"; 831 }; 832 833 pwm3: pwm@ff680030 { 834 compatible = "rockchip,rk3288-pwm"; 835 reg = <0x0 0xff680030 0x0 0x10>; 836 #pwm-cells = <3>; 837 pinctrl-names = "active"; 838 pinctrl-0 = <&pwm3_pin>; 839 clocks = <&cru PCLK_RKPWM>; 840 clock-names = "pwm"; 841 status = "disabled"; 842 }; 843 844 timer: timer@ff6b0000 { 845 compatible = "rockchip,rk3288-timer"; 846 reg = <0x0 0xff6b0000 0x0 0x20>; 847 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cru PCLK_TIMER>, <&xin24m>; 849 clock-names = "pclk", "timer"; 850 }; 851 852 bus_intmem: sram@ff700000 { 853 compatible = "mmio-sram"; 854 reg = <0x0 0xff700000 0x0 0x18000>; 855 #address-cells = <1>; 856 #size-cells = <1>; 857 ranges = <0 0x0 0xff700000 0x18000>; 858 smp-sram@0 { 859 compatible = "rockchip,rk3066-smp-sram"; 860 reg = <0x00 0x10>; 861 }; 862 }; 863 864 pmu_sram: sram@ff720000 { 865 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 866 reg = <0x0 0xff720000 0x0 0x1000>; 867 }; 868 869 pmu: power-management@ff730000 { 870 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 871 reg = <0x0 0xff730000 0x0 0x100>; 872 873 power: power-controller { 874 compatible = "rockchip,rk3288-power-controller"; 875 #power-domain-cells = <1>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 879 assigned-clocks = <&cru SCLK_EDP_24M>; 880 assigned-clock-parents = <&xin24m>; 881 882 /* 883 * Note: Although SCLK_* are the working clocks 884 * of device without including on the NOC, needed for 885 * synchronous reset. 886 * 887 * The clocks on the which NOC: 888 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 889 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 890 * ACLK_RGA is on ACLK_RGA_NIU. 891 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 892 * 893 * Which clock are device clocks: 894 * clocks devices 895 * *_IEP IEP:Image Enhancement Processor 896 * *_ISP ISP:Image Signal Processing 897 * *_VIP VIP:Video Input Processor 898 * *_VOP* VOP:Visual Output Processor 899 * *_RGA RGA 900 * *_EDP* EDP 901 * *_LVDS_* LVDS 902 * *_HDMI HDMI 903 * *_MIPI_* MIPI 904 */ 905 power-domain@RK3288_PD_VIO { 906 reg = <RK3288_PD_VIO>; 907 clocks = <&cru ACLK_IEP>, 908 <&cru ACLK_ISP>, 909 <&cru ACLK_RGA>, 910 <&cru ACLK_VIP>, 911 <&cru ACLK_VOP0>, 912 <&cru ACLK_VOP1>, 913 <&cru DCLK_VOP0>, 914 <&cru DCLK_VOP1>, 915 <&cru HCLK_IEP>, 916 <&cru HCLK_ISP>, 917 <&cru HCLK_RGA>, 918 <&cru HCLK_VIP>, 919 <&cru HCLK_VOP0>, 920 <&cru HCLK_VOP1>, 921 <&cru PCLK_EDP_CTRL>, 922 <&cru PCLK_HDMI_CTRL>, 923 <&cru PCLK_LVDS_PHY>, 924 <&cru PCLK_MIPI_CSI>, 925 <&cru PCLK_MIPI_DSI0>, 926 <&cru PCLK_MIPI_DSI1>, 927 <&cru SCLK_EDP_24M>, 928 <&cru SCLK_EDP>, 929 <&cru SCLK_HDMI_CEC>, 930 <&cru SCLK_ISP_JPE>, 931 <&cru SCLK_ISP>, 932 <&cru SCLK_RGA>; 933 pm_qos = <&qos_vio0_iep>, 934 <&qos_vio1_vop>, 935 <&qos_vio1_isp_w0>, 936 <&qos_vio1_isp_w1>, 937 <&qos_vio0_vop>, 938 <&qos_vio0_vip>, 939 <&qos_vio2_rga_r>, 940 <&qos_vio2_rga_w>, 941 <&qos_vio1_isp_r>; 942 }; 943 944 /* 945 * Note: The following 3 are HEVC(H.265) clocks, 946 * and on the ACLK_HEVC_NIU (NOC). 947 */ 948 power-domain@RK3288_PD_HEVC { 949 reg = <RK3288_PD_HEVC>; 950 clocks = <&cru ACLK_HEVC>, 951 <&cru SCLK_HEVC_CABAC>, 952 <&cru SCLK_HEVC_CORE>; 953 pm_qos = <&qos_hevc_r>, 954 <&qos_hevc_w>; 955 }; 956 957 /* 958 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 959 * (video endecoder & decoder) clocks that on the 960 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 961 */ 962 power-domain@RK3288_PD_VIDEO { 963 reg = <RK3288_PD_VIDEO>; 964 clocks = <&cru ACLK_VCODEC>, 965 <&cru HCLK_VCODEC>; 966 pm_qos = <&qos_video>; 967 }; 968 969 /* 970 * Note: ACLK_GPU is the GPU clock, 971 * and on the ACLK_GPU_NIU (NOC). 972 */ 973 power-domain@RK3288_PD_GPU { 974 reg = <RK3288_PD_GPU>; 975 clocks = <&cru ACLK_GPU>; 976 pm_qos = <&qos_gpu_r>, 977 <&qos_gpu_w>; 978 }; 979 }; 980 981 reboot-mode { 982 compatible = "syscon-reboot-mode"; 983 offset = <0x94>; 984 mode-normal = <BOOT_NORMAL>; 985 mode-recovery = <BOOT_RECOVERY>; 986 mode-bootloader = <BOOT_FASTBOOT>; 987 mode-loader = <BOOT_BL_DOWNLOAD>; 988 mode-ums = <BOOT_UMS>; 989 }; 990 }; 991 992 sgrf: syscon@ff740000 { 993 compatible = "rockchip,rk3288-sgrf", "syscon"; 994 reg = <0x0 0xff740000 0x0 0x1000>; 995 }; 996 997 cru: clock-controller@ff760000 { 998 compatible = "rockchip,rk3288-cru"; 999 reg = <0x0 0xff760000 0x0 0x1000>; 1000 rockchip,grf = <&grf>; 1001 #clock-cells = <1>; 1002 #reset-cells = <1>; 1003 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>, 1004 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 1005 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 1006 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 1007 <&cru ACLK_VIO0>, <&cru ACLK_VIO1>; 1008 assigned-clock-rates = <594000000>, <500000000>, 1009 <300000000>, <150000000>, 1010 <75000000>, <300000000>, 1011 <150000000>, <75000000>, 1012 <594000000>, <297000000>; 1013 }; 1014 1015 grf: syscon@ff770000 { 1016 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 1017 reg = <0x0 0xff770000 0x0 0x1000>; 1018 1019 edp_phy: edp-phy { 1020 compatible = "rockchip,rk3288-dp-phy"; 1021 clocks = <&cru SCLK_EDP_24M>; 1022 clock-names = "24m"; 1023 #phy-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 io_domains: io-domains { 1028 compatible = "rockchip,rk3288-io-voltage-domain"; 1029 status = "disabled"; 1030 }; 1031 1032 mipi_phy_rx0: mipi-phy-rx0 { 1033 compatible = "rockchip,rk3288-mipi-dphy"; 1034 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>; 1035 clock-names = "dphy-ref", "pclk"; 1036 status = "disabled"; 1037 }; 1038 1039 lvds: lvds { 1040 compatible = "rockchip,rk3288-lvds"; 1041 phys = <&video_phy>; 1042 phy-names = "phy"; 1043 status = "disabled"; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 port@0 { 1050 reg = <0>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 lvds_in_vopb: endpoint@0 { 1055 reg = <0>; 1056 remote-endpoint = <&vopb_out_lvds>; 1057 }; 1058 1059 lvds_in_vopl: endpoint@1 { 1060 reg = <1>; 1061 remote-endpoint = <&vopl_out_lvds>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 rgb: rgb { 1068 compatible = "rockchip,rk3288-rgb"; 1069 pinctrl-names = "default", "sleep"; 1070 pinctrl-0 = <&lcdc_rgb_pins>; 1071 pinctrl-1 = <&lcdc_sleep_pins>; 1072 phys = <&video_phy>; 1073 phy-names = "phy"; 1074 status = "disabled"; 1075 1076 ports { 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 1080 port@0 { 1081 reg = <0>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 rgb_in_vopb: endpoint@0 { 1086 reg = <0>; 1087 remote-endpoint = <&vopb_out_rgb>; 1088 }; 1089 1090 rgb_in_vopl: endpoint@1 { 1091 reg = <1>; 1092 remote-endpoint = <&vopl_out_rgb>; 1093 }; 1094 }; 1095 }; 1096 }; 1097 1098 usbphy: usbphy { 1099 compatible = "rockchip,rk3288-usb-phy"; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 status = "disabled"; 1103 1104 usbphy0: usb-phy@320 { 1105 #phy-cells = <0>; 1106 reg = <0x320>; 1107 clocks = <&cru SCLK_OTGPHY0>; 1108 clock-names = "phyclk"; 1109 #clock-cells = <0>; 1110 resets = <&cru SRST_USBOTG_PHY>; 1111 reset-names = "phy-reset"; 1112 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1113 interrupt-names = "otg-bvalid"; 1114 }; 1115 1116 usbphy1: usb-phy@334 { 1117 #phy-cells = <0>; 1118 reg = <0x334>; 1119 clocks = <&cru SCLK_OTGPHY1>; 1120 clock-names = "phyclk"; 1121 #clock-cells = <0>; 1122 resets = <&cru SRST_USBHOST0_PHY>; 1123 reset-names = "phy-reset"; 1124 }; 1125 1126 usbphy2: usb-phy@348 { 1127 #phy-cells = <0>; 1128 reg = <0x348>; 1129 clocks = <&cru SCLK_OTGPHY2>; 1130 clock-names = "phyclk"; 1131 #clock-cells = <0>; 1132 resets = <&cru SRST_USBHOST1_PHY>; 1133 reset-names = "phy-reset"; 1134 }; 1135 }; 1136 1137 pvtm: pvtm { 1138 compatible = "rockchip,rk3288-pvtm"; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "okay"; 1142 1143 pvtm@0 { 1144 reg = <0>; 1145 clocks = <&cru SCLK_PVTM_CORE>; 1146 clock-names = "clk"; 1147 resets = <&cru SRST_CORE_PVTM>; 1148 reset-names = "rst"; 1149 }; 1150 pvtm@1 { 1151 reg = <1>; 1152 clocks = <&cru SCLK_PVTM_GPU>; 1153 clock-names = "clk"; 1154 resets = <&cru SRST_GPU_PVTM>; 1155 reset-names = "rst"; 1156 }; 1157 }; 1158 }; 1159 1160 wdt: watchdog@ff800000 { 1161 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 1162 reg = <0x0 0xff800000 0x0 0x100>; 1163 clocks = <&cru PCLK_WDT>; 1164 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1165 status = "disabled"; 1166 }; 1167 1168 spdif_2ch: sound@ff880000 { 1169 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 1170 reg = <0x0 0xff880000 0x0 0x10000>; 1171 #sound-dai-cells = <0>; 1172 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 1173 clock-names = "mclk", "hclk"; 1174 dmas = <&dmac_bus_s 2>; 1175 dma-names = "tx"; 1176 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&spdif_tx>; 1179 rockchip,grf = <&grf>; 1180 status = "disabled"; 1181 }; 1182 1183 i2s: i2s@ff890000 { 1184 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 1185 reg = <0x0 0xff890000 0x0 0x10000>; 1186 #sound-dai-cells = <0>; 1187 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 1189 clock-names = "i2s_clk", "i2s_hclk"; 1190 assigned-clocks = <&cru SCLK_I2S_SRC>; 1191 assigned-clock-parents = <&cru PLL_GPLL>; 1192 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 1193 dma-names = "tx", "rx"; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&i2s0_bus>; 1196 resets = <&cru SRST_I2S0>; 1197 reset-names = "reset-m"; 1198 rockchip,playback-channels = <8>; 1199 rockchip,capture-channels = <2>; 1200 status = "disabled"; 1201 }; 1202 1203 rng: rng@ff8a0000 { 1204 compatible = "rockchip,cryptov1-rng"; 1205 reg = <0x0 0xff8a0000 0x0 0x4000>; 1206 clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1207 clock-names = "clk_crypto", "hclk_crypto"; 1208 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1209 assigned-clock-rates = <150000000>, <100000000>; 1210 status = "disabled"; 1211 }; 1212 1213 crypto: crypto@ff8a0000 { 1214 compatible = "rockchip,rk3288-crypto"; 1215 reg = <0x0 0xff8a0000 0x0 0x4000>; 1216 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 1218 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 1219 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 1220 resets = <&cru SRST_CRYPTO>; 1221 reset-names = "crypto-rst"; 1222 status = "disabled"; 1223 }; 1224 1225 spdif: sound@ff8b0000 { 1226 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 1227 reg = <0x0 0xff8b0000 0x0 0x10000>; 1228 #sound-dai-cells = <0>; 1229 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 1230 clock-names = "mclk", "hclk"; 1231 dmas = <&dmac_bus_s 3>; 1232 dma-names = "tx"; 1233 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&spdif_tx>; 1236 rockchip,grf = <&grf>; 1237 status = "disabled"; 1238 }; 1239 1240 iep: iep@ff90000 { 1241 compatible = "rockchip,iep"; 1242 iommu_enabled = <1>; 1243 iommus = <&iep_mmu>; 1244 reg = <0x0 0xff900000 0x0 0x800>; 1245 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1247 clock-names = "aclk_iep", "hclk_iep"; 1248 power-domains = <&power RK3288_PD_VIO>; 1249 allocator = <1>; 1250 version = <1>; 1251 status = "disabled"; 1252 }; 1253 1254 iep_mmu: iommu@ff900800 { 1255 compatible = "rockchip,iommu"; 1256 reg = <0x0 0xff900800 0x0 0x40>; 1257 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1258 interrupt-names = "iep_mmu"; 1259 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1260 clock-names = "aclk", "iface"; 1261 #iommu-cells = <0>; 1262 status = "disabled"; 1263 }; 1264 1265 isp: isp@ff910000 { 1266 compatible = "rockchip,rk3288-isp", "rockchip,isp"; 1267 reg = <0x0 0xff910000 0x0 0x4000>; 1268 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&power RK3288_PD_VIO>; 1270 clocks = 1271 <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, 1272 <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>, 1273 <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>, 1274 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>; 1275 clock-names = 1276 "aclk_isp", "hclk_isp", "clk_isp", 1277 "clk_isp_jpe", "pclkin_isp", "clk_cif_out", 1278 "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1"; 1279 pinctrl-names = 1280 "default", "isp_dvp8bit2", "isp_dvp10bit", 1281 "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", 1282 "isp_mipi_fl_prefl", "isp_flash_as_gpio", 1283 "isp_flash_as_trigger_out"; 1284 pinctrl-0 = <&isp_mipi>; 1285 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>; 1286 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>; 1287 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 1288 &isp_dvp_d10d11>; 1289 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>; 1290 pinctrl-5 = <&isp_mipi>; 1291 pinctrl-6 = <&isp_mipi &isp_prelight>; 1292 pinctrl-7 = <&isp_flash_trigger_as_gpio>; 1293 pinctrl-8 = <&isp_flash_trigger>; 1294 rockchip,isp,mipiphy = <2>; 1295 rockchip,isp,cifphy = <1>; 1296 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>; 1297 rockchip,grf = <&grf>; 1298 rockchip,cru = <&cru>; 1299 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; 1300 rockchip,isp,iommu_enable = <1>; 1301 iommus = <&isp_mmu>; 1302 status = "disabled"; 1303 }; 1304 1305 rkisp1: rkisp1@ff910000 { 1306 compatible = "rockchip,rk3288-rkisp1"; 1307 reg = <0x0 0xff910000 0x0 0x4000>; 1308 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1309 interrupt-names = "isp_irq"; 1310 clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>, 1311 <&cru HCLK_ISP>, <&cru PCLK_ISP_IN>, 1312 <&cru SCLK_ISP_JPE>; 1313 clock-names = "clk_isp", "aclk_isp", 1314 "hclk_isp", "pclk_isp_in", 1315 "sclk_isp_jpe"; 1316 assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>; 1317 assigned-clock-rates = <400000000>, <400000000>; 1318 power-domains = <&power RK3288_PD_VIO>; 1319 iommus = <&isp_mmu>; 1320 status = "disabled"; 1321 }; 1322 1323 isp_mmu: iommu@ff914000 { 1324 compatible = "rockchip,iommu"; 1325 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1326 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "isp_mmu"; 1328 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1329 clock-names = "aclk", "iface"; 1330 #iommu-cells = <0>; 1331 rockchip,disable-mmu-reset; 1332 status = "disabled"; 1333 }; 1334 1335 rga: rga@ff920000 { 1336 compatible = "rockchip,rk3288-rga"; 1337 reg = <0x0 0xff920000 0x0 0x180>; 1338 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1340 clock-names = "aclk", "hclk", "sclk"; 1341 power-domains = <&power RK3288_PD_VIO>; 1342 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1343 reset-names = "core", "axi", "ahb"; 1344 status = "disabled"; 1345 }; 1346 1347 vopb: vop@ff930000 { 1348 compatible = "rockchip,rk3288-vop-big"; 1349 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1350 reg-names = "regs", "gamma_lut"; 1351 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1353 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1354 power-domains = <&power RK3288_PD_VIO>; 1355 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1356 reset-names = "axi", "ahb", "dclk"; 1357 iommus = <&vopb_mmu>; 1358 status = "disabled"; 1359 1360 vopb_out: port { 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 vopb_out_hdmi: endpoint@0 { 1365 reg = <0>; 1366 remote-endpoint = <&hdmi_in_vopb>; 1367 }; 1368 1369 vopb_out_edp: endpoint@1 { 1370 reg = <1>; 1371 remote-endpoint = <&edp_in_vopb>; 1372 }; 1373 1374 vopb_out_dsi0: endpoint@2 { 1375 reg = <2>; 1376 remote-endpoint = <&dsi0_in_vopb>; 1377 }; 1378 1379 vopb_out_dsi1: endpoint@3 { 1380 reg = <3>; 1381 remote-endpoint = <&dsi1_in_vopb>; 1382 }; 1383 1384 vopb_out_lvds: endpoint@4 { 1385 reg = <4>; 1386 remote-endpoint = <&lvds_in_vopb>; 1387 }; 1388 1389 vopb_out_rgb: endpoint@5 { 1390 reg = <5>; 1391 remote-endpoint = <&rgb_in_vopb>; 1392 }; 1393 }; 1394 }; 1395 1396 vopb_mmu: iommu@ff930300 { 1397 compatible = "rockchip,iommu"; 1398 reg = <0x0 0xff930300 0x0 0x100>; 1399 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "vopb_mmu"; 1401 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1402 clock-names = "aclk", "iface"; 1403 power-domains = <&power RK3288_PD_VIO>; 1404 #iommu-cells = <0>; 1405 rockchip,disable-device-link-resume; 1406 status = "disabled"; 1407 }; 1408 1409 vopl: vop@ff940000 { 1410 compatible = "rockchip,rk3288-vop-lit"; 1411 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1412 reg-names = "regs", "gamma_lut"; 1413 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1414 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1415 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1416 power-domains = <&power RK3288_PD_VIO>; 1417 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1418 reset-names = "axi", "ahb", "dclk"; 1419 iommus = <&vopl_mmu>; 1420 status = "disabled"; 1421 1422 vopl_out: port { 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 vopl_out_hdmi: endpoint@0 { 1427 reg = <0>; 1428 remote-endpoint = <&hdmi_in_vopl>; 1429 }; 1430 1431 vopl_out_edp: endpoint@1 { 1432 reg = <1>; 1433 remote-endpoint = <&edp_in_vopl>; 1434 }; 1435 1436 vopl_out_dsi0: endpoint@2 { 1437 reg = <2>; 1438 remote-endpoint = <&dsi0_in_vopl>; 1439 }; 1440 1441 vopl_out_dsi1: endpoint@3 { 1442 reg = <3>; 1443 remote-endpoint = <&dsi1_in_vopl>; 1444 }; 1445 1446 vopl_out_lvds: endpoint@4 { 1447 reg = <4>; 1448 remote-endpoint = <&lvds_in_vopl>; 1449 }; 1450 1451 vopl_out_rgb: endpoint@5 { 1452 reg = <5>; 1453 remote-endpoint = <&rgb_in_vopl>; 1454 }; 1455 }; 1456 }; 1457 1458 vopl_mmu: iommu@ff940300 { 1459 compatible = "rockchip,iommu"; 1460 reg = <0x0 0xff940300 0x0 0x100>; 1461 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1462 interrupt-names = "vopl_mmu"; 1463 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1464 clock-names = "aclk", "iface"; 1465 power-domains = <&power RK3288_PD_VIO>; 1466 #iommu-cells = <0>; 1467 rockchip,disable-device-link-resume; 1468 status = "disabled"; 1469 }; 1470 1471 cif: cif@ff950000 { 1472 compatible = "rockchip,cif", "rockchip,rk3288-cif"; 1473 reg = <0x0 0xff950000 0x0 0x400>; 1474 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>, 1476 <&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>; 1477 clock-names = "aclk_cif0", "hclk_cif0", 1478 "cif0_in", "cif0_out"; 1479 resets = <&cru SRST_VIP>; 1480 reset-names = "rst_cif"; 1481 pinctrl-names = "cif_pin_all"; 1482 pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>; 1483 rockchip,grf = <&grf>; 1484 rockchip,cru = <&cru>; 1485 power-domains = <&power RK3288_PD_VIO>; 1486 status = "disabled"; 1487 }; 1488 1489 dsi0: dsi@ff960000 { 1490 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1491 reg = <0x0 0xff960000 0x0 0x4000>; 1492 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1493 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1494 clock-names = "ref", "pclk"; 1495 resets = <&cru SRST_MIPIDSI0>; 1496 reset-names = "apb"; 1497 power-domains = <&power RK3288_PD_VIO>; 1498 rockchip,grf = <&grf>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 status = "disabled"; 1502 1503 ports { 1504 mipi_in: port { 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 dsi0_in_vopb: endpoint@0 { 1508 reg = <0>; 1509 remote-endpoint = <&vopb_out_dsi0>; 1510 }; 1511 dsi0_in_vopl: endpoint@1 { 1512 reg = <1>; 1513 remote-endpoint = <&vopl_out_dsi0>; 1514 }; 1515 }; 1516 }; 1517 }; 1518 1519 dsi1: dsi@ff964000 { 1520 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1521 reg = <0x0 0xff964000 0x0 0x4000>; 1522 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1523 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>; 1524 clock-names = "ref", "pclk"; 1525 resets = <&cru SRST_MIPIDSI1>; 1526 reset-names = "apb"; 1527 power-domains = <&power RK3288_PD_VIO>; 1528 rockchip,grf = <&grf>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 1533 ports { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 dsi1_in: port { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 dsi1_in_vopb: endpoint@0 { 1542 reg = <0>; 1543 remote-endpoint = <&vopb_out_dsi1>; 1544 }; 1545 dsi1_in_vopl: endpoint@1 { 1546 reg = <1>; 1547 remote-endpoint = <&vopl_out_dsi1>; 1548 }; 1549 }; 1550 }; 1551 }; 1552 1553 video_phy: video-phy@ff96c000 { 1554 compatible = "rockchip,rk3288-video-phy"; 1555 reg = <0x0 0xff96c000 0x0 0x4000>; 1556 clocks = <&cru PCLK_LVDS_PHY>; 1557 clock-names = "pclk"; 1558 resets = <&cru SRST_LVDS_PHY>; 1559 reset-names = "rst"; 1560 power-domains = <&power RK3288_PD_VIO>; 1561 #phy-cells = <0>; 1562 status = "disabled"; 1563 }; 1564 1565 edp: dp@ff970000 { 1566 compatible = "rockchip,rk3288-dp"; 1567 reg = <0x0 0xff970000 0x0 0x4000>; 1568 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1569 clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>, 1570 <&cru SCLK_EDP>; 1571 clock-names = "dp", "pclk", "spdif"; 1572 assigned-clocks = <&cru SCLK_EDP_24M>; 1573 assigned-clock-parents = <&xin24m>; 1574 power-domains = <&power RK3288_PD_VIO>; 1575 resets = <&cru SRST_EDP>; 1576 reset-names = "dp"; 1577 rockchip,grf = <&grf>; 1578 status = "disabled"; 1579 1580 ports { 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 edp_in: port@0 { 1584 reg = <0>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 edp_in_vopb: endpoint@0 { 1588 reg = <0>; 1589 remote-endpoint = <&vopb_out_edp>; 1590 }; 1591 edp_in_vopl: endpoint@1 { 1592 reg = <1>; 1593 remote-endpoint = <&vopl_out_edp>; 1594 }; 1595 }; 1596 }; 1597 }; 1598 1599 hdmi: hdmi@ff980000 { 1600 compatible = "rockchip,rk3288-dw-hdmi"; 1601 reg = <0x0 0xff980000 0x0 0x20000>; 1602 reg-io-width = <4>; 1603 #sound-dai-cells = <0>; 1604 rockchip,grf = <&grf>; 1605 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1607 clock-names = "iahb", "isfr", "cec"; 1608 pinctrl-names = "default", "sleep"; 1609 pinctrl-0 = <&hdmi_ddc>; 1610 pinctrl-1 = <&hdmi_gpio>; 1611 power-domains = <&power RK3288_PD_VIO>; 1612 unsupported-yuv-input; 1613 status = "disabled"; 1614 1615 ports { 1616 hdmi_in: port { 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 hdmi_in_vopb: endpoint@0 { 1620 reg = <0>; 1621 remote-endpoint = <&vopb_out_hdmi>; 1622 }; 1623 hdmi_in_vopl: endpoint@1 { 1624 reg = <1>; 1625 remote-endpoint = <&vopl_out_hdmi>; 1626 }; 1627 }; 1628 }; 1629 }; 1630 1631 vpu: video-codec@ff9a0000 { 1632 compatible = "rockchip,rk3288-vpu"; 1633 reg = <0x0 0xff9a0000 0x0 0x800>; 1634 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1636 interrupt-names = "vepu", "vdpu"; 1637 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1638 clock-names = "aclk", "hclk"; 1639 iommus = <&vpu_mmu>; 1640 power-domains = <&power RK3288_PD_VIDEO>; 1641 status = "disabled"; 1642 }; 1643 1644 mpp_srv: mpp-srv { 1645 compatible = "rockchip,mpp-service"; 1646 rockchip,taskqueue-count = <2>; 1647 rockchip,resetgroup-count = <2>; 1648 status = "disabled"; 1649 }; 1650 1651 vepu: vepu@ff9a0000 { 1652 compatible = "rockchip,vpu-encoder-v1"; 1653 reg = <0x0 0xff9a0000 0x0 0x400>; 1654 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "irq_enc"; 1656 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1657 clock-names = "aclk_vcodec", "hclk_vcodec"; 1658 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>; 1659 reset-names = "shared_video_a", "shared_video_h"; 1660 assigned-clocks = <&cru ACLK_VCODEC>; 1661 assigned-clock-rates = <400000000>; 1662 iommus = <&vpu_mmu>; 1663 power-domains = <&power RK3288_PD_VIDEO>; 1664 rockchip,srv = <&mpp_srv>; 1665 rockchip,taskqueue-node = <0>; 1666 rockchip,resetgroup-node = <0>; 1667 status = "disabled"; 1668 }; 1669 1670 vdpu: vdpu@ff9a0400 { 1671 compatible = "rockchip,vpu-decoder-rk3288", "rockchip,vpu-decoder-v1"; 1672 reg = <0x0 0xff9a0400 0x0 0x400>; 1673 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1674 interrupt-names = "irq_dec"; 1675 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1676 clock-names = "aclk_vcodec", "hclk_vcodec"; 1677 rockchip,normal-rates = <300000000>, <0>; 1678 rockchip,advanced-rates = <600000000>, <0>; 1679 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>; 1680 reset-names = "shared_video_a", "shared_video_h"; 1681 assigned-clocks = <&cru ACLK_VCODEC>; 1682 assigned-clock-rates = <400000000>; 1683 iommus = <&vpu_mmu>; 1684 power-domains = <&power RK3288_PD_VIDEO>; 1685 rockchip,srv = <&mpp_srv>; 1686 rockchip,taskqueue-node = <0>; 1687 rockchip,resetgroup-node = <0>; 1688 status = "disabled"; 1689 }; 1690 1691 vpu_mmu: iommu@ff9a0800 { 1692 compatible = "rockchip,iommu"; 1693 reg = <0x0 0xff9a0800 0x0 0x100>; 1694 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1695 interrupt-names = "vpu_mmu"; 1696 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1697 clock-names = "aclk", "iface"; 1698 #iommu-cells = <0>; 1699 power-domains = <&power RK3288_PD_VIDEO>; 1700 status = "disabled"; 1701 }; 1702 1703 hevc: hevc_service@ff9c0000 { 1704 compatible = "rockchip,hevc-decoder"; 1705 reg = <0x0 0xff9c0000 0x0 0x400>; 1706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1707 interrupt-names = "irq_dec"; 1708 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CORE>, 1709 <&cru SCLK_HEVC_CABAC>; 1710 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", 1711 "clk_cabac"; 1712 rockchip,normal-rates = <300000000>, <0>, <200000000>, 1713 <200000000>; 1714 rockchip,advanced-rates = <500000000>, <0>, <400000000>, 1715 <400000000>; 1716 rockchip,default-max-load = <2088960>; 1717 resets = <&cru SRST_HEVC>; 1718 reset-names = "video_core"; 1719 1720 /* 1721 * The 4K hevc would also work well with 500/125/300/300, 1722 * no more err irq and reset request. 1723 */ 1724 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, 1725 <&cru SCLK_HEVC_CORE>, 1726 <&cru SCLK_HEVC_CABAC>; 1727 assigned-clock-rates = <400000000>, <100000000>, 1728 <300000000>, <300000000>; 1729 iommus = <&hevc_mmu>; 1730 rockchip,srv = <&mpp_srv>; 1731 rockchip,taskqueue-node = <1>; 1732 rockchip,resetgroup-node = <1>; 1733 power-domains = <&power RK3288_PD_HEVC>; 1734 status = "disabled"; 1735 }; 1736 1737 hevc_mmu: iommu@ff9c0440 { 1738 compatible = "rockchip,iommu"; 1739 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1740 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1741 interrupt-names = "hevc_mmu"; 1742 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1743 clock-names = "aclk", "iface"; 1744 power-domains = <&power RK3288_PD_HEVC>; 1745 #iommu-cells = <0>; 1746 status = "disabled"; 1747 }; 1748 1749 gpu: gpu@ffa30000 { 1750 compatible = "rockchip,rk3288-mali", "arm,mali-t760", 1751 "arm,malit764", "arm,malit76x", "arm,malit7xx", 1752 "arm,mali-midgard"; 1753 reg = <0x0 0xffa30000 0x0 0x10000>; 1754 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1757 interrupt-names = "job", "mmu", "gpu"; 1758 clocks = <&cru ACLK_GPU>; 1759 clock-names = "clk_mali"; 1760 operating-points-v2 = <&gpu_opp_table>; 1761 #cooling-cells = <2>; /* min followed by max */ 1762 power-domains = <&power RK3288_PD_GPU>; 1763 status = "disabled"; 1764 1765 upthreshold = <75>; 1766 downdifferential = <10>; 1767 1768 gpu_power_model: power_model { 1769 compatible = "arm,mali-simple-power-model"; 1770 static-coefficient = <411000>; 1771 dynamic-coefficient = <733>; 1772 ts = <32000 4700 (-80) 2>; 1773 thermal-zone = "gpu-thermal"; 1774 }; 1775 }; 1776 1777 gpu_opp_table: gpu-opp-table { 1778 compatible = "operating-points-v2"; 1779 1780 clocks = <&cru PLL_GPLL>; 1781 nvmem-cells = <&performance>, <&performance_w>; 1782 nvmem-cell-names = "performance", "performance-w"; 1783 rockchip,bin-scaling-sel = < 1784 0 55 1785 1 59 1786 2 61 1787 3 61 1788 >; 1789 1790 opp-100000000 { 1791 opp-hz = /bits/ 64 <100000000>; 1792 opp-microvolt = <950000>; 1793 }; 1794 opp-200000000 { 1795 opp-hz = /bits/ 64 <200000000>; 1796 opp-microvolt = <950000>; 1797 }; 1798 opp-300000000 { 1799 opp-hz = /bits/ 64 <300000000>; 1800 opp-microvolt = <1000000>; 1801 }; 1802 opp-420000000 { 1803 opp-hz = /bits/ 64 <420000000>; 1804 opp-microvolt = <1100000>; 1805 }; 1806 opp-600000000 { 1807 opp-hz = /bits/ 64 <600000000>; 1808 opp-microvolt = <1250000>; 1809 }; 1810 }; 1811 1812 qos_gpu_r: qos@ffaa0000 { 1813 compatible = "syscon"; 1814 reg = <0x0 0xffaa0000 0x0 0x20>; 1815 }; 1816 1817 qos_gpu_w: qos@ffaa0080 { 1818 compatible = "syscon"; 1819 reg = <0x0 0xffaa0080 0x0 0x20>; 1820 }; 1821 1822 qos_vio1_vop: qos@ffad0000 { 1823 compatible = "syscon"; 1824 reg = <0x0 0xffad0000 0x0 0x20>; 1825 }; 1826 1827 qos_vio1_isp_w0: qos@ffad0100 { 1828 compatible = "syscon"; 1829 reg = <0x0 0xffad0100 0x0 0x20>; 1830 }; 1831 1832 qos_vio1_isp_w1: qos@ffad0180 { 1833 compatible = "syscon"; 1834 reg = <0x0 0xffad0180 0x0 0x20>; 1835 }; 1836 1837 qos_vio0_vop: qos@ffad0400 { 1838 compatible = "syscon"; 1839 reg = <0x0 0xffad0400 0x0 0x20>; 1840 }; 1841 1842 qos_vio0_vip: qos@ffad0480 { 1843 compatible = "syscon"; 1844 reg = <0x0 0xffad0480 0x0 0x20>; 1845 }; 1846 1847 qos_vio0_iep: qos@ffad0500 { 1848 compatible = "syscon"; 1849 reg = <0x0 0xffad0500 0x0 0x20>; 1850 }; 1851 1852 qos_vio2_rga_r: qos@ffad0800 { 1853 compatible = "syscon"; 1854 reg = <0x0 0xffad0800 0x0 0x20>; 1855 }; 1856 1857 qos_vio2_rga_w: qos@ffad0880 { 1858 compatible = "syscon"; 1859 reg = <0x0 0xffad0880 0x0 0x20>; 1860 }; 1861 1862 qos_vio1_isp_r: qos@ffad0900 { 1863 compatible = "syscon"; 1864 reg = <0x0 0xffad0900 0x0 0x20>; 1865 }; 1866 1867 qos_video: qos@ffae0000 { 1868 compatible = "syscon"; 1869 reg = <0x0 0xffae0000 0x0 0x20>; 1870 }; 1871 1872 qos_hevc_r: qos@ffaf0000 { 1873 compatible = "syscon"; 1874 reg = <0x0 0xffaf0000 0x0 0x20>; 1875 }; 1876 1877 qos_hevc_w: qos@ffaf0080 { 1878 compatible = "syscon"; 1879 reg = <0x0 0xffaf0080 0x0 0x20>; 1880 }; 1881 1882 efuse: efuse@ffb40000 { 1883 compatible = "rockchip,rk3288-efuse"; 1884 reg = <0x0 0xffb40000 0x0 0x20>; 1885 #address-cells = <1>; 1886 #size-cells = <1>; 1887 clocks = <&cru PCLK_EFUSE256>; 1888 clock-names = "pclk_efuse"; 1889 1890 special_function: special-function@5 { 1891 reg = <0x5 0x1>; 1892 bits = <4 4>; 1893 }; 1894 package_info: package-info@5 { 1895 reg = <0x5 0x1>; 1896 bits = <2 2>; 1897 }; 1898 process_version: process-version@6 { 1899 reg = <0x6 0x1>; 1900 bits = <0 4>; 1901 }; 1902 cpu_id: cpu-id@7 { 1903 reg = <0x07 0x10>; 1904 }; 1905 cpu_leakage: cpu_leakage@17 { 1906 reg = <0x17 0x1>; 1907 }; 1908 performance_w: performance@1c { 1909 reg = <0x1c 0x1>; 1910 bits = <4 3>; 1911 }; 1912 performance: performance@1d { 1913 reg = <0x1d 0x1>; 1914 bits = <4 3>; 1915 }; 1916 }; 1917 1918 gic: interrupt-controller@ffc01000 { 1919 compatible = "arm,gic-400"; 1920 interrupt-controller; 1921 #interrupt-cells = <3>; 1922 #address-cells = <0>; 1923 1924 reg = <0x0 0xffc01000 0x0 0x1000>, 1925 <0x0 0xffc02000 0x0 0x2000>, 1926 <0x0 0xffc04000 0x0 0x2000>, 1927 <0x0 0xffc06000 0x0 0x2000>; 1928 interrupts = <GIC_PPI 9 0xf04>; 1929 }; 1930 1931 rockchip_system_monitor: rockchip-system-monitor { 1932 compatible = "rockchip,system-monitor"; 1933 }; 1934 1935 rockchip_suspend: rockchip-suspend { 1936 compatible = "rockchip,pm-rk3288"; 1937 status = "disabled"; 1938 rockchip,sleep-mode-config = < 1939 (0 1940 |RKPM_CTR_PWR_DMNS 1941 |RKPM_CTR_GTCLKS 1942 |RKPM_CTR_PLLS 1943 |RKPM_CTR_ARMOFF_LPMD 1944 |RKPM_CTR_SYSCLK_OSC_DIS 1945 ) 1946 >; 1947 rockchip,wakeup-config = < 1948 (0 1949 | RKPM_GPIO_WKUP_EN 1950 ) 1951 >; 1952 rockchip,pwm-regulator-config = < 1953 (0 1954 | PWM2_REGULATOR_EN 1955 ) 1956 >; 1957 }; 1958 1959 pinctrl: pinctrl { 1960 compatible = "rockchip,rk3288-pinctrl"; 1961 rockchip,grf = <&grf>; 1962 rockchip,pmu = <&pmu>; 1963 #address-cells = <2>; 1964 #size-cells = <2>; 1965 ranges; 1966 1967 gpio0: gpio0@ff750000 { 1968 compatible = "rockchip,gpio-bank"; 1969 reg = <0x0 0xff750000 0x0 0x100>; 1970 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1971 clocks = <&cru PCLK_GPIO0>; 1972 1973 gpio-controller; 1974 #gpio-cells = <2>; 1975 1976 interrupt-controller; 1977 #interrupt-cells = <2>; 1978 }; 1979 1980 gpio1: gpio1@ff780000 { 1981 compatible = "rockchip,gpio-bank"; 1982 reg = <0x0 0xff780000 0x0 0x100>; 1983 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1984 clocks = <&cru PCLK_GPIO1>; 1985 1986 gpio-controller; 1987 #gpio-cells = <2>; 1988 1989 interrupt-controller; 1990 #interrupt-cells = <2>; 1991 }; 1992 1993 gpio2: gpio2@ff790000 { 1994 compatible = "rockchip,gpio-bank"; 1995 reg = <0x0 0xff790000 0x0 0x100>; 1996 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1997 clocks = <&cru PCLK_GPIO2>; 1998 1999 gpio-controller; 2000 #gpio-cells = <2>; 2001 2002 interrupt-controller; 2003 #interrupt-cells = <2>; 2004 }; 2005 2006 gpio3: gpio3@ff7a0000 { 2007 compatible = "rockchip,gpio-bank"; 2008 reg = <0x0 0xff7a0000 0x0 0x100>; 2009 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&cru PCLK_GPIO3>; 2011 2012 gpio-controller; 2013 #gpio-cells = <2>; 2014 2015 interrupt-controller; 2016 #interrupt-cells = <2>; 2017 }; 2018 2019 gpio4: gpio4@ff7b0000 { 2020 compatible = "rockchip,gpio-bank"; 2021 reg = <0x0 0xff7b0000 0x0 0x100>; 2022 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2023 clocks = <&cru PCLK_GPIO4>; 2024 2025 gpio-controller; 2026 #gpio-cells = <2>; 2027 2028 interrupt-controller; 2029 #interrupt-cells = <2>; 2030 }; 2031 2032 gpio5: gpio5@ff7c0000 { 2033 compatible = "rockchip,gpio-bank"; 2034 reg = <0x0 0xff7c0000 0x0 0x100>; 2035 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&cru PCLK_GPIO5>; 2037 2038 gpio-controller; 2039 #gpio-cells = <2>; 2040 2041 interrupt-controller; 2042 #interrupt-cells = <2>; 2043 }; 2044 2045 gpio6: gpio6@ff7d0000 { 2046 compatible = "rockchip,gpio-bank"; 2047 reg = <0x0 0xff7d0000 0x0 0x100>; 2048 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 2049 clocks = <&cru PCLK_GPIO6>; 2050 2051 gpio-controller; 2052 #gpio-cells = <2>; 2053 2054 interrupt-controller; 2055 #interrupt-cells = <2>; 2056 }; 2057 2058 gpio7: gpio7@ff7e0000 { 2059 compatible = "rockchip,gpio-bank"; 2060 reg = <0x0 0xff7e0000 0x0 0x100>; 2061 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 2062 clocks = <&cru PCLK_GPIO7>; 2063 2064 gpio-controller; 2065 #gpio-cells = <2>; 2066 2067 interrupt-controller; 2068 #interrupt-cells = <2>; 2069 }; 2070 2071 gpio8: gpio8@ff7f0000 { 2072 compatible = "rockchip,gpio-bank"; 2073 reg = <0x0 0xff7f0000 0x0 0x100>; 2074 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2075 clocks = <&cru PCLK_GPIO8>; 2076 2077 gpio-controller; 2078 #gpio-cells = <2>; 2079 2080 interrupt-controller; 2081 #interrupt-cells = <2>; 2082 }; 2083 2084 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2085 bias-disable; 2086 drive-strength = <12>; 2087 }; 2088 }; 2089}; 2090 2091#include "rk3288-pinctrl.dtsi" 2092