xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rk3568.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3568-power.h>

/ {
	compatible = "rockchip,rk3568";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		dsi0 = &dsi0;
		dsi1 = &dsi1;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		lvds0 = &lvds0;
		lvds1 = &lvds1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
		serial8 = &uart8;
		serial9 = &uart9;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <1000000 1000000 1250000>;
			clock-latency-ns = <40000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1000000 1000000 1250000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1000000 1000000 1250000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1000000 1000000 1250000>;
			clock-latency-ns = <40000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1000000 1000000 1250000>;
			clock-latency-ns = <40000>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	display_subsystem: display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop_out>;
	};

	mpp_srv: mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <5>;
		rockchip,resetgroup-count = <5>;
		status = "disabled";
	};

	psci: psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	thermal_zones: thermal-zones {
		soc_thermal: soc-thermal {
			polling-delay-passive = <20>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&tsadc 0>;
			trips {
				soc_crit: soc-crit {
					/* millicelsius */
					temperature = <115000>;
					/* millicelsius */
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		gpu_thermal: gpu-thermal {
			polling-delay-passive = <20>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&tsadc 1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gmac0_clkin: external-gmac0-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "gmac0_clkin";
		#clock-cells = <0>;
	};

	gmac1_clkin: external-gmac1-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "gmac1_clkin";
		#clock-cells = <0>;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
	};

	sata0: sata@fc000000 {
		compatible = "snps,dwc-ahci";
		reg = <0 0xfc000000 0 0x1000>;
		clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
			 <&cru CLK_SATA0_RXOOB>;
		clock-names = "sata", "pmalive", "rxoob";
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hostc";
		phys = <&combphy0_us PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		ports-implemented = <0x1>;
		power-domains = <&power RK3568_PD_PIPE>;
		status = "disabled";
	};

	sata1: sata@fc400000 {
		compatible = "snps,dwc-ahci";
		reg = <0 0xfc400000 0 0x1000>;
		clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
			 <&cru CLK_SATA1_RXOOB>;
		clock-names = "sata", "pmalive", "rxoob";
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hostc";
		phys = <&combphy1_usq PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		ports-implemented = <0x1>;
		power-domains = <&power RK3568_PD_PIPE>;
		status = "disabled";
	};

	sata2: sata@fc800000 {
		compatible = "snps,dwc-ahci";
		reg = <0 0xfc800000 0 0x1000>;
		clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
			 <&cru CLK_SATA2_RXOOB>;
		clock-names = "sata", "pmalive", "rxoob";
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hostc";
		phys = <&combphy2_psq PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		ports-implemented = <0x1>;
		power-domains = <&power RK3568_PD_PIPE>;
		status = "disabled";
	};

	usbdrd30: usbdrd {
		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
			 <&cru ACLK_USB3OTG0>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbdrd_dwc3: dwc3@fcc00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfcc00000 0x0 0x400000>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "otg";
			phys = <&u2phy0_otg>;
			phy-names = "usb2-phy";
			phy_type = "utmi_wide";
			power-domains = <&power RK3568_PD_PIPE>;
			resets = <&cru SRST_USB3OTG0>;
			reset-names = "usb3-otg";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	usbhost30: usbhost {
		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
			 <&cru ACLK_USB3OTG1>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbhost_dwc3: dwc3@fd000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfd000000 0x0 0x400000>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			phys = <&u2phy0_host>;
			phy-names = "usb2-phy";
			phy_type = "utmi_wide";
			power-domains = <&power RK3568_PD_PIPE>;
			resets = <&cru SRST_USB3OTG1>;
			reset-names = "usb3-host";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	gic: interrupt-controller@fd400000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;

		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		its: interrupt-controller@fd440000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0xfd440000 0x0 0x20000>;
			status = "disabled";
		};
	};

	usb_host0_ehci: usb@fd800000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfd800000 0x0 0x40000>;
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
			 <&cru PCLK_USB>, <&usb2phy1>;
		clock-names = "usbhost", "arbiter", "pclk", "utmi";
		phys = <&u2phy1_otg>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host0_ohci: usb@fd840000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfd840000 0x0 0x40000>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
			 <&cru PCLK_USB>, <&usb2phy1>;
		clock-names = "usbhost", "arbiter", "pclk", "utmi";
		phys = <&u2phy1_otg>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host1_ehci: usb@fd880000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfd880000 0x0 0x40000>;
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
			 <&cru PCLK_USB>, <&usb2phy1>;
		clock-names = "usbhost", "arbiter", "pclk", "utmi";
		phys = <&u2phy1_host>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host1_ohci: usb@fd8c0000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfd8c0000 0x0 0x40000>;
		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
			 <&cru PCLK_USB>, <&usb2phy1>;
		clock-names = "usbhost", "arbiter", "pclk", "utmi";
		phys = <&u2phy1_host>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	pmugrf: syscon@fdc20000 {
		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xfdc20000 0x0 0x10000>;

		pmu_io_domains: io-domains {
			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
			status = "disabled";
		};

		reboot_mode: reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x200>;
			mode-bootloader = <BOOT_BL_DOWNLOAD>;
			mode-charge = <BOOT_CHARGING>;
			mode-fastboot = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-ums = <BOOT_UMS>;
			mode-panic = <BOOT_PANIC>;
			mode-watchdog = <BOOT_WATCHDOG>;
		};
	};

	pipegrf: syscon@fdc50000 {
		compatible = "rockchip,rk3568-pipegrf", "syscon";
		reg = <0x0 0xfdc50000 0x0 0x1000>;
	};

	grf: syscon@fdc60000 {
		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfdc60000 0x0 0x10000>;

		io_domains: io-domains {
			compatible = "rockchip,rk3568-io-voltage-domain";
			status = "disabled";
		};

		lvds0: lvds0 {
			compatible = "rockchip,rk3568-lvds";
			phys = <&video_phy0>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					lvds0_in_vp1: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vp1_out_lvds0>;
					};

					lvds0_in_vp2: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vp2_out_lvds0>;
					};
				};
			};
		};

		lvds1: lvds1 {
			compatible = "rockchip,rk3568-lvds";
			phys = <&video_phy1>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					lvds1_in_vp1: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vp1_out_lvds1>;
					};

					lvds1_in_vp2: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vp2_out_lvds1>;
					};
				};
			};
		};

		rgb: rgb {
			compatible = "rockchip,rk3568-rgb";
			pinctrl-names = "default";
			pinctrl-0 = <&lcdc_ctl>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					rgb_in_vp2: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vp2_out_rgb>;
					};
				};

			};
		};

	};

	pipe_phy_grf0: syscon@fdc70000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc70000 0x0 0x1000>;
	};

	pipe_phy_grf1: syscon@fdc80000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc80000 0x0 0x1000>;
	};

	pipe_phy_grf2: syscon@fdc90000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc90000 0x0 0x1000>;
	};

	usb2phy0_grf: syscon@fdca0000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca0000 0x0 0x8000>;
	};

	usb2phy1_grf: syscon@fdca8000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca8000 0x0 0x8000>;
	};

	edp_phy: edp-phy@fdcb0000 {
		compatible = "rockchip,rk3568-edp-phy";
		reg = <0x0 0xfdcb0000 0x0 0x8000>;
		clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
		clock-names = "refclk", "pclk";
		resets = <&cru SRST_P_EDPPHY_GRF>;
		reset-names = "apb";
		#phy-cells = <0>;
		status = "disabled";
	};

	pcie30_phy_grf: syscon@fdcb8000 {
		compatible = "rockchip,pcie30-phy-grf", "syscon";
		reg = <0x0 0xfdcb8000 0x0 0x10000>;
	};

	pmucru: clock-controller@fdd00000 {
		compatible = "rockchip,rk3568-pmucru";
		reg = <0x0 0xfdd00000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cru: clock-controller@fdd20000 {
		compatible = "rockchip,rk3568-cru";
		reg = <0x0 0xfdd20000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,
			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
			<&cru PLL_GPLL>, <&cru ARMCLK>,
			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
			<&cru PLL_NPLL>;
		assigned-clock-rates =
			<32768>, <200000000>,
			<100000000>, <1000000000>,
			<1188000000>, <600000000>,
			<150000000>, <100000000>,
			<300000000>, <200000000>,
			<150000000>, <100000000>,
			<300000000>, <150000000>,
			<1200000000>;
		assigned-clock-parents =
			<&pmucru CLK_RTC32K_FRAC>;
	};

	i2c0: i2c@fdd40000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfdd40000 0x0 0x1000>;
		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart0: serial@fdd50000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfdd50000 0x0 0x100>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 0>, <&dmac0 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer>;
		status = "disabled";
	};

	pwm0: pwm@fdd70000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm1: pwm@fdd70010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm2: pwm@fdd70020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm3: pwm@fdd70030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pmu: power-management@fdd90000 {
		compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xfdd90000 0x0 0x1000>;

		power: power-controller {
			compatible = "rockchip,rk3568-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			/* These power domains are grouped by VD_NPU */
			pd_npu@RK3568_PD_NPU {
				reg = <RK3568_PD_NPU>;
				clocks = <&cru ACLK_NPU_PRE>,
					 <&cru HCLK_NPU_PRE>,
					 <&cru PCLK_NPU_PRE>;
				pm_qos = <&qos_npu>;
			};
			/* These power domains are grouped by VD_GPU */
			pd_gpu@RK3568_PD_GPU {
				reg = <RK3568_PD_GPU>;
				clocks = <&cru ACLK_GPU_PRE>,
					 <&cru PCLK_GPU_PRE>;
				pm_qos = <&qos_gpu>;
			};
			/* These power domains are grouped by VD_LOGIC */
			pd_vi@RK3568_PD_VI {
				reg = <RK3568_PD_VI>;
				clocks = <&cru HCLK_VI>,
					 <&cru PCLK_VI>;
				pm_qos = <&qos_isp>,
					 <&qos_vicap0>,
					 <&qos_vicap1>;
			};
			pd_vo@RK3568_PD_VO {
				reg = <RK3568_PD_VO>;
				clocks = <&cru HCLK_VO>,
					 <&cru PCLK_VO>,
					 <&cru ACLK_VOP_PRE>;
				pm_qos = <&qos_hdcp>,
					 <&qos_vop_m0>,
					 <&qos_vop_m1>;
			};
			pd_rga@RK3568_PD_RGA {
				reg = <RK3568_PD_RGA>;
				clocks = <&cru HCLK_RGA_PRE>,
					 <&cru PCLK_RGA_PRE>;
				pm_qos = <&qos_ebc>,
					 <&qos_iep>,
					 <&qos_jpeg_dec>,
					 <&qos_jpeg_enc>,
					 <&qos_rga_rd>,
					 <&qos_rga_wr>;
			};
			pd_vpu@RK3568_PD_VPU {
				reg = <RK3568_PD_VPU>;
				clocks = <&cru HCLK_VPU_PRE>;
				pm_qos = <&qos_vpu>;
			};
			pd_rkvdec@RK3568_PD_RKVDEC {
				clocks = <&cru HCLK_RKVDEC_PRE>;
				reg = <RK3568_PD_RKVDEC>;
				pm_qos = <&qos_rkvdec>;
			};
			pd_rkvenc@RK3568_PD_RKVENC {
				reg = <RK3568_PD_RKVENC>;
				clocks = <&cru HCLK_RKVENC_PRE>;
				pm_qos = <&qos_rkvenc_rd_m0>,
					 <&qos_rkvenc_rd_m1>,
					 <&qos_rkvenc_wr_m0>;
			};
			pd_pipe@RK3568_PD_PIPE {
				reg = <RK3568_PD_PIPE>;
				clocks = <&cru PCLK_PIPE>;
				pm_qos = <&qos_pcie2x1>,
					 <&qos_pcie3x1>,
					 <&qos_pcie3x2>,
					 <&qos_sata0>,
					 <&qos_sata1>,
					 <&qos_sata2>,
					 <&qos_usb3_0>,
					 <&qos_usb3_1>;
			};
		};
	};

	pvtm@fde00000 {
		compatible = "rockchip,rk3568-core-pvtm";
		reg = <0x0 0xfde00000 0x0 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		pvtm@0 {
			reg = <0>;
			clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
			clock-names = "clk", "pclk";
			resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
			reset-names = "rts", "rst-p";
			thermal-zone = "soc-thermal";
		};
	};

	gpu: gpu@fde60000 {
		compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
		reg = <0x0 0xfde60000 0x0 0x4000>;

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "GPU", "MMU", "JOB";

		upthreshold = <40>;
		downdifferential = <10>;

		clocks = <&cru CLK_GPU>;
		clock-names = "clk_mali";
		power-domains = <&power RK3568_PD_GPU>;
		#cooling-cells = <2>;
		operating-points-v2 = <&gpu_opp_table>;

		status = "disabled";
		power_model {
			compatible = "arm,mali-simple-power-model";
			static-coefficient = <411000>;
			dynamic-coefficient = <733>;
			ts = <32000 4700 (-80) 2>;
			thermal-zone = "gpu-thermal";
		};
	};

	gpu_opp_table: opp-table2 {
		compatible = "operating-points-v2";

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <1000000>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1000000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <1000000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1000000>;
		};
	};

	pvtm@fde80000 {
		compatible = "rockchip,rk3568-gpu-pvtm";
		reg = <0x0 0xfde80000 0x0 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		pvtm@1 {
			reg = <1>;
			clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
			clock-names = "clk", "pclk";
			resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
			reset-names = "rts", "rst-p";
			thermal-zone = "gpu-thermal";
		};
	};

	pvtm@fde90000 {
		compatible = "rockchip,rk3568-npu-pvtm";
		reg = <0x0 0xfde90000 0x0 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		pvtm@2 {
			reg = <2>;
			clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
				 <&cru HCLK_NPU_PRE>;
			clock-names = "clk", "pclk", "hclk";
			resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
			reset-names = "rts", "rst-p";
			thermal-zone = "soc-thermal";
		};
	};

	vdpu: vdpu@fdea0400 {
		compatible = "rockchip,vpu-decoder-v2";
		reg = <0x0 0xfdea0400 0x0 0x400>;
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
		reset-names = "video_a", "video_h";
		iommus = <&vdpu_mmu>;
		power-domains = <&power RK3568_PD_VPU>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	vdpu_mmu: iommu@fdea0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfdea0800 0x0 0x40>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vdpu_mmu";
		clock-names = "aclk", "iface";
		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
		power-domains = <&power RK3568_PD_VPU>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	rk_rga: rk_rga@fdeb0000 {
		compatible = "rockchip,rga2";
		reg = <0x0 0xfdeb0000 0x0 0x1000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		power-domains = <&power RK3568_PD_RGA>;
		status = "disabled";
	};

	ebc: ebc@fdec0000 {
		compatible = "rockchip,rk3568-ebc-tcon";
		reg = <0x0 0xfdec0000 0x0 0x5000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
		clock-names = "hclk", "dclk";
		power-domains = <&power RK3568_PD_RGA>;
		rockchip,grf = <&grf>;
		pinctrl-names = "default";
		pinctrl-0 = <&ebc_pins>;
		status = "disabled";
	};

	jpegd: jpegd@fded0000 {
		compatible = "rockchip,rkv-jpeg-decoder-v1";
		reg = <0x0 0xfded0000 0x0 0x400>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		rockchip,normal-rates = <297000000>, <0>;
		resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
		reset-names = "video_a", "video_h";
		iommus = <&jpegd_mmu>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <1>;
		rockchip,resetgroup-node = <1>;
		power-domains = <&power RK3568_PD_RGA>;
		status = "disabled";
	};

	jpegd_mmu: iommu@fded0480 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfded0480 0x0 0x40>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "jpegd_mmu";
		clock-names = "aclk", "iface";
		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
		power-domains = <&power RK3568_PD_RGA>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	vepu: vepu@fdee0000 {
		compatible = "rockchip,vpu-encoder-v2";
		reg = <0x0 0xfdee0000 0x0 0x400>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		rockchip,normal-rates = <297000000>, <0>;
		resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
		reset-names = "video_a", "video_h";
		iommus = <&vepu_mmu>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <2>;
		rockchip,resetgroup-node = <2>;
		power-domains = <&power RK3568_PD_RGA>;
		status = "disabled";
	};

	vepu_mmu: iommu@fdee0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfdee0800 0x0 0x40>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vepu_mmu";
		clock-names = "aclk", "iface";
		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
		power-domains = <&power RK3568_PD_RGA>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	iep: iep@fdef0000 {
		compatible = "rockchip,iep-v2";
		reg = <0x0 0xfdef0000 0x0 0x500>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
		clock-names = "aclk", "hclk", "sclk";
		resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
			<&cru SRST_IEP_CORE>;
		reset-names = "rst_a", "rst_h", "rst_s";
		power-domains = <&power RK3568_PD_RGA>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <5>;
		rockchip,resetgroup-node = <5>;
		iommus = <&iep_mmu>;
		status = "disabled";
	};

	iep_mmu: iommu@fdef0800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfdef0800 0x0 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iep_mmu";
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3568_PD_RGA>;
		//rockchip,disable-device-link-resume;
		status = "disabled";
	};

	eink: eink@fdf00000 {
		compatible = "rockchip,rk3568-eink-tcon";
		reg = <0x0 0xfdf00000 0x0 0x74>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
		clock-names = "pclk", "hclk";
		status = "disabled";
	};

	rkvenc: rkvenc@fdf40000 {
		compatible = "rockchip,rkv-encoder-v1";
		reg = <0x0 0xfdf40000 0x0 0x400>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc";
		clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
			<&cru CLK_RKVENC_CORE>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
		rockchip,normal-rates = <297000000>, <0>, <400000000>;
		rockchip,advanced-rates = <297000000>, <0>, <500000000>;
		rockchip,default-max-load = <2088960>;
		resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
			<&cru SRST_RKVENC_CORE>;
		reset-names = "video_a", "video_h", "video_core";
		assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
		assigned-clock-rates = <297000000>, <297000000>;
		iommus = <&rkvenc_mmu>;
		node-name = "rkvenc";
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <3>;
		rockchip,resetgroup-node = <3>;
		power-domains = <&power RK3568_PD_RKVENC>;
		status = "disabled";
	};

	rkvenc_mmu: iommu@fdf40f00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
		clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
		clock-names = "aclk", "iface";
		rockchip,disable-mmu-reset;
		rockchip,enable-cmd-retry;
		#iommu-cells = <0>;
		power-domains = <&power RK3568_PD_RKVENC>;
		status = "disabled";
	};

	rkvdec: rkvdec@fdf80200 {
		compatible = "rockchip,rkv-decoder-v2";
		reg = <0x0 0xfdf80200 0x0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
			 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
			 <&cru CLK_RKVDEC_HEVC_CA>;
		clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
			      "clk_core", "clk_hevc_cabac";
		rockchip,normal-rates = <297000000>, <0>, <297000000>,
					<297000000>, <400000000>;
		rockchip,advanced-rates = <400000000>, <0>, <400000000>,
					<400000000>, <500000000>;
		rockchip,default-max-load = <2088960>;
		resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
			 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
			 <&cru SRST_RKVDEC_HEVC_CA>;
		assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
				  <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
		assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
		reset-names = "video_a", "video_h", "video_cabac",
			      "video_core", "video_hevc_cabac";
		power-domains = <&power RK3568_PD_RKVDEC>;
		iommus = <&rkvdec_mmu>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <4>;
		rockchip,resetgroup-node = <4>;
		status = "disabled";
	};

	rkvdec_mmu: iommu@fdf80800 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rkvdec_mmu";
		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3568_PD_RKVDEC>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	mipi_csi2: mipi-csi2@fdfb0000 {
		compatible = "rockchip,rk3568-mipi-csi2";
		reg = <0x0 0xfdfb0000 0x0 0x10000>;
		reg-names = "csihost_regs";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "csi-intr1", "csi-intr2";
		clocks = <&cru PCLK_CSI2HOST1>, <&cru SRST_P_CSI2HOST1>;
		clock-names = "pclk_csi2host", "srst_csihost_p";
		power-domains = <&power RK3568_PD_VI>;
		status = "disabled";
	};

	rkcif: rkcif@fdfe0000 {
		compatible = "rockchip,rk3568-cif";
		reg = <0x0 0xfdfe0000 0x0 0x8000>;
		reg-names = "cif_regs";
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "cif-intr";

		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
			 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
		clock-names = "aclk_cif", "hclk_cif",
			      "dclk_cif", "iclk_cif_g";
		resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
			 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
			 <&cru SRST_I_VICAP>;
		reset-names = "rst_cif_a", "rst_cif_h",
			      "rst_cif_d", "rst_cif_p",
			      "rst_cif_i";
		assigned-clocks = <&cru DCLK_VICAP>;
		assigned-clock-rates = <300000000>;
		power-domains = <&power RK3568_PD_VI>;
		rockchip,grf = <&grf>;
		iommus = <&rkcif_mmu>;
		status = "disabled";
	};

	rkcif_mmu: iommu@fdfe0800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xfdfe0800 0x0 0x100>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "cif_mmu";
		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3568_PD_VI>;
		#iommu-cells = <0>;
		rockchip,disable-mmu-reset;
		status = "disabled";
	};

	rkcif_dvp: rkcif_dvp {
		compatible = "rockchip,rkcif-dvp";
		rockchip,hw = <&rkcif>;
		iommus = <&rkcif_mmu>;
		status = "disabled";
	};

	rkcif_dvp_sditf: rkcif_dvp_sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <&rkcif_dvp>;
		status = "disabled";
	};

	rkcif_mipi_lvds: rkcif_mipi_lvds {
		compatible = "rockchip,rkcif-mipi-lvds";
		rockchip,hw = <&rkcif>;
		iommus = <&rkcif_mmu>;
		status = "disabled";
	};

	rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf {
		compatible = "rockchip,rkcif-sditf";
		rockchip,cif = <&rkcif_mipi_lvds>;
		status = "disabled";
	};

	rkisp: rkisp@fdff0000 {
		compatible = "rockchip,rk3568-rkisp";
		reg = <0x0 0xfdff0000 0x0 0x10000>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
		clock-names = "aclk_isp", "hclk_isp", "clk_isp";
		resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
		reset-names = "isp", "isp-h";
		rockchip,grf = <&grf>;
		power-domains = <&power RK3568_PD_VI>;
		iommus = <&rkisp_mmu>;
		status = "disabled";
	};

	rkisp_mmu: iommu@fdff1a00 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xfdff1a00 0x0 0x100>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "isp_mmu";
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3568_PD_VI>;
		#iommu-cells = <0>;
		rockchip,disable-mmu-reset;
		status = "disabled";
	};

	rkisp_vir0: rkisp-vir0 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <&rkisp>;
		status = "disabled";
	};

	rkisp_vir1: rkisp-vir1 {
		compatible = "rockchip,rkisp-vir";
		rockchip,hw = <&rkisp>;
		status = "disabled";
	};

	gmac1: ethernet@fe010000 {
		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
		reg = <0x0 0xfe010000 0x0 0x10000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
		clock-names = "stmmaceth", "mac_clk_rx",
			      "mac_clk_tx", "clk_mac_refout",
			      "aclk_mac", "pclk_mac",
			      "clk_mac_speed", "ptp_ref";
		resets = <&cru SRST_A_GMAC1>;
		reset-names = "stmmaceth";

		snps,mixed-burst;
		snps,tso;

		snps,axi-config = <&gmac1_stmmac_axi_setup>;
		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
		status = "disabled";

		mdio1: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		gmac1_stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <4>;
			snps,rd_osr_lmt = <8>;
			snps,blen = <0 0 0 0 16 8 4>;
		};

		gmac1_mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <1>;
			queue0 {};
		};

		gmac1_mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <1>;
			queue0 {};
		};
	};

	vop: vop@fe040000 {
		compatible = "rockchip,rk3568-vop";
		reg = <0x0 0xfe040000 0x0 0x3000>;
		reg-names = "regs";
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
		clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
		iommus = <&vop_mmu>;
		power-domains = <&power RK3568_PD_VO>;
		status = "disabled";

		vop_out: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				vp0_out_dsi0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&dsi0_in_vp0>;
				};

				vp0_out_dsi1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&dsi1_in_vp0>;
				};

				vp0_out_edp: endpoint@2 {
					reg = <2>;
					remote-endpoint = <&edp_in_vp0>;
				};

				vp0_out_hdmi: endpoint@3 {
					reg = <3>;
					remote-endpoint = <&hdmi_in_vp0>;
				};
			};

			port@1 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <1>;

				vp1_out_dsi0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&dsi0_in_vp1>;
				};

				vp1_out_dsi1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&dsi1_in_vp1>;
				};

				vp1_out_edp: endpoint@2 {
					reg = <2>;
					remote-endpoint = <&edp_in_vp1>;
				};

				vp1_out_hdmi: endpoint@3 {
					reg = <3>;
					remote-endpoint = <&hdmi_in_vp1>;
				};

				vp1_out_lvds0: endpoint@4 {
					reg = <4>;
					remote-endpoint = <&lvds0_in_vp1>;
				};

				vp1_out_lvds1: endpoint@5 {
					reg = <5>;
					remote-endpoint = <&lvds1_in_vp1>;
				};

			};

			port@2 {
				#address-cells = <1>;
				#size-cells = <0>;

				reg = <2>;

				vp2_out_lvds0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&lvds0_in_vp2>;
				};

				vp2_out_lvds1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&lvds1_in_vp2>;
				};

				vp2_out_rgb: endpoint@2 {
					reg = <2>;
					remote-endpoint = <&rgb_in_vp2>;
				};
			};
		};
	};

	vop_mmu: iommu@fe043e00 {
		compatible = "rockchip,iommu-v2";
		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vop_mmu";
		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		status = "disabled";
	};

	dsi0: dsi@fe060000 {
		compatible = "rockchip,rk3568-mipi-dsi";
		reg = <0x0 0xfe060000 0x0 0x10000>;
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>;
		clock-names = "pclk", "hclk", "hs_clk";
		resets = <&cru SRST_P_DSITX_0>;
		reset-names = "apb";
		phys = <&mipi_dphy0>;
		phy-names = "mipi_dphy";
		power-domains = <&power RK3568_PD_VO>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			dsi0_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				dsi0_in_vp0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vp0_out_dsi0>;
				};

				dsi0_in_vp1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vp1_out_dsi0>;
				};
			};
		};
	};

	dsi1: dsi@fe070000 {
		compatible = "rockchip,rk3568-mipi-dsi";
		reg = <0x0 0xfe070000 0x0 0x10000>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>;
		clock-names = "pclk", "hclk", "hs_clk";
		resets = <&cru SRST_P_DSITX_1>;
		reset-names = "apb";
		phys = <&mipi_dphy1>;
		phy-names = "mipi_dphy";
		power-domains = <&power RK3568_PD_VO>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			dsi1_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				dsi1_in_vp0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vp0_out_dsi1>;
				};

				dsi1_in_vp1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vp1_out_dsi1>;
				};
			};
		};
	};

	hdmi: hdmi@fe0a0000 {
		compatible = "rockchip,rk3568-dw-hdmi";
		reg = <0x0 0xfe0a0000 0x0 0x20000>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_HDMI_HOST>,
			 <&cru CLK_HDMI_SFR>,
			 <&cru CLK_HDMI_CEC>,
			 <&pmucru PLL_HPLL>,
			 <&cru HCLK_VOP>;
		clock-names = "iahb", "isfr", "cec", "ref", "hclk";
		power-domains = <&power RK3568_PD_VO>;
		reg-io-width = <4>;
		rockchip,grf = <&grf>;
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			hdmi_in: port {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				hdmi_in_vp0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vp0_out_hdmi>;
				};
				hdmi_in_vp1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vp1_out_hdmi>;
				};
			};
		};
	};

	edp: edp@fe0c0000 {
		compatible = "rockchip,rk3568-edp";
		reg = <0x0 0xfe0c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
			 <&cru CLK_EDP_200M>, <&cru HCLK_VO>;
		clock-names = "dp", "pclk", "spdif", "hclk";
		resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
		reset-names = "dp", "apb";
		phys = <&edp_phy>;
		phy-names = "dp";
		power-domains = <&power RK3568_PD_VO>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			edp_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				edp_in_vp0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vp0_out_edp>;
				};

				edp_in_vp1: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vp1_out_edp>;
				};
			};
		};
	};

	qos_gpu: qos@fe128000 {
		compatible = "syscon";
		reg = <0x0 0xfe128000 0x0 0x20>;
	};

	qos_rkvenc_rd_m0: qos@fe138080 {
		compatible = "syscon";
		reg = <0x0 0xfe138080 0x0 0x20>;
	};

	qos_rkvenc_rd_m1: qos@fe138100 {
		compatible = "syscon";
		reg = <0x0 0xfe138100 0x0 0x20>;
	};

	qos_rkvenc_wr_m0: qos@fe138180 {
		compatible = "syscon";
		reg = <0x0 0xfe138180 0x0 0x20>;
	};

	qos_isp: qos@fe148000 {
		compatible = "syscon";
		reg = <0x0 0xfe148000 0x0 0x20>;
	};

	qos_vicap0: qos@fe148080 {
		compatible = "syscon";
		reg = <0x0 0xfe148080 0x0 0x20>;
	};

	qos_vicap1: qos@fe148100 {
		compatible = "syscon";
		reg = <0x0 0xfe148100 0x0 0x20>;
	};

	qos_vpu: qos@fe150000 {
		compatible = "syscon";
		reg = <0x0 0xfe150000 0x0 0x20>;
	};

	qos_ebc: qos@fe158000 {
		compatible = "syscon";
		reg = <0x0 0xfe158000 0x0 0x20>;
	};

	qos_iep: qos@fe158100 {
		compatible = "syscon";
		reg = <0x0 0xfe158100 0x0 0x20>;
	};

	qos_jpeg_dec: qos@fe158180 {
		compatible = "syscon";
		reg = <0x0 0xfe158180 0x0 0x20>;
	};

	qos_jpeg_enc: qos@fe158200 {
		compatible = "syscon";
		reg = <0x0 0xfe158200 0x0 0x20>;
	};

	qos_rga_rd: qos@fe158280 {
		compatible = "syscon";
		reg = <0x0 0xfe158280 0x0 0x20>;
	};

	qos_rga_wr: qos@fe158300 {
		compatible = "syscon";
		reg = <0x0 0xfe158300 0x0 0x20>;
	};

	qos_npu: qos@fe180000 {
		compatible = "syscon";
		reg = <0x0 0xfe180000 0x0 0x20>;
	};

	qos_pcie2x1: qos@fe190000 {
		compatible = "syscon";
		reg = <0x0 0xfe190000 0x0 0x20>;
	};

	qos_pcie3x1: qos@fe190080 {
		compatible = "syscon";
		reg = <0x0 0xfe190080 0x0 0x20>;
	};

	qos_pcie3x2: qos@fe190100 {
		compatible = "syscon";
		reg = <0x0 0xfe190100 0x0 0x20>;
	};

	qos_sata0: qos@fe190200 {
		compatible = "syscon";
		reg = <0x0 0xfe190200 0x0 0x20>;
	};

	qos_sata1: qos@fe190280 {
		compatible = "syscon";
		reg = <0x0 0xfe190280 0x0 0x20>;
	};

	qos_sata2: qos@fe190300 {
		compatible = "syscon";
		reg = <0x0 0xfe190300 0x0 0x20>;
	};

	qos_usb3_0: qos@fe190380 {
		compatible = "syscon";
		reg = <0x0 0xfe190380 0x0 0x20>;
	};

	qos_usb3_1: qos@fe190400 {
		compatible = "syscon";
		reg = <0x0 0xfe190400 0x0 0x20>;
	};

	qos_rkvdec: qos@fe198000 {
		compatible = "syscon";
		reg = <0x0 0xfe198000 0x0 0x20>;
	};

	qos_hdcp: qos@fe1a8000 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8000 0x0 0x20>;
	};

	qos_vop_m0: qos@fe1a8080 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8080 0x0 0x20>;
	};

	qos_vop_m1: qos@fe1a8100 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8100 0x0 0x20>;
	};

	sdmmc2: dwmmc@fe000000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe000000 0x0 0x4000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
			 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC2>;
		reset-names = "reset";
		status = "disabled";
	};

	pcie2x1: pcie@fe260000 {
		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0x1f>;
		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk";
		device_type = "pci";
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		linux,pci-domain = <0>;
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		max-link-speed = <2>;
		msi-map = <0x0 &its 0x0 0x1000>;
		num-lanes = <1>;
		phys = <&combphy2_psq PHY_TYPE_PCIE>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3568_PD_PIPE>;
		ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
			  0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
			  0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000
			  0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
		reg = <0x3 0xc0000000 0x0 0x400000>,
		      <0x0 0xfe260000 0x0 0x10000>;
		reg-names = "pcie-dbi", "pcie-apb";
		resets = <&cru SRST_PCIE20_POWERUP>;
		reset-names = "pipe";
		status = "disabled";
	};

	pcie3x1: pcie@fe270000 {
		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0x1f>;
		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk";
		device_type = "pci";
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		linux,pci-domain = <1>;
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		max-link-speed = <3>;
		msi-map = <0x0 &its 0x3000 0x1000>;
		num-lanes = <1>;
		phys = <&pcie30phy>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3568_PD_PIPE>;
		ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
			  0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
			  0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000
			  0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
		reg = <0x3 0xc0400000 0x0 0x400000>,
		      <0x0 0xfe270000 0x0 0x10000>;
		reg-names = "pcie-dbi", "pcie-apb";
		resets = <&cru SRST_PCIE30X1_POWERUP>;
		reset-names = "pipe";
		/* rockchip,bifurcation; lane1 when using 1+1 */
		status = "disabled";
	};

	pcie3x2: pcie@fe280000 {
		compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0x1f>;
		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>;
		clock-names = "aclk_mst", "aclk_slv",
			      "aclk_dbi", "pclk";
		device_type = "pci";
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
		linux,pci-domain = <2>;
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		max-link-speed = <3>;
		msi-map = <0x0 &its 0x2000 0x1000>;
		num-lanes = <2>;
		phys = <&pcie30phy>;
		phy-names = "pcie-phy";
		power-domains = <&power RK3568_PD_PIPE>;
		ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
			  0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
			  0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000
			  0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
		reg = <0x3 0xc0800000 0x0 0x400000>,
		      <0x0 0xfe280000 0x0 0x10000>;
		reg-names = "pcie-dbi", "pcie-apb";
		resets = <&cru SRST_PCIE30X2_POWERUP>;
		reset-names = "pipe";
		/* rockchip,bifurcation; lane0 when using 1+1 */
		status = "disabled";
	};

	gmac0: ethernet@fe2a0000 {
		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
		reg = <0x0 0xfe2a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
		clock-names = "stmmaceth", "mac_clk_rx",
			      "mac_clk_tx", "clk_mac_refout",
			      "aclk_mac", "pclk_mac",
			      "clk_mac_speed", "ptp_ref";
		resets = <&cru SRST_A_GMAC0>;
		reset-names = "stmmaceth";

		snps,mixed-burst;
		snps,tso;

		snps,axi-config = <&gmac0_stmmac_axi_setup>;
		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
		status = "disabled";

		mdio0: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		gmac0_stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <4>;
			snps,rd_osr_lmt = <8>;
			snps,blen = <0 0 0 0 16 8 4>;
		};

		gmac0_mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <1>;
			queue0 {};
		};

		gmac0_mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <1>;
			queue0 {};
		};
	};

	sdmmc0: dwmmc@fe2b0000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe2b0000 0x0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
			 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC0>;
		reset-names = "reset";
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
		status = "disabled";
	};

	sdmmc1: dwmmc@fe2c0000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe2c0000 0x0 0x4000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
			 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC1>;
		reset-names = "reset";
		status = "disabled";
	};

	sfc: sfc@fe300000 {
		compatible = "rockchip,sfc";
		reg = <0x0 0xfe300000 0x0 0x4000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		assigned-clocks = <&cru SCLK_SFC>;
		assigned-clock-rates = <100000000>;
		status = "disabled";
	};

	sdhci: sdhci@fe310000 {
		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
		reg = <0x0 0xfe310000 0x0 0x10000>;
		max-frequency = <200000000>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
		assigned-clock-rates = <200000000>, <24000000>;
		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
			 <&cru TCLK_EMMC>;
		clock-names = "core", "bus", "axi", "block", "timer";
		status = "disabled";
	};

	nandc0: nandc@fe330000 {
		compatible = "rockchip,rk-nandc";
		reg = <0x0 0xfe330000 0x0 0x4000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		nandc_id = <0>;
		clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
		clock-names = "clk_nandc", "hclk_nandc";
		status = "disabled";
	};

	crypto: crypto@fe380000 {
		compatible = "rockchip,rk3568-crypto";
		reg = <0x0 0xfe380000 0x0 0x4000>;
		clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
		clock-names = "sclk_crypto", "apkclk_crypto";
		clock-frequency = <150000000>, <300000000>;
		status = "disabled";
	};

	rng: rng@fe388000 {
		compatible = "rockchip,cryptov2-rng";
		reg = <0x0 0xfe388000 0x0 0x2000>;
		status = "disabled";
	};

	 otp: otp@fe38c000 {
                compatible = "rockchip,rk3568-otp";
                reg = <0x0 0xfe38c000 0x0 0x4000>;
                #address-cells = <1>;
                #size-cells = <1>;
                clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
                         <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
                clock-names = "usr", "sbpi", "apb", "phy";
                resets = <&cru SRST_OTPPHY>;
                reset-names = "otp_phy";

                /* Data cells */
                cpu_code: cpu-code@2 {
                        reg = <0x02 0x2>;
                };
                otp_cpu_version: cpu-version@8 {
                        reg = <0x08 0x1>;
                        bits = <3 3>;
                };
                mbist_vmin: mbist-vmin@9 {
                        reg = <0x09 0x1>;
                        bits = <0 4>;
                };
                otp_id: id@a {
                        reg = <0x0a 0x10>;
                };
                cpu_leakage: cpu-leakage@1a {
                        reg = <0x1a 0x1>;
                };
                log_leakage: log-leakage@1b {
                        reg = <0x1b 0x1>;
                };
                npu_leakage: npu-leakage@1c {
                        reg = <0x1c 0x1>;
                };
                gpu_leakage: gpu-leakage@1d {
                        reg = <0x1d 0x1>;
                };
                core_pvtm:core-pvtm@2a {
                        reg = <0x2a 0x2>;
                };
                cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e {
                        reg = <0x2e 0x1>;
                };
                cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f {
                        reg = <0x2f 0x1>;
                        bits = <0 4>;
                };
                gpu_tsadc_trim_l: npu-tsadc-trim-l@30 {
                        reg = <0x30 0x1>;
                };
                gpu_tsadc_trim_h: npu-tsadc-trim-h@31 {
                        reg = <0x31 0x1>;
                        bits = <0 4>;
                };
                tsadc_trim_base_frac: tsadc-trim-base-frac@31 {
                        reg = <0x31 0x1>;
                        bits = <4 4>;
                };
                tsadc_trim_base: tsadc-trim-base@32 {
                        reg = <0x32 0x1>;
                };
                cpu_opp_info: cpu-opp-info@36 {
                        reg = <0x36 0x6>;
                };
                gpu_opp_info: gpu-opp-info@3c {
                        reg = <0x3c 0x6>;
                };
                npu_opp_info: npu-opp-info@42 {
                        reg = <0x42 0x6>;
                };
                dmc_opp_info: dmc-opp-info@48 {
                        reg = <0x48 0x6>;
                };
        };

	i2s0_8ch: i2s@fe400000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe400000 0x0 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 0>;
		dma-names = "tx";
		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		rockchip,playback-only;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s1_8ch: i2s@fe410000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe410000 0x0 0x1000>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 2>, <&dmac1 3>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1sclktxm0
			     &i2s1sclkrxm0
			     &i2s1lrcktxm0
			     &i2s1lrckrxm0
			     &i2s1sdi0m0
			     &i2s1sdi1m0
			     &i2s1sdi2m0
			     &i2s1sdi3m0
			     &i2s1sdo0m0
			     &i2s1sdo1m0
			     &i2s1sdo2m0
			     &i2s1sdo3m0>;
		status = "disabled";
	};

	i2s2_2ch: i2s@fe420000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe420000 0x0 0x1000>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 4>, <&dmac1 5>;
		dma-names = "tx", "rx";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		rockchip,clk-trcm = <1>;
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2sclktxm0
			     &i2s2lrcktxm0
			     &i2s2sdim0
			     &i2s2sdom0>;
		status = "disabled";
	};

	i2s3_2ch: i2s@fe430000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe430000 0x0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 6>, <&dmac1 7>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s3sclkm0
			     &i2s3lrckm0
			     &i2s3sdim0
			     &i2s3sdom0>;
		status = "disabled";
	};

	pdm: pdm@fe440000 {
		compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
		reg = <0x0 0xfe440000 0x0 0x1000>;
		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
		clock-names = "pdm_clk", "pdm_hclk";
		dmas = <&dmac1 9>;
		dma-names = "rx";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	vad: vad@fe450000 {
		compatible = "rockchip,rk3568-vad";
		reg = <0x0 0xfe450000 0x0 0x10000>;
		reg-names = "vad";
		clocks = <&cru HCLK_VAD>;
		clock-names = "hclk";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,audio-src = <0>;
		rockchip,det-channel = <0>;
		rockchip,mode = <0>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	spdif_8ch: spdif@fe460000 {
		compatible = "rockchip,rk3568-spdif";
		reg = <0x0 0xfe460000 0x0 0x1000>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&dmac1 1>;
		dma-names = "tx";
		clock-names = "mclk", "hclk";
		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdifm0_pins>;
		status = "disabled";
	};

	audpwm: audpwm@fe470000 {
		compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
		reg = <0x0 0xfe470000 0x0 0x1000>;
		clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
		clock-names = "clk", "hclk";
		dmas = <&dmac1 8>;
		dma-names = "tx";
		#sound-dai-cells = <0>;
		rockchip,sample-width-bits = <11>;
		rockchip,interpolat-points = <1>;
		status = "disabled";
	};

	dig_acodec: codec-digital@fe478000 {
		compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
		reg = <0x0 0xfe478000 0x0 0x1000>;
		clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
			 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
		clock-names = "adc", "dac", "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&acodec_pins>;
		resets = <&cru SRST_ACDCDIG>;
		reset-names = "reset" ;
		rockchip,grf = <&grf>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	dmac0: dmac@fe530000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfe530000 0x0 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_BUS>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		arm,pl330-periph-burst;
	};

	dmac1: dmac@fe550000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfe550000 0x0 0x4000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_BUS>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		arm,pl330-periph-burst;
	};

	can0: can@fe570000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe570000 0x0 0x1000>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	can1: can@fe580000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe580000 0x0 0x1000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	can2: can@fe590000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe590000 0x0 0x1000>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	i2c1: i2c@fe5a0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5a0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@fe5b0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5b0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@fe5c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5c0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@fe5d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5d0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c5: i2c@fe5e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5e0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	wdt: watchdog@fe600000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0xfe600000 0x0 0x100>;
		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
		clock-names = "tclk", "pclk";
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&cru SRST_T_WDT_NS>;
		reset-names = "reset";
		status = "okay";
	};

	spi0: spi@fe610000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe610000 0x0 0x1000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 20>, <&dmac0 21>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>;
		pinctrl-1 = <&spi0clkm0_hs &spi0cs0m0 &spi0cs1m0 &spi0misom0_hs &spi0mosim0_hs>;
		status = "disabled";
	};

	spi1: spi@fe620000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe620000 0x0 0x1000>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 22>, <&dmac0 23>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>;
		pinctrl-1 = <&spi1clkm0_hs &spi1cs0m0 &spi1cs1m0 &spi1misom0_hs &spi1mosim0_hs>;
		status = "disabled";
	};

	spi2: spi@fe630000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe630000 0x0 0x1000>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 24>, <&dmac0 25>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>;
		pinctrl-1 = <&spi2clkm0_hs &spi2cs0m0 &spi2cs1m0 &spi2misom0_hs &spi2mosim0_hs>;
		status = "disabled";
	};

	spi3: spi@fe640000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe640000 0x0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 26>, <&dmac0 27>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>;
		pinctrl-1 = <&spi3clkm0_hs &spi3cs0m0 &spi3cs1m0 &spi3misom0_hs &spi3mosim0_hs>;
		status = "disabled";
	};

	uart1: serial@fe650000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe650000 0x0 0x100>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 2>, <&dmac0 3>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1m0_xfer>;
		status = "disabled";
	};

	uart2: serial@fe660000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe660000 0x0 0x100>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 4>, <&dmac0 5>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m0_xfer>;
		status = "disabled";
	};

	uart3: serial@fe670000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe670000 0x0 0x100>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 6>, <&dmac0 7>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart3m0_xfer>;
		status = "disabled";
	};

	uart4: serial@fe680000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe680000 0x0 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 8>, <&dmac0 9>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart4m0_xfer>;
		status = "disabled";
	};

	uart5: serial@fe690000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe690000 0x0 0x100>;
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 10>, <&dmac0 11>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart5m0_xfer>;
		status = "disabled";
	};

	uart6: serial@fe6a0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6a0000 0x0 0x100>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 12>, <&dmac0 13>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart6m0_xfer>;
		status = "disabled";
	};

	uart7: serial@fe6b0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6b0000 0x0 0x100>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 14>, <&dmac0 15>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart7m0_xfer>;
		status = "disabled";
	};

	uart8: serial@fe6c0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6c0000 0x0 0x100>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 16>, <&dmac0 17>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart8m0_xfer>;
		status = "disabled";
	};

	uart9: serial@fe6d0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6d0000 0x0 0x100>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 18>, <&dmac0 19>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart9m0_xfer>;
		status = "disabled";
	};

	pwm4: pwm@fe6e0000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm4_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm5: pwm@fe6e0010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm5_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm6: pwm@fe6e0020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm6_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm7: pwm@fe6e0030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm7_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm8: pwm@fe6f0000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm8m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm9: pwm@fe6f0010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm9m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm10: pwm@fe6f0020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm10m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm11: pwm@fe6f0030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm11m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm12: pwm@fe700000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm12m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm13: pwm@fe700010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm13m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm14: pwm@fe700020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm14m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm15: pwm@fe700030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm15m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	tsadc: tsadc@fe710000 {
		compatible = "rockchip,rk3568-tsadc";
		reg = <0x0 0xfe710000 0x0 0x100>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,grf = <&grf>;
		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
		assigned-clock-rates = <17000000>, <700000>;
		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
			 <&cru SRST_TSADCPHY>;
		reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
		#thermal-sensor-cells = <1>;
		rockchip,hw-tshut-temp = <120000>;
		rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
		pinctrl-names = "gpio", "otpout";
		pinctrl-0 = <&tsadc_gpio>;
		pinctrl-1 = <&tsadc_shutorg>;
		status = "disabled";
	};

	saradc: saradc@fe720000 {
		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
		reg = <0x0 0xfe720000 0x0 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_P_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	mailbox: mailbox@fe780000 {
		compatible = "rockchip,rk3568-mailbox",
			     "rockchip,rk3368-mailbox";
		reg = <0x0 0xfe780000 0x0 0x1000>;
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	combphy0_us: phy@fe820000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe820000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
		clock-names = "refclk", "apbclk";
		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
		assigned-clock-rates = <24000000>;
		resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
		status = "disabled";
	};

	combphy1_usq: phy@fe830000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe830000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
		clock-names = "refclk", "apbclk";
		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
		assigned-clock-rates = <24000000>;
		resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
		status = "disabled";
	};

	combphy2_psq: phy@fe840000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe840000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
		clock-names = "refclk", "apbclk";
		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
		assigned-clock-rates = <24000000>;
		resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
		status = "disabled";
	};

	mipi_dphy0: mipi-dphy@fe850000 {
		compatible = "rockchip,rk3568-mipi-dphy";
		reg = <0x0 0xfe850000 0x0 0x10000>;
		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
		clock-names = "ref", "pclk";
		clock-output-names = "mipi_dphy_pll";
		#clock-cells = <0>;
		resets = <&cru SRST_P_MIPIDSIPHY0>;
		reset-names = "apb";
		power-domains = <&power RK3568_PD_VO>;
		#phy-cells = <0>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	video_phy0: video-phy@fe850000 {
		compatible = "rockchip,rk3568-video-phy";
		reg = <0x0 0xfe850000  0x0 0x10000>,
		      <0x0 0xfe060000 0x0 0x10000>;
		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
			 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
		clock-names = "ref", "pclk_phy", "pclk_host";
		#clock-cells = <0>;
		resets = <&cru SRST_P_MIPIDSIPHY0>;
		reset-names = "rst";
		power-domains = <&power RK3568_PD_VO>;
		#phy-cells = <0>;
		status = "disabled";
	};

	mipi_dphy1: mipi-dphy@fe860000 {
		compatible = "rockchip,rk3568-mipi-dphy";
		reg = <0x0 0xfe860000 0x0 0x10000>;
		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
		clock-names = "ref", "pclk";
		clock-output-names = "mipi_dphy1_pll";
		#clock-cells = <0>;
		resets = <&cru SRST_P_MIPIDSIPHY1>;
		reset-names = "apb";
		power-domains = <&power RK3568_PD_VO>;
		#phy-cells = <0>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	video_phy1: video-phy@fe860000 {
		compatible = "rockchip,rk3568-video-phy";
		reg = <0x0 0xfe860000 0x0 0x10000>,
		      <0x0 0xfe070000 0x0 0x10000>;
		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
			 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
		clock-names = "ref", "pclk_phy", "pclk_host";
		#clock-cells = <0>;
		resets = <&cru SRST_P_MIPIDSIPHY1>;
		reset-names = "rst";
		power-domains = <&power RK3568_PD_VO>;
		#phy-cells = <0>;
		status = "disabled";
	};

	csi_dphy: csi-dphy@fe870000 {
		compatible = "rockchip,rk3568-csi-dphy";
		reg = <0x0 0xfe870000 0x0 0x1000>;
		clocks = <&cru PCLK_MIPICSIPHY>;
		clock-names = "pclk";
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	usb2phy0: usb2-phy@fe8a0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY0_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		assigned-clocks = <&cru USB480M>;
		assigned-clock-parents = <&usb2phy0>;
		clock-output-names = "usb480m_phy";
		rockchip,usbgrf = <&usb2phy0_grf>;
		status = "disabled";

		u2phy0_host: host-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy0_otg: otg-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};

	usb2phy1: usb2-phy@fe8b0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY1_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		rockchip,usbgrf = <&usb2phy1_grf>;
		status = "disabled";

		u2phy1_host: host-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy1_otg: otg-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};

	pcie30phy: phy@fe8c0000 {
		compatible = "rockchip,rk3568-pcie3-phy";
		reg = <0x0 0xfe8c0000 0x0 0x20000>;
		#phy-cells = <0>;
		clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
			 <&cru PCLK_PCIE30PHY>;
		clock-names = "refclk_m", "refclk_n", "pclk";
		resets = <&cru SRST_PCIE30PHY>;
		reset-names = "phy";
		rockchip,phy-grf = <&pcie30_phy_grf>;
		status = "disabled";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3568-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio@fdd60000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfdd60000 0x0 0x100>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@fe740000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe740000 0x0 0x100>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 32 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@fe750000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe750000 0x0 0x100>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 64 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@fe760000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe760000 0x0 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 96 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@fe770000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe770000 0x0 0x100>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 128 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "rk3568-pinctrl.dtsi"