xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rv1106-thunder-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	memory: memory {
8*4882a593Smuzhiyun		device_type = "memory";
9*4882a593Smuzhiyun		reg = <0x00000000 0x08000000>;
10*4882a593Smuzhiyun	};
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	ramdisk: ramdisk {
13*4882a593Smuzhiyun		compatible = "rockchip,ramdisk";
14*4882a593Smuzhiyun		memory-region = <&ramdisk_r>;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	reserved-memory {
18*4882a593Smuzhiyun		#address-cells = <1>;
19*4882a593Smuzhiyun		#size-cells = <1>;
20*4882a593Smuzhiyun		ranges;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun		rtos: rtos@40000 {
23*4882a593Smuzhiyun			reg = <0x40000 0x40000>;
24*4882a593Smuzhiyun		};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		meta: meta@800000 {
27*4882a593Smuzhiyun			/* reg's offset MUST match with RTOS */
28*4882a593Smuzhiyun			reg = <0x00800000 0x60000>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		rkisp_thunderboot: rkisp@860000 {
32*4882a593Smuzhiyun			/* reg's offset MUST match with RTOS */
33*4882a593Smuzhiyun			/*
34*4882a593Smuzhiyun			 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
35*4882a593Smuzhiyun			 * e.g. 1920x1080: 0xa8c000
36*4882a593Smuzhiyun			 */
37*4882a593Smuzhiyun			reg = <0x00860000 0xa8c000>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		ramdisk_r: ramdisk_r {
41*4882a593Smuzhiyun			reg = <0x12ec000 (10 * 0x00100000)>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		ramdisk_c: ramdisk_c {
45*4882a593Smuzhiyun			reg = <0x1cec000 (5 * 0x00100000)>;
46*4882a593Smuzhiyun		};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun		rkisp1_thunderboot: rkisp1_thunderboot {
49*4882a593Smuzhiyun			/* vicap capture for other camera */
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	thunder_boot_rkisp: thunder-boot-rkisp {
54*4882a593Smuzhiyun		compatible = "rockchip,thunder-boot-rkisp";
55*4882a593Smuzhiyun		clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
56*4882a593Smuzhiyun			 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>,
57*4882a593Smuzhiyun			 <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
58*4882a593Smuzhiyun			 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
59*4882a593Smuzhiyun			 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
60*4882a593Smuzhiyun			 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
61*4882a593Smuzhiyun			 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
62*4882a593Smuzhiyun			 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>,
63*4882a593Smuzhiyun			 <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>,
64*4882a593Smuzhiyun			 <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>,
65*4882a593Smuzhiyun			 <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
66*4882a593Smuzhiyun		clock-names = "aclk_isp", "hclk_isp",
67*4882a593Smuzhiyun			      "clk_isp_core", "clk_isp_core_vicap",
68*4882a593Smuzhiyun			      "aclk_cif","hclk_cif",
69*4882a593Smuzhiyun			      "dclk_cif", "pclk_cif",
70*4882a593Smuzhiyun			      "i0clk_cif", "i1clk_cif",
71*4882a593Smuzhiyun			      "rx0clk_cif", "rx1clk_cif",
72*4882a593Smuzhiyun			      "isp0clk_cif", "sclk_m0_cif",
73*4882a593Smuzhiyun			      "sclk_m1_cif", "pclk_vepu_cif",
74*4882a593Smuzhiyun			      "pclk_csi2host0", "clk_rxbyte_hs0",
75*4882a593Smuzhiyun			      "pclk_csi2host1", "clk_rxbyte_hs1",
76*4882a593Smuzhiyun			      "i2c", "pclk";
77*4882a593Smuzhiyun		status = "okay";
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	thunder_boot_service: thunder-boot-service {
81*4882a593Smuzhiyun		compatible = "rockchip,thunder-boot-service";
82*4882a593Smuzhiyun		mbox-names = "amp-rx";
83*4882a593Smuzhiyun		mboxes = <&mailbox 1>;
84*4882a593Smuzhiyun		resets = <&cru SRST_CORE_MCU>, <&cru SRST_CORE_MCU_PWRUP>,
85*4882a593Smuzhiyun			 <&cru SRST_CORE_MCU_CPU>, <&cru SRST_T_CORE_MCU_CPU>;
86*4882a593Smuzhiyun		reset-names = "core_mcu", "core_mcu_pwrup",
87*4882a593Smuzhiyun			      "core_mcu_cpu", "t_core_mcu_cpu";
88*4882a593Smuzhiyun		memory-region = <&rtos>;
89*4882a593Smuzhiyun		status = "disabled";
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&hw_decompress {
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun	memory-region = <&ramdisk_c>;
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&rkisp_vir0 {
99*4882a593Smuzhiyun	memory-region-thunderboot = <&rkisp_thunderboot>;
100*4882a593Smuzhiyun};
101