1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3528-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/phy/phy.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3528-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/soc/rockchip-system-status.h> 15#include <dt-bindings/suspend/rockchip-rk3528.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/display/rockchip-tve.h> 18 19/ { 20 compatible = "rockchip,rk3528"; 21 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 ethernet0 = &gmac0; 28 ethernet1 = &gmac1; 29 gpio0 = &gpio0; 30 gpio1 = &gpio1; 31 gpio2 = &gpio2; 32 gpio3 = &gpio3; 33 gpio4 = &gpio4; 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 serial0 = &uart0; 43 serial1 = &uart1; 44 serial2 = &uart2; 45 serial3 = &uart3; 46 serial4 = &uart4; 47 serial5 = &uart5; 48 serial6 = &uart6; 49 serial7 = &uart7; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &sfc; 53 }; 54 55 cpus { 56 #address-cells = <2>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 }; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 clocks = <&scmi_clk SCMI_CLK_CPU>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 cpu-idle-states = <&CPU_SLEEP0>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x1>; 90 enable-method = "psci"; 91 clocks = <&scmi_clk SCMI_CLK_CPU>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 cpu-idle-states = <&CPU_SLEEP0>; 94 }; 95 96 cpu2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x2>; 100 enable-method = "psci"; 101 clocks = <&scmi_clk SCMI_CLK_CPU>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 cpu-idle-states = <&CPU_SLEEP1>; 104 }; 105 106 cpu3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x3>; 110 enable-method = "psci"; 111 clocks = <&scmi_clk SCMI_CLK_CPU>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 cpu-idle-states = <&CPU_SLEEP1>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP0: cpu-sleep0 { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 status = "disabled"; 127 }; 128 129 CPU_SLEEP1: cpu-sleep { 130 compatible = "arm,idle-state"; 131 local-timer-stop; 132 arm,psci-suspend-param = <0x0010000>; 133 entry-latency-us = <120>; 134 exit-latency-us = <250>; 135 min-residency-us = <900>; 136 status = "okay"; 137 }; 138 }; 139 }; 140 141 cpu0_opp_table: cpu0-opp-table { 142 compatible = "operating-points-v2"; 143 opp-shared; 144 145 nvmem-cells = <&cpu_leakage>; 146 nvmem-cell-names = "leakage"; 147 148 rockchip,pvtm-voltage-sel = < 149 0 1310 0 150 1311 1340 1 151 1341 1370 2 152 1371 1400 3 153 1401 1430 4 154 1431 1460 5 155 1461 9999 6 156 >; 157 rockchip,pvtm-pvtpll; 158 rockchip,pvtm-offset = <0x18>; 159 rockchip,pvtm-sample-time = <1100>; 160 rockchip,pvtm-freq = <1416000>; 161 rockchip,pvtm-volt = <900000>; 162 rockchip,pvtm-ref-temp = <40>; 163 rockchip,pvtm-temp-prop = <0 0>; 164 rockchip,pvtm-thermal-zone = "soc-thermal"; 165 rockchip,grf = <&grf>; 166 167 opp-408000000 { 168 opp-hz = /bits/ 64 <408000000>; 169 opp-microvolt = <825000 825000 1100000>; 170 clock-latency-ns = <40000>; 171 opp-suspend; 172 }; 173 opp-600000000 { 174 opp-hz = /bits/ 64 <600000000>; 175 opp-microvolt = <825000 825000 1100000>; 176 clock-latency-ns = <40000>; 177 }; 178 opp-816000000 { 179 opp-hz = /bits/ 64 <816000000>; 180 opp-microvolt = <825000 825000 1100000>; 181 clock-latency-ns = <40000>; 182 }; 183 opp-1008000000 { 184 opp-hz = /bits/ 64 <1008000000>; 185 opp-microvolt = <825000 825000 1100000>; 186 clock-latency-ns = <40000>; 187 }; 188 opp-1200000000 { 189 opp-hz = /bits/ 64 <1200000000>; 190 opp-microvolt = <875000 875000 1100000>; 191 opp-microvolt-L1 = <862500 862500 1100000>; 192 opp-microvolt-L2 = <850000 850000 1100000>; 193 opp-microvolt-L3 = <837500 837500 1100000>; 194 opp-microvolt-L4 = <837500 837500 1100000>; 195 opp-microvolt-L5 = <837500 837500 1100000>; 196 opp-microvolt-L6 = <825000 825000 1100000>; 197 clock-latency-ns = <40000>; 198 }; 199 opp-1416000000 { 200 opp-hz = /bits/ 64 <1416000000>; 201 opp-microvolt = <937500 937500 1100000>; 202 opp-microvolt-L1 = <925000 925000 1100000>; 203 opp-microvolt-L2 = <912500 912500 1100000>; 204 opp-microvolt-L3 = <900000 900000 1100000>; 205 opp-microvolt-L4 = <900000 900000 1100000>; 206 opp-microvolt-L5 = <900000 900000 1100000>; 207 opp-microvolt-L6 = <887500 887500 1100000>; 208 clock-latency-ns = <40000>; 209 }; 210 opp-1608000000 { 211 opp-hz = /bits/ 64 <1608000000>; 212 opp-microvolt = <1012500 1012500 1100000>; 213 opp-microvolt-L1 = <1000000 1000000 1100000>; 214 opp-microvolt-L2 = <987500 987500 1100000>; 215 opp-microvolt-L3 = <975000 975000 1100000>; 216 opp-microvolt-L4 = <962500 962500 1100000>; 217 opp-microvolt-L5 = <950000 950000 1100000>; 218 opp-microvolt-L6 = <937500 937500 1100000>; 219 clock-latency-ns = <40000>; 220 }; 221 opp-1800000000 { 222 opp-hz = /bits/ 64 <1800000000>; 223 opp-microvolt = <1062500 1062500 1100000>; 224 opp-microvolt-L1 = <1050000 1050000 1100000>; 225 opp-microvolt-L2 = <1037500 1037500 1100000>; 226 opp-microvolt-L3 = <1025000 1025000 1100000>; 227 opp-microvolt-L4 = <1012500 1012500 1100000>; 228 opp-microvolt-L5 = <1000000 1000000 1100000>; 229 opp-microvolt-L6 = <987500 987500 1100000>; 230 clock-latency-ns = <40000>; 231 }; 232 opp-2016000000 { 233 opp-hz = /bits/ 64 <2016000000>; 234 opp-microvolt = <1100000 1100000 1100000>; 235 opp-microvolt-L1 = <1087500 1087500 1100000>; 236 opp-microvolt-L2 = <1075000 1075000 1100000>; 237 opp-microvolt-L3 = <1062500 1062500 1100000>; 238 opp-microvolt-L4 = <1050000 1050000 1100000>; 239 opp-microvolt-L5 = <1037500 1037500 1100000>; 240 opp-microvolt-L6 = <1025000 1025000 1100000>; 241 clock-latency-ns = <40000>; 242 }; 243 }; 244 245 arm-pmu { 246 compatible = "arm,cortex-a53-pmu"; 247 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 252 }; 253 254 cpuinfo { 255 compatible = "rockchip,cpuinfo"; 256 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 257 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 258 }; 259 260 display_subsystem: display-subsystem { 261 compatible = "rockchip,display-subsystem"; 262 ports = <&vop_out>; 263 status = "disabled"; 264 }; 265 266 firmware: firmware { 267 scmi: scmi { 268 compatible = "arm,scmi-smc"; 269 shmem = <&scmi_shmem>; 270 arm,smc-id = <0x82000010>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 scmi_clk: protocol@14 { 275 reg = <0x14>; 276 #clock-cells = <1>; 277 }; 278 }; 279 }; 280 281 mpp_srv: mpp-srv { 282 compatible = "rockchip,mpp-service"; 283 rockchip,taskqueue-count = <5>; 284 rockchip,resetgroup-count = <5>; 285 status = "disabled"; 286 }; 287 288 psci: psci { 289 compatible = "arm,psci-1.0"; 290 method = "smc"; 291 }; 292 293 rockchip_suspend: rockchip-suspend { 294 compatible = "rockchip,pm-rk3528"; 295 status = "disabled"; 296 rockchip,sleep-debug-en = <0>; 297 rockchip,sleep-mode-config = < 298 (0 299 | RKPM_SLP_ARMPD 300 ) 301 >; 302 rockchip,wakeup-config = < 303 (0 304 | RKPM_CPU0_WKUP_EN 305 | RKPM_GPIO_WKUP_EN 306 ) 307 >; 308 }; 309 310 rockchip_system_monitor: rockchip-system-monitor { 311 compatible = "rockchip,system-monitor"; 312 313 rockchip,thermal-zone = "soc-thermal"; 314 }; 315 316 thermal_zones: thermal-zones { 317 soc_thermal: soc-thermal { 318 polling-delay-passive = <20>; /* milliseconds */ 319 polling-delay = <1000>; /* milliseconds */ 320 321 thermal-sensors = <&tsadc 0>; 322 trips { 323 soc_crit: soc-crit { 324 /* millicelsius */ 325 temperature = <115000>; 326 /* millicelsius */ 327 hysteresis = <2000>; 328 type = "critical"; 329 }; 330 }; 331 }; 332 }; 333 334 timer { 335 compatible = "arm,armv8-timer"; 336 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 337 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 339 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 340 }; 341 342 xin24m: xin24m { 343 compatible = "fixed-clock"; 344 #clock-cells = <0>; 345 clock-frequency = <24000000>; 346 clock-output-names = "xin24m"; 347 }; 348 349 scmi_shmem: scmi-shmem@10f000 { 350 compatible = "arm,scmi-shmem"; 351 reg = <0x0 0x0010f000 0x0 0x100>; 352 }; 353 354 pcie2x1: pcie@fe4f0000 { 355 compatible = "rockchip,rk3528-pcie", "snps,dw-pcie"; 356 #address-cells = <3>; 357 #size-cells = <2>; 358 bus-range = <0x0 0xff>; 359 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, 360 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>, 361 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>, 362 <&cru PCLK_PCIE_PHY>; 363 clock-names = "aclk", "hclk_slv", 364 "hclk_dbi", "pclk_cru", 365 "aux", "pclk", 366 "pipe"; 367 device_type = "pci"; 368 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; 375 #interrupt-cells = <1>; 376 interrupt-map-mask = <0 0 0 7>; 377 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 378 <0 0 0 2 &pcie2x1_intc 1>, 379 <0 0 0 3 &pcie2x1_intc 2>, 380 <0 0 0 4 &pcie2x1_intc 3>; 381 linux,pci-domain = <0>; 382 num-ib-windows = <8>; 383 num-ob-windows = <8>; 384 num-viewport = <4>; 385 max-link-speed = <2>; 386 num-lanes = <1>; 387 phys = <&combphy_pu PHY_TYPE_PCIE>; 388 phy-names = "pcie-phy"; 389 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 390 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 391 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 392 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; 393 reg = <0x0 0xfe4f0000 0x0 0x10000>, 394 <0x1 0x40000000 0x0 0x400000>; 395 reg-names = "pcie-apb", "pcie-dbi"; 396 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>, 397 <&cru SRST_PRESETN_CRU_PCIE>; 398 reset-names = "pcie", "periph", "preset_cru"; 399 status = "disabled"; 400 401 pcie2x1_intc: legacy-interrupt-controller { 402 interrupt-controller; 403 #address-cells = <0>; 404 #interrupt-cells = <1>; 405 interrupt-parent = <&gic>; 406 interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>; 407 }; 408 }; 409 410 usbdrd30: usbdrd { 411 compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3"; 412 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>, 413 <&cru ACLK_USB3OTG>; 414 clock-names = "ref_clk", "suspend_clk", 415 "bus_clk"; 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges; 419 status = "disabled"; 420 421 usbdrd_dwc3: dwc3@fe500000 { 422 compatible = "snps,dwc3"; 423 reg = <0x0 0xfe500000 0x0 0x400000>; 424 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 425 dr_mode = "otg"; 426 phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; 427 phy-names = "usb2-phy", "usb3-phy"; 428 phy_type = "utmi_wide"; 429 resets = <&cru SRST_ARESETN_USB3OTG>; 430 reset-names = "usb3-otg"; 431 snps,dis_enblslpm_quirk; 432 snps,dis-u1u2-quirk; 433 snps,dis-u2-freeclk-exists-quirk; 434 snps,dis-del-phy-power-chg-quirk; 435 snps,dis-tx-ipgap-linecheck-quirk; 436 snps,xhci-trb-ent-quirk; 437 snps,dis_rxdet_inp3_quirk; 438 quirk-skip-phy-init; 439 status = "disabled"; 440 }; 441 }; 442 443 gic: interrupt-controller@fed01000 { 444 compatible = "arm,gic-400"; 445 #interrupt-cells = <3>; 446 #address-cells = <0>; 447 interrupt-controller; 448 reg = <0x0 0xfed01000 0 0x1000>, 449 <0x0 0xfed02000 0 0x2000>, 450 <0x0 0xfed04000 0 0x2000>, 451 <0x0 0xfed06000 0 0x2000>; 452 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 453 }; 454 455 usb_host0_ehci: usb@ff100000 { 456 compatible = "generic-ehci"; 457 reg = <0x0 0xff100000 0x0 0x40000>; 458 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&cru HCLK_USBHOST>, 460 <&cru HCLK_USBHOST_ARB>, 461 <&usb2phy>; 462 clock-names = "usbhost", "arbiter", "utmi"; 463 phys = <&u2phy_host>; 464 phy-names = "usb2-phy"; 465 status = "disabled"; 466 }; 467 468 usb_host0_ohci: usb@ff140000 { 469 compatible = "generic-ohci"; 470 reg = <0x0 0xff140000 0x0 0x40000>; 471 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru HCLK_USBHOST>, 473 <&cru HCLK_USBHOST_ARB>, 474 <&usb2phy>; 475 clock-names = "usbhost", "arbiter", "utmi"; 476 phys = <&u2phy_host>; 477 phy-names = "usb2-phy"; 478 status = "disabled"; 479 }; 480 481 debug: debug@ff190000 { 482 compatible = "rockchip,debug"; 483 reg = <0x0 0xff190000 0x0 0x1000>, 484 <0x0 0xff192000 0x0 0x1000>, 485 <0x0 0xff194000 0x0 0x1000>, 486 <0x0 0xff196000 0x0 0x1000>; 487 }; 488 489 qos_crypto_a: qos@ff200000 { 490 compatible = "syscon"; 491 reg = <0x0 0xff200000 0x0 0x20>; 492 }; 493 494 qos_crypto_p: qos@ff200080 { 495 compatible = "syscon"; 496 reg = <0x0 0xff200080 0x0 0x20>; 497 }; 498 499 qos_dcf: qos@ff200100 { 500 compatible = "syscon"; 501 reg = <0x0 0xff200100 0x0 0x20>; 502 }; 503 504 qos_dft2apb: qos@ff200200 { 505 compatible = "syscon"; 506 reg = <0x0 0xff200200 0x0 0x20>; 507 }; 508 509 qos_dma2ddr: qos@ff200280 { 510 compatible = "syscon"; 511 reg = <0x0 0xff200280 0x0 0x20>; 512 }; 513 514 qos_dmac: qos@ff200300 { 515 compatible = "syscon"; 516 reg = <0x0 0xff200300 0x0 0x20>; 517 }; 518 519 qos_keyreader: qos@ff200380 { 520 compatible = "syscon"; 521 reg = <0x0 0xff200380 0x0 0x20>; 522 }; 523 524 qos_cpu: qos@ff210000 { 525 compatible = "syscon"; 526 reg = <0x0 0xff210000 0x0 0x20>; 527 }; 528 529 qos_debug: qos@ff210080 { 530 compatible = "syscon"; 531 reg = <0x0 0xff210080 0x0 0x20>; 532 }; 533 534 qos_gpu_m0: qos@ff220000 { 535 compatible = "syscon"; 536 reg = <0x0 0xff220000 0x0 0x20>; 537 }; 538 539 qos_gpu_m1: qos@ff220080 { 540 compatible = "syscon"; 541 reg = <0x0 0xff220080 0x0 0x20>; 542 }; 543 544 qos_pmu_mcu: qos@ff240000 { 545 compatible = "syscon"; 546 reg = <0x0 0xff240000 0x0 0x20>; 547 }; 548 549 qos_rkvdec: qos@ff250000 { 550 compatible = "syscon"; 551 reg = <0x0 0xff250000 0x0 0x20>; 552 }; 553 554 qos_rkvenc: qos@ff260000 { 555 compatible = "syscon"; 556 reg = <0x0 0xff260000 0x0 0x20>; 557 }; 558 559 qos_gmac0: qos@ff270000 { 560 compatible = "syscon"; 561 reg = <0x0 0xff270000 0x0 0x20>; 562 }; 563 564 qos_hdcp: qos@ff270080 { 565 compatible = "syscon"; 566 reg = <0x0 0xff270080 0x0 0x20>; 567 }; 568 569 qos_jpegdec: qos@ff270100 { 570 compatible = "syscon"; 571 reg = <0x0 0xff270100 0x0 0x20>; 572 }; 573 574 qos_rga2_m0ro: qos@ff270200 { 575 compatible = "syscon"; 576 reg = <0x0 0xff270200 0x0 0x20>; 577 }; 578 579 qos_rga2_m0wo: qos@ff270280 { 580 compatible = "syscon"; 581 reg = <0x0 0xff270280 0x0 0x20>; 582 }; 583 584 qos_sdmmc0: qos@ff270300 { 585 compatible = "syscon"; 586 reg = <0x0 0xff270300 0x0 0x20>; 587 }; 588 589 qos_usb2host: qos@ff270380 { 590 compatible = "syscon"; 591 reg = <0x0 0xff270380 0x0 0x20>; 592 }; 593 594 qos_vdpp: qos@ff270480 { 595 compatible = "syscon"; 596 reg = <0x0 0xff270480 0x0 0x20>; 597 }; 598 599 qos_vop: qos@ff270500 { 600 compatible = "syscon"; 601 reg = <0x0 0xff270500 0x0 0x20>; 602 }; 603 604 qos_emmc: qos@ff280000 { 605 compatible = "syscon"; 606 reg = <0x0 0xff280000 0x0 0x20>; 607 }; 608 609 qos_fspi: qos@ff280080 { 610 compatible = "syscon"; 611 reg = <0x0 0xff280080 0x0 0x20>; 612 }; 613 614 qos_gmac1: qos@ff280100 { 615 compatible = "syscon"; 616 reg = <0x0 0xff280100 0x0 0x20>; 617 }; 618 619 qos_pcie: qos@ff280180 { 620 compatible = "syscon"; 621 reg = <0x0 0xff280180 0x0 0x20>; 622 }; 623 624 qos_sdio0: qos@ff280200 { 625 compatible = "syscon"; 626 reg = <0x0 0xff280200 0x0 0x20>; 627 }; 628 629 qos_sdio1: qos@ff280280 { 630 compatible = "syscon"; 631 reg = <0x0 0xff280280 0x0 0x20>; 632 }; 633 634 qos_tsp: qos@ff280300 { 635 compatible = "syscon"; 636 reg = <0x0 0xff280300 0x0 0x20>; 637 }; 638 639 qos_usb3otg: qos@ff280380 { 640 compatible = "syscon"; 641 reg = <0x0 0xff280380 0x0 0x20>; 642 }; 643 644 qos_vpu: qos@ff280400 { 645 compatible = "syscon"; 646 reg = <0x0 0xff280400 0x0 0x20>; 647 }; 648 649 /* 650 * Merge all GRF, each independent GRF offset is shown as bellow: 651 * CORE_GRF: 0xff300000 652 * GPU_GRF: 0xff310000 653 * RKVENC_GRF: 0xff320000 654 * DDR_GRF: 0xff330000 655 * VPU_GRF: 0xff340000 656 * COMBO_PIPE_PHY_GRF: 0xff348000 657 * RKVDEC_GRF: 0xff350000 658 * VO_GRF: 0xff360000 659 * PMU_GRF: 0xff370000 660 * SYS_GRF: 0xff380000 661 */ 662 grf: syscon@ff300000 { 663 compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd"; 664 reg = <0x0 0xff300000 0x0 0x90000>; 665 666 grf_cru: grf-clock-controller { 667 compatible = "rockchip,rk3528-grf-cru"; 668 #clock-cells = <1>; 669 }; 670 671 reboot_mode: reboot-mode { 672 compatible = "syscon-reboot-mode"; 673 offset = <0x70200>; 674 mode-bootloader = <BOOT_BL_DOWNLOAD>; 675 mode-charge = <BOOT_CHARGING>; 676 mode-fastboot = <BOOT_FASTBOOT>; 677 mode-loader = <BOOT_BL_DOWNLOAD>; 678 mode-normal = <BOOT_NORMAL>; 679 mode-recovery = <BOOT_RECOVERY>; 680 mode-ums = <BOOT_UMS>; 681 mode-panic = <BOOT_PANIC>; 682 mode-watchdog = <BOOT_WATCHDOG>; 683 }; 684 }; 685 686 cru: clock-controller@ff4a0000 { 687 compatible = "rockchip,rk3528-cru"; 688 reg = <0x0 0xff4a0000 0x0 0x30000>; 689 rockchip,grf = <&grf>; 690 #clock-cells = <1>; 691 #reset-cells = <1>; 692 693 assigned-clocks = 694 <&cru XIN_OSC0_DIV>, 695 <&cru PLL_GPLL>, 696 <&cru PLL_PPLL>, 697 <&cru PLL_CPLL>, 698 <&cru ARMCLK>, 699 <&cru CLK_MATRIX_250M_SRC>, 700 <&cru CLK_MATRIX_500M_SRC>, 701 <&cru CLK_MATRIX_50M_SRC>, 702 <&cru CLK_MATRIX_100M_SRC>, 703 <&cru CLK_MATRIX_150M_SRC>, 704 <&cru CLK_MATRIX_200M_SRC>, 705 <&cru CLK_MATRIX_300M_SRC>, 706 <&cru CLK_MATRIX_339M_SRC>, 707 <&cru CLK_MATRIX_400M_SRC>, 708 <&cru CLK_MATRIX_600M_SRC>, 709 <&cru CLK_PPLL_50M_MATRIX>, 710 <&cru CLK_PPLL_100M_MATRIX>, 711 <&cru CLK_PPLL_125M_MATRIX>, 712 <&cru ACLK_BUS_VOPGL_ROOT>; 713 714 assigned-clock-rates = 715 <32768>, 716 <1188000000>, 717 <1000000000>, 718 <996000000>, 719 <408000000>, 720 <250000000>, 721 <500000000>, 722 <50000000>, 723 <100000000>, 724 <150000000>, 725 <200000000>, 726 <300000000>, 727 <340000000>, 728 <400000000>, 729 <600000000>, 730 <50000000>, 731 <100000000>, 732 <125000000>, 733 <500000000>; 734 }; 735 736 ioc_grf: syscon@ff540000 { 737 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 738 reg = <0x0 0xff540000 0x0 0x40000>; 739 }; 740 741 pmu: power-management@ff600000 { 742 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 743 reg = <0x0 0xff600000 0x0 0x2000>; 744 745 power: power-controller { 746 compatible = "rockchip,rk3528-power-controller"; 747 #power-domain-cells = <1>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "okay"; 751 752 /* These power domains are grouped by VD_GPU */ 753 pd_gpu@RK3528_PD_GPU { 754 reg = <RK3528_PD_GPU>; 755 clocks = <&cru ACLK_GPU_MALI>, 756 <&cru PCLK_GPU_ROOT>; 757 pm_qos = <&qos_gpu_m0>, 758 <&qos_gpu_m1>; 759 }; 760 /* These power domains are grouped by VD_LOGIC */ 761 pd_rkvdec@RK3528_PD_RKVDEC { 762 reg = <RK3528_PD_RKVDEC>; 763 }; 764 pd_rkvenc@RK3528_PD_RKVENC { 765 reg = <RK3528_PD_RKVENC>; 766 }; 767 pd_vo@RK3528_PD_VO { 768 reg = <RK3528_PD_VO>; 769 }; 770 pd_vpu@RK3528_PD_VPU { 771 reg = <RK3528_PD_VPU>; 772 }; 773 }; 774 }; 775 776 mailbox: mailbox@ff630000 { 777 compatible = "rockchip,rk3528-mailbox", 778 "rockchip,rk3368-mailbox"; 779 reg = <0x0 0xff630000 0x0 0x200>; 780 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cru PCLK_PMU_MAILBOX>; 782 clock-names = "pclk_mailbox"; 783 #mbox-cells = <1>; 784 status = "disabled"; 785 }; 786 787 gpu: gpu@ff700000 { 788 compatible = "arm,mali-450"; 789 reg = <0x0 0xff700000 0x0 0x40000>; 790 791 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-names = "Mali_GP_IRQ", 799 "Mali_GP_MMU_IRQ", 800 "IRQPP", 801 "Mali_PP0_IRQ", 802 "Mali_PP0_MMU_IRQ", 803 "Mali_PP1_IRQ", 804 "Mali_PP1_MMU_IRQ"; 805 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>, 806 <&cru PCLK_GPU_ROOT>; 807 clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu"; 808 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 809 assigned-clock-rates = <300000000>; 810 power-domains = <&power RK3528_PD_GPU>; 811 operating-points-v2 = <&gpu_opp_table>; 812 status = "disabled"; 813 814 gpu_power_model: power_model { 815 compatible = "arm,mali-simple-power-model"; 816 voltage = <900>; 817 frequency = <500>; 818 static-power = <300>; 819 dynamic-power = <396>; 820 ts = <32000 4700 (-80) 2>; 821 thermal-zone = "soc-thermal"; 822 }; 823 }; 824 825 gpu_opp_table: gpu-opp-table { 826 compatible = "operating-points-v2"; 827 828 nvmem-cells = <&gpu_leakage>; 829 nvmem-cell-names = "leakage"; 830 831 rockchip,pvtm-voltage-sel = < 832 0 820 0 833 821 840 1 834 841 860 2 835 861 880 3 836 881 900 4 837 901 9999 5 838 >; 839 rockchip,pvtm-pvtpll; 840 rockchip,pvtm-offset = <0x10018>; 841 rockchip,pvtm-sample-time = <1100>; 842 rockchip,pvtm-freq = <700000>; 843 rockchip,pvtm-volt = <900000>; 844 rockchip,pvtm-ref-temp = <40>; 845 rockchip,pvtm-temp-prop = <0 0>; 846 rockchip,pvtm-thermal-zone = "soc-thermal"; 847 rockchip,grf = <&grf>; 848 849 opp-300000000 { 850 opp-hz = /bits/ 64 <300000000>; 851 opp-microvolt = <825000 825000 1000000>; 852 }; 853 opp-500000000 { 854 opp-hz = /bits/ 64 <500000000>; 855 opp-microvolt = <825000 825000 1000000>; 856 }; 857 opp-600000000 { 858 opp-hz = /bits/ 64 <600000000>; 859 opp-microvolt = <825000 825000 1000000>; 860 }; 861 opp-700000000 { 862 opp-hz = /bits/ 64 <700000000>; 863 opp-microvolt = <825000 825000 1000000>; 864 opp-microvolt-L0 = <850000 850000 1000000>; 865 opp-microvolt-L1 = <837500 837500 1000000>; 866 clock-latency-ns = <40000>; 867 }; 868 opp-800000000 { 869 opp-hz = /bits/ 64 <800000000>; 870 opp-microvolt = <900000 900000 1000000>; 871 opp-microvolt-L1 = <887500 887500 1000000>; 872 opp-microvolt-L2 = <875000 875000 1000000>; 873 opp-microvolt-L3 = <862500 862500 1000000>; 874 opp-microvolt-L4 = <850000 850000 1000000>; 875 opp-microvolt-L5 = <837500 837500 1000000>; 876 clock-latency-ns = <40000>; 877 }; 878 }; 879 880 rkvdec: rkvdec@ff740100 { 881 compatible = "rockchip,rkv-decoder-v2"; 882 reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>; 883 reg-names = "regs", "link"; 884 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "irq_dec"; 886 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 887 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; 888 rockchip,normal-rates = <340000000>, <0>, <600000000>; 889 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 890 assigned-clock-rates = <340000000>, <600000000>; 891 resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>, 892 <&cru SRST_RESETN_HEVC_CA_RKVDEC>; 893 reset-names = "video_a", "video_h", "video_hevc_cabac"; 894 power-domains = <&power RK3528_PD_RKVDEC>; 895 iommus = <&rkvdec_mmu>; 896 rockchip,srv = <&mpp_srv>; 897 rockchip,taskqueue-node = <0>; 898 rockchip,resetgroup-node = <0>; 899 rockchip,task-capacity = <16>; 900 status = "disabled"; 901 }; 902 903 rkvdec_mmu: iommu@ff740800 { 904 compatible = "rockchip,iommu-v2"; 905 reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>; 906 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 907 interrupt-names = "rkvdec_mmu"; 908 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 909 clock-names = "aclk", "iface", "clk_hevc_cabac"; 910 power-domains = <&power RK3528_PD_RKVDEC>; 911 #iommu-cells = <0>; 912 status = "disabled"; 913 }; 914 915 rkvenc: rkvenc@ff780000 { 916 compatible = "rockchip,rkv-encoder-v2"; 917 reg = <0x0 0xff780000 0x0 0x6000>; 918 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 919 interrupt-names = "irq_rkvenc"; 920 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 921 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 922 rockchip,normal-rates = <300000000>, <0>, <300000000>; 923 resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>, 924 <&cru SRST_RESETN_CORE_RKVENC>; 925 reset-names = "video_a", "video_h", "video_core"; 926 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 927 assigned-clock-rates = <300000000>, <300000000>; 928 power-domains = <&power RK3528_PD_RKVENC>; 929 iommus = <&rkvenc_mmu>; 930 rockchip,srv = <&mpp_srv>; 931 rockchip,taskqueue-node = <1>; 932 rockchip,resetgroup-node = <1>; 933 status = "disabled"; 934 }; 935 936 rkvenc_mmu: iommu@ff78f000 { 937 compatible = "rockchip,iommu-v2"; 938 reg = <0x0 0xff78f000 0x0 0x40>; 939 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "rkvenc_mmu"; 941 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 942 clock-names = "aclk", "iface"; 943 power-domains = <&power RK3528_PD_RKVENC>; 944 #iommu-cells = <0>; 945 status = "disabled"; 946 }; 947 948 vdpu: vdpu@ff7c0400 { 949 compatible = "rockchip,vpu-decoder-v2"; 950 reg = <0x0 0xff7c0400 0x0 0x400>; 951 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 952 interrupt-names = "irq_dec"; 953 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 954 clock-names = "aclk_vcodec", "hclk_vcodec"; 955 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; 956 reset-names = "shared_video_a", "shared_video_h"; 957 power-domains = <&power RK3528_PD_VPU>; 958 iommus = <&vdpu_mmu>; 959 rockchip,srv = <&mpp_srv>; 960 rockchip,taskqueue-node = <2>; 961 rockchip,resetgroup-node = <2>; 962 status = "disabled"; 963 }; 964 965 vdpu_mmu: iommu@ff7c0800 { 966 compatible = "rockchip,iommu-v2"; 967 reg = <0x0 0xff7c0800 0x0 0x40>; 968 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 969 interrupt-names = "vdpu_mmu"; 970 clock-names = "aclk", "iface"; 971 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 972 power-domains = <&power RK3528_PD_VPU>; 973 #iommu-cells = <0>; 974 status = "disabled"; 975 }; 976 977 avsd: avsd_plus@ff7c1000 { 978 compatible = "rockchip,avs-plus-decoder"; 979 reg = <0x0 0xff7c1000 0x0 0x200>; 980 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 981 interrupt-names = "irq_dec"; 982 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 983 clock-names = "aclk_vcodec", "hclk_vcodec"; 984 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; 985 reset-names = "shared_video_a", "shared_video_h"; 986 iommus = <&vdpu_mmu>; 987 power-domains = <&power RK3528_PD_VPU>; 988 rockchip,srv = <&mpp_srv>; 989 rockchip,taskqueue-node = <2>; 990 rockchip,resetgroup-node = <2>; 991 status = "disabled"; 992 }; 993 994 vop: vop@ff840000 { 995 compatible = "rockchip,rk3528-vop"; 996 reg = <0x0 0xff840000 0x0 0x3000>, 997 <0x0 0xff845000 0x0 0x1000>, 998 <0x0 0xff846400 0x0 0x800>; 999 reg-names = "regs", 1000 "gamma_lut", 1001 "acm_regs"; 1002 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&cru ACLK_VOP>, 1004 <&cru HCLK_VOP>, 1005 <&cru DCLK_VOP0>, 1006 <&cru DCLK_VOP1>; 1007 clock-names = "aclk_vop", 1008 "hclk_vop", 1009 "dclk_vp0", 1010 "dclk_vp1"; 1011 assigned-clocks = <&cru DCLK_VOP0>; 1012 assigned-clock-parents = <&hdmiphy>; 1013 iommus = <&vop_mmu>; 1014 rockchip,grf = <&grf>; 1015 status = "disabled"; 1016 1017 vop_out: ports { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 port@0 { 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 reg = <0>; 1025 1026 vp0_out_hdmi: endpoint@0 { 1027 reg = <0>; 1028 remote-endpoint = <&hdmi_in_vp0>; 1029 }; 1030 }; 1031 1032 port@1 { 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 reg = <1>; 1036 1037 vp1_out_tve: endpoint@0 { 1038 reg = <0>; 1039 remote-endpoint = <&tve_in_vp1>; 1040 }; 1041 }; 1042 }; 1043 }; 1044 1045 vop_mmu: iommu@ff847e00 { 1046 compatible = "rockchip,iommu-v2"; 1047 reg = <0x0 0xff847e00 0x0 0x100>; 1048 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1049 interrupt-names = "vop_mmu"; 1050 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1051 clock-names = "aclk", "iface"; 1052 #iommu-cells = <0>; 1053 rockchip,disable-device-link-resume; 1054 rockchip,shootdown-entire; 1055 status = "disabled"; 1056 }; 1057 1058 rga2: rga@ff850000 { 1059 compatible = "rockchip,rga2_core0"; 1060 reg = <0x0 0xff850000 0x0 0x1000>; 1061 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1062 interrupt-names = "rga2_irq"; 1063 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 1064 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 1065 iommus = <&rga2_mmu>; 1066 status = "disabled"; 1067 }; 1068 1069 rga2_mmu: iommu@ff850f00 { 1070 compatible = "rockchip,iommu-v2"; 1071 reg = <0x0 0xff850f00 0x0 0x100>; 1072 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "rga2_mmu"; 1074 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>; 1075 clock-names = "aclk", "iface"; 1076 #iommu-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 iep: iep@ff860000 { 1081 compatible = "rockchip,iep-v2"; 1082 reg = <0x0 0xff860000 0x0 0x500>; 1083 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1085 clock-names = "aclk", "hclk", "sclk"; 1086 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1087 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; 1088 assigned-clock-rates = <340000000>, <340000000>; 1089 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 1090 <&cru SRST_RESETN_CORE_VDPP>; 1091 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1092 rockchip,srv = <&mpp_srv>; 1093 rockchip,taskqueue-node = <3>; 1094 rockchip,resetgroup-node = <3>; 1095 power-domains = <&power RK3528_PD_VO>; 1096 iommus = <&iep_mmu>; 1097 status = "disabled"; 1098 }; 1099 1100 iep_mmu: iommu@ff860800 { 1101 compatible = "rockchip,iommu-v2"; 1102 reg = <0x0 0xff860800 0x0 0x100>; 1103 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1104 interrupt-names = "iep_mmu"; 1105 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>; 1106 clock-names = "aclk", "iface"; 1107 #iommu-cells = <0>; 1108 power-domains = <&power RK3528_PD_VO>; 1109 status = "disabled"; 1110 }; 1111 1112 vdpp: vdpp@ff861000 { 1113 compatible = "rockchip,vdpp-v1"; 1114 reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>; 1115 reg-names = "vdpp_regs", "zme_regs"; 1116 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1118 clock-names = "aclk", "hclk", "sclk"; 1119 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1120 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; 1121 assigned-clock-rates = <340000000>, <340000000>; 1122 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 1123 <&cru SRST_RESETN_CORE_VDPP>; 1124 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1125 rockchip,srv = <&mpp_srv>; 1126 rockchip,taskqueue-node = <3>; 1127 rockchip,resetgroup-node = <3>; 1128 power-domains = <&power RK3528_PD_VO>; 1129 iommus = <&iep_mmu>; 1130 status = "disabled"; 1131 }; 1132 1133 jpegd: jpegd@ff870000 { 1134 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1135 reg = <0x0 0xff870000 0x0 0x400>; 1136 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 1138 clock-names = "aclk_vcodec", "hclk_vcodec"; 1139 rockchip,disable-auto-freq; 1140 resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>; 1141 reset-names = "video_a", "video_h"; 1142 power-domains = <&power RK3528_PD_VO>; 1143 iommus = <&jpegd_mmu>; 1144 rockchip,srv = <&mpp_srv>; 1145 rockchip,taskqueue-node = <4>; 1146 rockchip,resetgroup-node = <4>; 1147 status = "disabled"; 1148 }; 1149 1150 jpegd_mmu: iommu@ff870480 { 1151 compatible = "rockchip,iommu-v2"; 1152 reg = <0x0 0xff870480 0x0 0x40>; 1153 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1154 interrupt-names = "jpegd_mmu"; 1155 clock-names = "aclk", "iface"; 1156 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 1157 power-domains = <&power RK3528_PD_VO>; 1158 #iommu-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 tve: tve@ff880000 { 1163 compatible = "rockchip,rk3528-tve"; 1164 reg = <0x0 0xff880000 0x0 0x4000>, 1165 <0x0 0xffde0000 0x0 0x300>; 1166 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&cru HCLK_CVBS>, 1168 <&cru PCLK_VCDCPHY>, 1169 <&cru DCLK_CVBS>, 1170 <&cru DCLK_4X_CVBS>; 1171 clock-names = "hclk", 1172 "pclk_vdac", 1173 "dclk", 1174 "dclk_4x"; 1175 rockchip,lumafilter0 = <0x000a0ffa>; 1176 rockchip,lumafilter1 = <0x0ff4001a>; 1177 rockchip,lumafilter2 = <0x00110fd2>; 1178 rockchip,lumafilter3 = <0x0fe80051>; 1179 rockchip,lumafilter4 = <0x001a0f74>; 1180 rockchip,lumafilter5 = <0x0fe600ec>; 1181 rockchip,lumafilter6 = <0x0ffa0e43>; 1182 rockchip,lumafilter7 = <0x08200527>; 1183 rockchip,tve-upsample = <DCLK_UPSAMPLEx4>; 1184 rockchip,grf = <&grf>; 1185 status = "disabled"; 1186 1187 ports { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 1191 port@0 { 1192 reg = <0>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 1196 tve_in_vp1: endpoint@0 { 1197 reg = <0>; 1198 remote-endpoint = <&vp1_out_tve>; 1199 status = "disabled"; 1200 }; 1201 }; 1202 }; 1203 }; 1204 1205 hdcp2: hdcp2@ff8c0000 { 1206 compatible = "rockchip,rk3528-hdmi-hdcp2"; 1207 reg = <0x0 0xff8c0000 0x0 0x2000>; 1208 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>, 1210 <&cru HCLK_HDCP>; 1211 clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi"; 1212 status = "disabled"; 1213 }; 1214 1215 hdmi: hdmi@ff8d0000 { 1216 compatible = "rockchip,rk3528-dw-hdmi"; 1217 reg = <0x0 0xff8d0000 0x0 0x20000>, 1218 <0x0 0xff610000 0x0 0x200>; 1219 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&cru PCLK_HDMI>, 1222 <&cru CLK_SFR_HDMI>, 1223 <&cru CLK_CEC_HDMI>; 1224 clock-names = "iahb", "isfr", "cec"; 1225 reg-io-width = <4>; 1226 rockchip,grf = <&grf>; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&hdmi_pins>; 1229 phys = <&hdmiphy>; 1230 phy-names = "hdmi"; 1231 #sound-dai-cells = <0>; 1232 hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; 1233 status = "disabled"; 1234 1235 ports { 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 1239 port@0 { 1240 reg = <0>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 1244 hdmi_in_vp0: endpoint@0 { 1245 reg = <0>; 1246 remote-endpoint = <&vp0_out_hdmi>; 1247 status = "disabled"; 1248 }; 1249 }; 1250 }; 1251 }; 1252 1253 can0: can@ff960000 { 1254 compatible = "rockchip,rk3528-can"; 1255 reg = <0x0 0xff960000 0x0 0x100>; 1256 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1257 assigned-clocks = <&cru CLK_CAN0>; 1258 assigned-clock-rates = <198000000>; 1259 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 1260 clock-names = "baudclk", "apb_pclk"; 1261 resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_PRESETN_CAN0>; 1262 reset-names = "can", "can-apb"; 1263 status = "disabled"; 1264 }; 1265 1266 can1: can@ff970000 { 1267 compatible = "rockchip,rk3528-can"; 1268 reg = <0x0 0xff970000 0x0 0x100>; 1269 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1270 assigned-clocks = <&cru CLK_CAN1>; 1271 assigned-clock-rates = <198000000>; 1272 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 1273 clock-names = "baudclk", "apb_pclk"; 1274 resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_PRESETN_CAN1>; 1275 reset-names = "can", "can-apb"; 1276 status = "disabled"; 1277 }; 1278 1279 can2: can@ff980000 { 1280 compatible = "rockchip,rk3528-can"; 1281 reg = <0x0 0xff980000 0x0 0x100>; 1282 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1283 assigned-clocks = <&cru CLK_CAN2>; 1284 assigned-clock-rates = <198000000>; 1285 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 1286 clock-names = "baudclk", "apb_pclk"; 1287 resets = <&cru SRST_RESETN_CAN2>, <&cru SRST_PRESETN_CAN2>; 1288 reset-names = "can", "can-apb"; 1289 status = "disabled"; 1290 }; 1291 1292 can3: can@ff990000 { 1293 compatible = "rockchip,rk3528-can"; 1294 reg = <0x0 0xff990000 0x0 0x100>; 1295 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1296 assigned-clocks = <&cru CLK_CAN3>; 1297 assigned-clock-rates = <198000000>; 1298 clocks = <&cru CLK_CAN3>, <&cru PCLK_CAN3>; 1299 clock-names = "baudclk", "apb_pclk"; 1300 resets = <&cru SRST_RESETN_CAN3>, <&cru SRST_PRESETN_CAN3>; 1301 reset-names = "can", "can-apb"; 1302 status = "disabled"; 1303 }; 1304 1305 spi0: spi@ff9c0000 { 1306 compatible = "rockchip,rk3066-spi"; 1307 reg = <0x0 0xff9c0000 0x0 0x1000>; 1308 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1312 clock-names = "spiclk", "apb_pclk"; 1313 dmas = <&dmac 25>, <&dmac 24>; 1314 dma-names = "tx", "rx"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>; 1317 status = "disabled"; 1318 }; 1319 1320 spi1: spi@ff9d0000 { 1321 compatible = "rockchip,rk3066-spi"; 1322 reg = <0x0 0xff9d0000 0x0 0x1000>; 1323 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1327 clock-names = "spiclk", "apb_pclk"; 1328 dmas = <&dmac 31>, <&dmac 30>; 1329 dma-names = "tx", "rx"; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>; 1332 status = "disabled"; 1333 }; 1334 1335 uart0: serial@ff9f0000 { 1336 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1337 reg = <0x0 0xff9f0000 0x0 0x100>; 1338 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1340 clock-names = "baudclk", "apb_pclk"; 1341 reg-shift = <2>; 1342 reg-io-width = <4>; 1343 dmas = <&dmac 9>, <&dmac 8>; 1344 status = "disabled"; 1345 }; 1346 1347 uart1: serial@ff9f8000 { 1348 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1349 reg = <0x0 0xff9f8000 0x0 0x100>; 1350 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1352 clock-names = "baudclk", "apb_pclk"; 1353 reg-shift = <2>; 1354 reg-io-width = <4>; 1355 dmas = <&dmac 11>, <&dmac 10>; 1356 status = "disabled"; 1357 }; 1358 1359 uart2: serial@ffa00000 { 1360 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1361 reg = <0x0 0xffa00000 0x0 0x100>; 1362 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1363 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1364 clock-names = "baudclk", "apb_pclk"; 1365 reg-shift = <2>; 1366 reg-io-width = <4>; 1367 dmas = <&dmac 13>, <&dmac 12>; 1368 status = "disabled"; 1369 }; 1370 1371 uart3: serial@ffa08000 { 1372 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1373 reg = <0x0 0xffa08000 0x0 0x100>; 1374 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1376 clock-names = "baudclk", "apb_pclk"; 1377 reg-shift = <2>; 1378 reg-io-width = <4>; 1379 dmas = <&dmac 15>, <&dmac 14>; 1380 status = "disabled"; 1381 }; 1382 1383 uart4: serial@ffa10000 { 1384 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1385 reg = <0x0 0xffa10000 0x0 0x100>; 1386 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1387 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1388 clock-names = "baudclk", "apb_pclk"; 1389 reg-shift = <2>; 1390 reg-io-width = <4>; 1391 dmas = <&dmac 17>, <&dmac 16>; 1392 status = "disabled"; 1393 }; 1394 1395 uart5: serial@ffa18000 { 1396 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1397 reg = <0x0 0xffa18000 0x0 0x100>; 1398 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1400 clock-names = "baudclk", "apb_pclk"; 1401 reg-shift = <2>; 1402 reg-io-width = <4>; 1403 dmas = <&dmac 19>, <&dmac 18>; 1404 status = "disabled"; 1405 }; 1406 1407 uart6: serial@ffa20000 { 1408 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1409 reg = <0x0 0xffa20000 0x0 0x100>; 1410 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1412 clock-names = "baudclk", "apb_pclk"; 1413 reg-shift = <2>; 1414 reg-io-width = <4>; 1415 dmas = <&dmac 21>, <&dmac 20>; 1416 status = "disabled"; 1417 }; 1418 1419 uart7: serial@ffa28000 { 1420 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1421 reg = <0x0 0xffa28000 0x0 0x100>; 1422 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1424 clock-names = "baudclk", "apb_pclk"; 1425 reg-shift = <2>; 1426 reg-io-width = <4>; 1427 dmas = <&dmac 23>, <&dmac 22>; 1428 status = "disabled"; 1429 }; 1430 1431 i2c0: i2c@ffa50000 { 1432 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1433 reg = <0x0 0xffa50000 0x0 0x1000>; 1434 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1435 clock-names = "i2c", "pclk"; 1436 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&i2c0m0_xfer>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 i2c1: i2c@ffa58000 { 1445 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1446 reg = <0x0 0xffa58000 0x0 0x1000>; 1447 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1448 clock-names = "i2c", "pclk"; 1449 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&i2c1m0_xfer>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 i2c2: i2c@ffa60000 { 1458 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1459 reg = <0x0 0xffa60000 0x0 0x1000>; 1460 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1461 clock-names = "i2c", "pclk"; 1462 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&i2c2m0_xfer>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 status = "disabled"; 1468 }; 1469 1470 i2c3: i2c@ffa68000 { 1471 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1472 reg = <0x0 0xffa68000 0x0 0x1000>; 1473 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1474 clock-names = "i2c", "pclk"; 1475 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&i2c3m0_xfer>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 status = "disabled"; 1481 }; 1482 1483 i2c4: i2c@ffa70000 { 1484 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1485 reg = <0x0 0xffa70000 0x0 0x1000>; 1486 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1487 clock-names = "i2c", "pclk"; 1488 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&i2c4_xfer>; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 i2c5: i2c@ffa78000 { 1497 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1498 reg = <0x0 0xffa78000 0x0 0x1000>; 1499 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1500 clock-names = "i2c", "pclk"; 1501 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&i2c5m0_xfer>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 1509 i2c6: i2c@ffa80000 { 1510 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1511 reg = <0x0 0xffa80000 0x0 0x1000>; 1512 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1513 clock-names = "i2c", "pclk"; 1514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&i2c6m0_xfer>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 status = "disabled"; 1520 }; 1521 1522 i2c7: i2c@ffa88000 { 1523 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1524 reg = <0x0 0xffa88000 0x0 0x1000>; 1525 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1526 clock-names = "i2c", "pclk"; 1527 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1528 pinctrl-names = "default"; 1529 pinctrl-0 = <&i2c7_xfer>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 pwm0: pwm@ffa90000 { 1536 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1537 reg = <0x0 0xffa90000 0x0 0x10>; 1538 #pwm-cells = <3>; 1539 pinctrl-names = "active"; 1540 pinctrl-0 = <&pwm0m0_pins>; 1541 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1542 clock-names = "pwm", "pclk"; 1543 status = "disabled"; 1544 }; 1545 1546 pwm1: pwm@ffa90010 { 1547 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1548 reg = <0x0 0xffa90010 0x0 0x10>; 1549 #pwm-cells = <3>; 1550 pinctrl-names = "active"; 1551 pinctrl-0 = <&pwm1m0_pins>; 1552 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1553 clock-names = "pwm", "pclk"; 1554 status = "disabled"; 1555 }; 1556 1557 pwm2: pwm@ffa90020 { 1558 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1559 reg = <0x0 0xffa90020 0x0 0x10>; 1560 #pwm-cells = <3>; 1561 pinctrl-names = "active"; 1562 pinctrl-0 = <&pwm2m0_pins>; 1563 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1564 clock-names = "pwm", "pclk"; 1565 status = "disabled"; 1566 }; 1567 1568 pwm3: pwm@ffa90030 { 1569 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1570 reg = <0x0 0xffa90030 0x0 0x10>; 1571 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1573 #pwm-cells = <3>; 1574 pinctrl-names = "active"; 1575 pinctrl-0 = <&pwm3m0_pins>; 1576 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1577 clock-names = "pwm", "pclk"; 1578 status = "disabled"; 1579 }; 1580 1581 pwm4: pwm@ffa98000 { 1582 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1583 reg = <0x0 0xffa98000 0x0 0x10>; 1584 #pwm-cells = <3>; 1585 pinctrl-names = "active"; 1586 pinctrl-0 = <&pwm4m0_pins>; 1587 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1588 clock-names = "pwm", "pclk"; 1589 status = "disabled"; 1590 }; 1591 1592 pwm5: pwm@ffa98010 { 1593 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1594 reg = <0x0 0xffa98010 0x0 0x10>; 1595 #pwm-cells = <3>; 1596 pinctrl-names = "active"; 1597 pinctrl-0 = <&pwm5m0_pins>; 1598 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1599 clock-names = "pwm", "pclk"; 1600 status = "disabled"; 1601 }; 1602 1603 pwm6: pwm@ffa98020 { 1604 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1605 reg = <0x0 0xffa98020 0x0 0x10>; 1606 #pwm-cells = <3>; 1607 pinctrl-names = "active"; 1608 pinctrl-0 = <&pwm6m0_pins>; 1609 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1610 clock-names = "pwm", "pclk"; 1611 status = "disabled"; 1612 }; 1613 1614 pwm7: pwm@ffa98030 { 1615 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1616 reg = <0x0 0xffa98030 0x0 0x10>; 1617 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1619 #pwm-cells = <3>; 1620 pinctrl-names = "active"; 1621 pinctrl-0 = <&pwm7m0_pins>; 1622 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1623 clock-names = "pwm", "pclk"; 1624 status = "disabled"; 1625 }; 1626 1627 rktimer: timer@ffab0000 { 1628 compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer"; 1629 reg = <0x0 0xffab0000 0x0 0x20>; 1630 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1632 clock-names = "pclk", "timer"; 1633 }; 1634 1635 wdt: watchdog@ffac0000 { 1636 compatible = "snps,dw-wdt"; 1637 reg = <0x0 0xffac0000 0x0 0x100>; 1638 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1639 clock-names = "tclk", "pclk"; 1640 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1641 status = "disabled"; 1642 }; 1643 1644 tsadc: tsadc@ffad0000 { 1645 compatible = "rockchip,rk3528-tsadc"; 1646 reg = <0x0 0xffad0000 0x0 0x400>; 1647 rockchip,grf = <&grf>; 1648 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; 1650 clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; 1651 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 1652 assigned-clock-rates = <1200000>, <12000000>; 1653 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>; 1654 reset-names = "tsadc", "tsadc-apb"; 1655 #thermal-sensor-cells = <1>; 1656 rockchip,hw-tshut-temp = <120000>; 1657 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1658 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1659 status = "disabled"; 1660 }; 1661 1662 saradc: saradc@ffae0000 { 1663 compatible = "rockchip,rk3528-saradc"; 1664 reg = <0x0 0xffae0000 0x0 0x10000>; 1665 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1666 #io-channel-cells = <1>; 1667 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1668 clock-names = "saradc", "apb_pclk"; 1669 resets = <&cru SRST_PRESETN_SARADC>; 1670 reset-names = "saradc-apb"; 1671 status = "disabled"; 1672 }; 1673 1674 sai3: sai@ffb70000 { 1675 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1676 reg = <0x0 0xffb70000 0x0 0x1000>; 1677 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1678 clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>; 1679 clock-names = "mclk", "hclk"; 1680 dmas = <&dmac 5>; 1681 dma-names = "tx"; 1682 resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>; 1683 reset-names = "m", "h"; 1684 #sound-dai-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 sai0: sai@ffb80000 { 1689 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1690 reg = <0x0 0xffb80000 0x0 0x1000>; 1691 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1692 clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>; 1693 clock-names = "mclk", "hclk"; 1694 dmas = <&dmac 1>, <&dmac 0>; 1695 dma-names = "tx", "rx"; 1696 resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>; 1697 reset-names = "m", "h"; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&i2s0m0_pins>; 1700 #sound-dai-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 sai2: sai@ffb90000 { 1705 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1706 reg = <0x0 0xffb90000 0x0 0x1000>; 1707 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1708 clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>; 1709 clock-names = "mclk", "hclk"; 1710 dmas = <&dmac 4>; 1711 dma-names = "tx"; 1712 resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>; 1713 reset-names = "m", "h"; 1714 #sound-dai-cells = <0>; 1715 status = "disabled"; 1716 }; 1717 1718 sai1: sai@ffba0000 { 1719 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1720 reg = <0x0 0xffba0000 0x0 0x1000>; 1721 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>; 1723 clock-names = "mclk", "hclk"; 1724 dmas = <&dmac 3>, <&dmac 2>; 1725 dma-names = "tx", "rx"; 1726 resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>; 1727 reset-names = "m", "h"; 1728 pinctrl-names = "default"; 1729 pinctrl-0 = <&i2s1_pins>; 1730 #sound-dai-cells = <0>; 1731 status = "disabled"; 1732 }; 1733 1734 pdm: pdm@ffbb0000 { 1735 compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm"; 1736 reg = <0x0 0xffbb0000 0x0 0x1000>; 1737 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1738 clock-names = "pdm_clk", "pdm_hclk"; 1739 dmas = <&dmac 6>; 1740 dma-names = "rx"; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&pdm_clk0 1743 &pdm_clk1 1744 &pdm_sdi0 1745 &pdm_sdi1 1746 &pdm_sdi2 1747 &pdm_sdi3>; 1748 #sound-dai-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 spdif_8ch: spdif@ffbc0000 { 1753 compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif"; 1754 reg = <0x0 0xffbc0000 0x0 0x1000>; 1755 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1756 dmas = <&dmac 7>; 1757 dma-names = "tx"; 1758 clock-names = "mclk", "hclk"; 1759 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; 1760 #sound-dai-cells = <0>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&spdifm0_pins>; 1763 status = "disabled"; 1764 }; 1765 1766 gmac0: ethernet@ffbd0000 { 1767 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1768 reg = <0x0 0xffbd0000 0x0 0x10000>; 1769 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1771 interrupt-names = "macirq", "eth_wake_irq"; 1772 rockchip,grf = <&grf>; 1773 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 1774 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 1775 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 1776 clock-names = "stmmaceth", "clk_mac_ref", 1777 "mac_clk_rx", "mac_clk_tx", 1778 "pclk_mac", "aclk_mac"; 1779 resets = <&cru SRST_ARESETN_MAC_VO>; 1780 reset-names = "stmmaceth"; 1781 1782 snps,mixed-burst; 1783 snps,tso; 1784 1785 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1786 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1787 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1788 1789 phy-mode = "rmii"; 1790 clock_in_out = "input"; 1791 phy-handle = <&rmii0_phy>; 1792 1793 nvmem-cells = <&macphy_bgs>; 1794 nvmem-cell-names = "bgs"; 1795 status = "disabled"; 1796 1797 mdio0: mdio { 1798 compatible = "snps,dwmac-mdio"; 1799 #address-cells = <0x1>; 1800 #size-cells = <0x0>; 1801 rmii0_phy: ethernet-phy@2 { 1802 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 1803 reg = <2>; 1804 clocks = <&cru CLK_MACPHY>; 1805 resets = <&cru SRST_RESETN_MACPHY>; 1806 phy-is-integrated; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>; 1809 nvmem-cells = <&macphy_txlevel>; 1810 nvmem-cell-names = "txlevel"; 1811 }; 1812 }; 1813 1814 gmac0_stmmac_axi_setup: stmmac-axi-config { 1815 snps,wr_osr_lmt = <4>; 1816 snps,rd_osr_lmt = <8>; 1817 snps,blen = <0 0 0 0 16 8 4>; 1818 }; 1819 1820 gmac0_mtl_rx_setup: rx-queues-config { 1821 snps,rx-queues-to-use = <1>; 1822 queue0 {}; 1823 }; 1824 1825 gmac0_mtl_tx_setup: tx-queues-config { 1826 snps,tx-queues-to-use = <1>; 1827 queue0 {}; 1828 }; 1829 }; 1830 1831 gmac1: ethernet@ffbe0000 { 1832 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1833 reg = <0x0 0xffbe0000 0x0 0x10000>; 1834 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "macirq", "eth_wake_irq"; 1837 rockchip,grf = <&grf>; 1838 clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>, 1839 <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>; 1840 clock-names = "stmmaceth", "clk_mac_ref", 1841 "pclk_mac", "aclk_mac"; 1842 resets = <&cru SRST_ARESETN_MAC>; 1843 reset-names = "stmmaceth"; 1844 1845 snps,mixed-burst; 1846 snps,tso; 1847 1848 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1849 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1850 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1851 1852 status = "disabled"; 1853 1854 mdio1: mdio { 1855 compatible = "snps,dwmac-mdio"; 1856 #address-cells = <0x1>; 1857 #size-cells = <0x0>; 1858 }; 1859 1860 gmac1_stmmac_axi_setup: stmmac-axi-config { 1861 snps,wr_osr_lmt = <4>; 1862 snps,rd_osr_lmt = <8>; 1863 snps,blen = <0 0 0 0 16 8 4>; 1864 }; 1865 1866 gmac1_mtl_rx_setup: rx-queues-config { 1867 snps,rx-queues-to-use = <1>; 1868 queue0 {}; 1869 }; 1870 1871 gmac1_mtl_tx_setup: tx-queues-config { 1872 snps,tx-queues-to-use = <1>; 1873 queue0 {}; 1874 }; 1875 }; 1876 1877 sdhci: mmc@ffbf0000 { 1878 compatible = "rockchip,rk3528-dwcmshc"; 1879 reg = <0x0 0xffbf0000 0x0 0x10000>; 1880 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1881 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1882 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1883 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1884 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1885 <&cru TCLK_EMMC>; 1886 clock-names = "core", "bus", "axi", "block", "timer"; 1887 resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>, 1888 <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>, 1889 <&cru SRST_TRESETN_EMMC>; 1890 reset-names = "core", "bus", "axi", "block", "timer"; 1891 max-frequency = <200000000>; 1892 status = "disabled"; 1893 }; 1894 1895 sfc: spi@ffc00000 { 1896 compatible = "rockchip,sfc"; 1897 reg = <0x0 0xffc00000 0x0 0x4000>; 1898 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1899 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1900 clock-names = "clk_sfc", "hclk_sfc"; 1901 assigned-clocks = <&cru SCLK_SFC>; 1902 assigned-clock-rates = <100000000>; 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 status = "disabled"; 1906 }; 1907 1908 sdio0: mmc@ffc10000 { 1909 compatible = "rockchip,rk3528-dw-mshc", 1910 "rockchip,rk3288-dw-mshc"; 1911 reg = <0x0 0xffc10000 0x0 0x4000>; 1912 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1913 max-frequency = <150000000>; 1914 clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>, 1915 <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>; 1916 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1917 fifo-depth = <0x100>; 1918 resets = <&cru SRST_HRESETN_SDIO0>; 1919 reset-names = "reset"; 1920 rockchip,use-v2-tuning; 1921 status = "disabled"; 1922 }; 1923 1924 sdio1: mmc@ffc20000 { 1925 compatible = "rockchip,rk3528-dw-mshc", 1926 "rockchip,rk3288-dw-mshc"; 1927 reg = <0x0 0xffc20000 0x0 0x4000>; 1928 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1929 max-frequency = <150000000>; 1930 clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>, 1931 <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>; 1932 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1933 fifo-depth = <0x100>; 1934 resets = <&cru SRST_HRESETN_SDIO1>; 1935 reset-names = "reset"; 1936 rockchip,use-v2-tuning; 1937 status = "disabled"; 1938 }; 1939 1940 sdmmc: mmc@ffc30000 { 1941 compatible = "rockchip,rk3528-dw-mshc", 1942 "rockchip,rk3288-dw-mshc"; 1943 reg = <0x0 0xffc30000 0x0 0x4000>; 1944 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1945 max-frequency = <150000000>; 1946 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>, 1947 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 1948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1949 fifo-depth = <0x100>; 1950 resets = <&cru SRST_HRESETN_SDMMC0>; 1951 reset-names = "reset"; 1952 rockchip,use-v2-tuning; 1953 pinctrl-names = "default"; 1954 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1955 status = "disabled"; 1956 }; 1957 1958 crypto: crypto@ffc40000 { 1959 compatible = "rockchip,crypto-v4"; 1960 reg = <0x0 0xffc40000 0x0 0x2000>; 1961 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1962 clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>, 1963 <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; 1964 clock-names = "aclk", "hclk", "sclk", "pka"; 1965 assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; 1966 assigned-clock-rates = <300000000>, <300000000>; 1967 resets = <&cru SRST_RESETN_CORE_CRYPTO>; 1968 reset-names = "crypto-rst"; 1969 status = "disabled"; 1970 }; 1971 1972 rng: rng@ffc50000 { 1973 compatible = "rockchip,rkrng"; 1974 reg = <0x0 0xffc50000 0x0 0x200>; 1975 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1976 clocks = <&scmi_clk SCMI_HCLK_TRNG>; 1977 clock-names = "hclk_trng"; 1978 resets = <&cru SRST_HRESETN_TRNG_NS>; 1979 reset-names = "reset"; 1980 status = "disabled"; 1981 }; 1982 1983 otp: otp@ffce0000 { 1984 compatible = "rockchip,rk3528-otp"; 1985 reg = <0x0 0xffce0000 0x0 0x4000>; 1986 #address-cells = <1>; 1987 #size-cells = <1>; 1988 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 1989 <&cru PCLK_OTPC_NS>; 1990 clock-names = "usr", "sbpi", "apb"; 1991 resets = <&cru SRST_RESETN_USER_OTPC_NS>, 1992 <&cru SRST_RESETN_SBPI_OTPC_NS>, 1993 <&cru SRST_PRESETN_OTPC_NS>; 1994 reset-names = "usr", "sbpi", "apb"; 1995 1996 /* Data cells */ 1997 cpu_code: cpu-code@2 { 1998 reg = <0x02 0x2>; 1999 }; 2000 otp_cpu_version: cpu-version@8 { 2001 reg = <0x08 0x1>; 2002 bits = <3 3>; 2003 }; 2004 otp_id: id@a { 2005 reg = <0x0a 0x10>; 2006 }; 2007 cpu_leakage: cpu-leakage@1a { 2008 reg = <0x1a 0x1>; 2009 }; 2010 log_leakage: log-leakage@1b { 2011 reg = <0x1b 0x1>; 2012 }; 2013 gpu_leakage: gpu-leakage@1c { 2014 reg = <0x1c 0x1>; 2015 }; 2016 macphy_bgs: macphy-bgs@2d { 2017 reg = <0x2d 0x1>; 2018 }; 2019 macphy_txlevel: macphy-txlevel@2e { 2020 reg = <0x2e 0x2>; 2021 }; 2022 }; 2023 2024 dmac: dma-controller@ffd60000 { 2025 compatible = "arm,pl330", "arm,primecell"; 2026 reg = <0x0 0xffd60000 0x0 0x4000>; 2027 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&cru ACLK_DMAC>; 2037 clock-names = "apb_pclk"; 2038 #dma-cells = <1>; 2039 arm,pl330-periph-burst; 2040 }; 2041 2042 hwlock: hwspinlock@ffd70000 { 2043 compatible = "rockchip,hwspinlock"; 2044 reg = <0x0 0xffd70000 0x0 0x100>; 2045 #hwlock-cells = <1>; 2046 status = "disabled"; 2047 }; 2048 2049 combphy_pu: phy@ffdc0000 { 2050 compatible = "rockchip,rk3528-naneng-combphy"; 2051 reg = <0x0 0xffdc0000 0x0 0x10000>; 2052 #phy-cells = <1>; 2053 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>; 2054 clock-names = "refclk", "apbclk", "pipe_clk"; 2055 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; 2056 assigned-clock-rates = <100000000>; 2057 resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>; 2058 reset-names = "combphy-apb", "combphy"; 2059 rockchip,pipe-grf = <&grf>; 2060 rockchip,pipe-phy-grf = <&grf>; 2061 status = "disabled"; 2062 }; 2063 2064 usb2phy: usb2-phy@ffdf0000 { 2065 compatible = "rockchip,rk3528-usb2phy"; 2066 reg = <0x0 0xffdf0000 0x0 0x10000>; 2067 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 2068 clock-names = "phyclk", "apb_pclk"; 2069 #clock-cells = <0>; 2070 rockchip,usbgrf = <&grf>; 2071 status = "disabled"; 2072 2073 u2phy_otg: otg-port { 2074 #phy-cells = <0>; 2075 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2078 interrupt-names = "otg-bvalid", 2079 "otg-id", 2080 "linestate"; 2081 status = "disabled"; 2082 }; 2083 2084 u2phy_host: host-port { 2085 #phy-cells = <0>; 2086 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2087 interrupt-names = "linestate"; 2088 status = "disabled"; 2089 }; 2090 }; 2091 2092 hdmiphy: hdmiphy@ffe00000 { 2093 compatible = "rockchip,rk3528-hdmi-phy"; 2094 reg = <0x0 0xffe00000 0x0 0x10000>; 2095 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2096 #phy-cells = <0>; 2097 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>; 2098 clock-names = "sysclk", "refclk"; 2099 #clock-cells = <0>; 2100 clock-output-names = "clk_hdmiphy_pixel_io"; 2101 status = "disabled"; 2102 }; 2103 2104 acodec: acodec@ffe10000 { 2105 compatible = "rockchip,rk3528-codec"; 2106 reg = <0x0 0xffe10000 0x0 0x1000>; 2107 #sound-dai-cells = <0>; 2108 clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>; 2109 clock-names = "pclk", "mclk"; 2110 resets = <&cru SRST_PRESETN_ACODEC>; 2111 reset-names = "acodec"; 2112 status = "disabled"; 2113 }; 2114 2115 pinctrl: pinctrl { 2116 compatible = "rockchip,rk3528-pinctrl"; 2117 rockchip,grf = <&ioc_grf>; 2118 #address-cells = <2>; 2119 #size-cells = <2>; 2120 ranges; 2121 2122 gpio0: gpio@ff610000 { 2123 compatible = "rockchip,gpio-bank"; 2124 reg = <0x0 0xff610000 0x0 0x200>; 2125 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2126 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2127 gpio-controller; 2128 #gpio-cells = <2>; 2129 gpio-ranges = <&pinctrl 0 0 32>; 2130 interrupt-controller; 2131 #interrupt-cells = <2>; 2132 }; 2133 2134 gpio1: gpio@ffaf0000 { 2135 compatible = "rockchip,gpio-bank"; 2136 reg = <0x0 0xffaf0000 0x0 0x200>; 2137 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 2138 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2139 gpio-controller; 2140 #gpio-cells = <2>; 2141 gpio-ranges = <&pinctrl 0 32 32>; 2142 interrupt-controller; 2143 #interrupt-cells = <2>; 2144 }; 2145 2146 gpio2: gpio@ffb00000 { 2147 compatible = "rockchip,gpio-bank"; 2148 reg = <0x0 0xffb00000 0x0 0x200>; 2149 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 2150 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2151 gpio-controller; 2152 #gpio-cells = <2>; 2153 gpio-ranges = <&pinctrl 0 64 32>; 2154 interrupt-controller; 2155 #interrupt-cells = <2>; 2156 }; 2157 2158 gpio3: gpio@ffb10000 { 2159 compatible = "rockchip,gpio-bank"; 2160 reg = <0x0 0xffb10000 0x0 0x200>; 2161 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2163 gpio-controller; 2164 #gpio-cells = <2>; 2165 gpio-ranges = <&pinctrl 0 96 32>; 2166 interrupt-controller; 2167 #interrupt-cells = <2>; 2168 }; 2169 2170 gpio4: gpio@ffb20000 { 2171 compatible = "rockchip,gpio-bank"; 2172 reg = <0x0 0xffb20000 0x0 0x200>; 2173 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2174 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2175 gpio-controller; 2176 #gpio-cells = <2>; 2177 gpio-ranges = <&pinctrl 0 128 32>; 2178 interrupt-controller; 2179 #interrupt-cells = <2>; 2180 }; 2181 }; 2182}; 2183 2184#include "rk3528-pinctrl.dtsi" 2185