1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/ { 7 8}; 9 10&cru { 11 assigned-clocks = 12 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 13 <&cru ARMCLK>, 14 <&cru CLK_50M_SRC>, <&cru CLK_100M_SRC>, 15 <&cru CLK_150M_SRC>, <&cru CLK_200M_SRC>, 16 <&cru CLK_250M_SRC>, <&cru CLK_300M_SRC>, 17 <&cru CLK_339M_SRC>, <&cru CLK_400M_SRC>, 18 <&cru CLK_450M_SRC>, <&cru CLK_500M_SRC>, 19 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 20 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 21 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 22 <&cru HCLK_PMU_ROOT>; 23 assigned-clock-rates = 24 <983040000>, <1188000000>, 25 <1104000000>, 26 <50000000>, <100000000>, 27 <150000000>, <200000000>, 28 <250000000>, <300000000>, 29 <340000000>, <400000000>, 30 <450000000>, <500000000>, 31 <400000000>, <200000000>, 32 <100000000>, <300000000>, 33 <100000000>, <100000000>, 34 <200000000>; 35}; 36 37&fiq_debugger { 38 rockchip,irq-mode-enable = <1>; 39 status = "okay"; 40}; 41 42&i2s0_8ch { 43 status = "okay"; 44 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>, 45 <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>, 46 <&cru PLL_GPLL>, <&cru PLL_GPLL>; 47 clock-names = "mclk_tx", "mclk_rx", "hclk", 48 "mclk_tx_src", "mclk_rx_src", 49 "mclk_root0", "mclk_root1"; 50 rockchip,mclk-calibrate; 51}; 52 53&mpp_srv { 54 status = "okay"; 55}; 56 57&mpp_vcodec { 58 status = "okay"; 59}; 60 61&npu { 62 status = "okay"; 63}; 64 65&rga2 { 66 status = "okay"; 67}; 68 69&rkvenc { 70 status = "okay"; 71}; 72 73&rkvenc_pp { 74 status = "okay"; 75}; 76 77&rng { 78 status = "okay"; 79}; 80 81&rve { 82 status = "okay"; 83}; 84 85&u2phy { 86 status = "okay"; 87}; 88 89&u2phy_otg { 90 status = "okay"; 91}; 92 93&usbdrd { 94 status = "okay"; 95}; 96 97&usbdrd_dwc3 { 98 dr_mode = "peripheral"; 99 status = "okay"; 100}; 101