1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/rk3568-power.h> 14 15/ { 16 compatible = "rockchip,rk3568"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 dsi0 = &dsi0; 24 dsi1 = &dsi1; 25 ethernet0 = &gmac0; 26 ethernet1 = &gmac1; 27 gpio0 = &gpio0; 28 gpio1 = &gpio1; 29 gpio2 = &gpio2; 30 gpio3 = &gpio3; 31 gpio4 = &gpio4; 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 lvds0 = &lvds0; 39 lvds1 = &lvds1; 40 serial0 = &uart0; 41 serial1 = &uart1; 42 serial2 = &uart2; 43 serial3 = &uart3; 44 serial4 = &uart4; 45 serial5 = &uart5; 46 serial6 = &uart6; 47 serial7 = &uart7; 48 serial8 = &uart8; 49 serial9 = &uart9; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 }; 55 56 cpus { 57 #address-cells = <2>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 clocks = <&cru ARMCLK>; 66 operating-points-v2 = <&cpu0_opp_table>; 67 }; 68 69 cpu1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x100>; 73 enable-method = "psci"; 74 clocks = <&cru ARMCLK>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu2: cpu@200 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a55"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 }; 86 87 cpu3: cpu@300 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a55"; 90 reg = <0x0 0x300>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLK>; 93 operating-points-v2 = <&cpu0_opp_table>; 94 }; 95 }; 96 97 cpu0_opp_table: cpu0-opp-table { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 101 opp-408000000 { 102 opp-hz = /bits/ 64 <408000000>; 103 opp-microvolt = <1000000 1000000 1250000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-600000000 { 107 opp-hz = /bits/ 64 <600000000>; 108 opp-microvolt = <1000000 1000000 1250000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-816000000 { 112 opp-hz = /bits/ 64 <816000000>; 113 opp-microvolt = <1000000 1000000 1250000>; 114 clock-latency-ns = <40000>; 115 opp-suspend; 116 }; 117 opp-1008000000 { 118 opp-hz = /bits/ 64 <1008000000>; 119 opp-microvolt = <1000000 1000000 1250000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <1000000 1000000 1250000>; 125 clock-latency-ns = <40000>; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; 131 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 display_subsystem: display-subsystem { 139 compatible = "rockchip,display-subsystem"; 140 ports = <&vop_out>; 141 }; 142 143 mpp_srv: mpp-srv { 144 compatible = "rockchip,mpp-service"; 145 rockchip,taskqueue-count = <5>; 146 rockchip,resetgroup-count = <5>; 147 status = "disabled"; 148 }; 149 150 psci: psci { 151 compatible = "arm,psci-1.0"; 152 method = "smc"; 153 }; 154 155 thermal_zones: thermal-zones { 156 soc_thermal: soc-thermal { 157 polling-delay-passive = <20>; /* milliseconds */ 158 polling-delay = <1000>; /* milliseconds */ 159 160 thermal-sensors = <&tsadc 0>; 161 trips { 162 soc_crit: soc-crit { 163 /* millicelsius */ 164 temperature = <115000>; 165 /* millicelsius */ 166 hysteresis = <2000>; 167 type = "critical"; 168 }; 169 }; 170 }; 171 172 gpu_thermal: gpu-thermal { 173 polling-delay-passive = <20>; /* milliseconds */ 174 polling-delay = <1000>; /* milliseconds */ 175 176 thermal-sensors = <&tsadc 1>; 177 }; 178 }; 179 180 timer { 181 compatible = "arm,armv8-timer"; 182 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 183 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 185 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 gmac0_clkin: external-gmac0-clock { 189 compatible = "fixed-clock"; 190 clock-frequency = <125000000>; 191 clock-output-names = "gmac0_clkin"; 192 #clock-cells = <0>; 193 }; 194 195 gmac1_clkin: external-gmac1-clock { 196 compatible = "fixed-clock"; 197 clock-frequency = <125000000>; 198 clock-output-names = "gmac1_clkin"; 199 #clock-cells = <0>; 200 }; 201 202 xin24m: xin24m { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <24000000>; 206 clock-output-names = "xin24m"; 207 }; 208 209 sata0: sata@fc000000 { 210 compatible = "snps,dwc-ahci"; 211 reg = <0 0xfc000000 0 0x1000>; 212 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 213 <&cru CLK_SATA0_RXOOB>; 214 clock-names = "sata", "pmalive", "rxoob"; 215 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "hostc"; 217 phys = <&combphy0_us PHY_TYPE_SATA>; 218 phy-names = "sata-phy"; 219 ports-implemented = <0x1>; 220 power-domains = <&power RK3568_PD_PIPE>; 221 status = "disabled"; 222 }; 223 224 sata1: sata@fc400000 { 225 compatible = "snps,dwc-ahci"; 226 reg = <0 0xfc400000 0 0x1000>; 227 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 228 <&cru CLK_SATA1_RXOOB>; 229 clock-names = "sata", "pmalive", "rxoob"; 230 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "hostc"; 232 phys = <&combphy1_usq PHY_TYPE_SATA>; 233 phy-names = "sata-phy"; 234 ports-implemented = <0x1>; 235 power-domains = <&power RK3568_PD_PIPE>; 236 status = "disabled"; 237 }; 238 239 sata2: sata@fc800000 { 240 compatible = "snps,dwc-ahci"; 241 reg = <0 0xfc800000 0 0x1000>; 242 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 243 <&cru CLK_SATA2_RXOOB>; 244 clock-names = "sata", "pmalive", "rxoob"; 245 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 246 interrupt-names = "hostc"; 247 phys = <&combphy2_psq PHY_TYPE_SATA>; 248 phy-names = "sata-phy"; 249 ports-implemented = <0x1>; 250 power-domains = <&power RK3568_PD_PIPE>; 251 status = "disabled"; 252 }; 253 254 usbdrd30: usbdrd { 255 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 256 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 257 <&cru ACLK_USB3OTG0>; 258 clock-names = "ref_clk", "suspend_clk", 259 "bus_clk"; 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 status = "disabled"; 264 265 usbdrd_dwc3: dwc3@fcc00000 { 266 compatible = "snps,dwc3"; 267 reg = <0x0 0xfcc00000 0x0 0x400000>; 268 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 269 dr_mode = "otg"; 270 phys = <&u2phy0_otg>; 271 phy-names = "usb2-phy"; 272 phy_type = "utmi_wide"; 273 power-domains = <&power RK3568_PD_PIPE>; 274 resets = <&cru SRST_USB3OTG0>; 275 reset-names = "usb3-otg"; 276 snps,dis_enblslpm_quirk; 277 snps,dis-u2-freeclk-exists-quirk; 278 snps,dis_u2_susphy_quirk; 279 snps,dis-del-phy-power-chg-quirk; 280 snps,dis-tx-ipgap-linecheck-quirk; 281 snps,xhci-trb-ent-quirk; 282 status = "disabled"; 283 }; 284 }; 285 286 usbhost30: usbhost { 287 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 288 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 289 <&cru ACLK_USB3OTG1>; 290 clock-names = "ref_clk", "suspend_clk", 291 "bus_clk"; 292 #address-cells = <2>; 293 #size-cells = <2>; 294 ranges; 295 status = "disabled"; 296 297 usbhost_dwc3: dwc3@fd000000 { 298 compatible = "snps,dwc3"; 299 reg = <0x0 0xfd000000 0x0 0x400000>; 300 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 301 dr_mode = "host"; 302 phys = <&u2phy0_host>; 303 phy-names = "usb2-phy"; 304 phy_type = "utmi_wide"; 305 power-domains = <&power RK3568_PD_PIPE>; 306 resets = <&cru SRST_USB3OTG1>; 307 reset-names = "usb3-host"; 308 snps,dis_enblslpm_quirk; 309 snps,dis-u2-freeclk-exists-quirk; 310 snps,dis_u2_susphy_quirk; 311 snps,dis-del-phy-power-chg-quirk; 312 snps,dis-tx-ipgap-linecheck-quirk; 313 snps,xhci-trb-ent-quirk; 314 status = "disabled"; 315 }; 316 }; 317 318 gic: interrupt-controller@fd400000 { 319 compatible = "arm,gic-v3"; 320 #interrupt-cells = <3>; 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges; 324 interrupt-controller; 325 326 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 327 <0x0 0xfd460000 0 0xc0000>; /* GICR */ 328 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 329 its: interrupt-controller@fd440000 { 330 compatible = "arm,gic-v3-its"; 331 msi-controller; 332 reg = <0x0 0xfd440000 0x0 0x20000>; 333 status = "disabled"; 334 }; 335 }; 336 337 usb_host0_ehci: usb@fd800000 { 338 compatible = "generic-ehci"; 339 reg = <0x0 0xfd800000 0x0 0x40000>; 340 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 342 <&cru PCLK_USB>, <&usb2phy1>; 343 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 344 phys = <&u2phy1_otg>; 345 phy-names = "usb2-phy"; 346 status = "disabled"; 347 }; 348 349 usb_host0_ohci: usb@fd840000 { 350 compatible = "generic-ohci"; 351 reg = <0x0 0xfd840000 0x0 0x40000>; 352 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 354 <&cru PCLK_USB>, <&usb2phy1>; 355 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 356 phys = <&u2phy1_otg>; 357 phy-names = "usb2-phy"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ehci: usb@fd880000 { 362 compatible = "generic-ehci"; 363 reg = <0x0 0xfd880000 0x0 0x40000>; 364 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 366 <&cru PCLK_USB>, <&usb2phy1>; 367 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 368 phys = <&u2phy1_host>; 369 phy-names = "usb2-phy"; 370 status = "disabled"; 371 }; 372 373 usb_host1_ohci: usb@fd8c0000 { 374 compatible = "generic-ohci"; 375 reg = <0x0 0xfd8c0000 0x0 0x40000>; 376 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 378 <&cru PCLK_USB>, <&usb2phy1>; 379 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 380 phys = <&u2phy1_host>; 381 phy-names = "usb2-phy"; 382 status = "disabled"; 383 }; 384 385 pmugrf: syscon@fdc20000 { 386 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 387 reg = <0x0 0xfdc20000 0x0 0x10000>; 388 389 pmu_io_domains: io-domains { 390 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 391 status = "disabled"; 392 }; 393 394 reboot_mode: reboot-mode { 395 compatible = "syscon-reboot-mode"; 396 offset = <0x200>; 397 mode-bootloader = <BOOT_BL_DOWNLOAD>; 398 mode-charge = <BOOT_CHARGING>; 399 mode-fastboot = <BOOT_FASTBOOT>; 400 mode-loader = <BOOT_BL_DOWNLOAD>; 401 mode-normal = <BOOT_NORMAL>; 402 mode-recovery = <BOOT_RECOVERY>; 403 mode-ums = <BOOT_UMS>; 404 mode-panic = <BOOT_PANIC>; 405 mode-watchdog = <BOOT_WATCHDOG>; 406 }; 407 }; 408 409 pipegrf: syscon@fdc50000 { 410 compatible = "rockchip,rk3568-pipegrf", "syscon"; 411 reg = <0x0 0xfdc50000 0x0 0x1000>; 412 }; 413 414 grf: syscon@fdc60000 { 415 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 416 reg = <0x0 0xfdc60000 0x0 0x10000>; 417 418 io_domains: io-domains { 419 compatible = "rockchip,rk3568-io-voltage-domain"; 420 status = "disabled"; 421 }; 422 423 lvds0: lvds0 { 424 compatible = "rockchip,rk3568-lvds"; 425 phys = <&video_phy0>; 426 phy-names = "phy"; 427 status = "disabled"; 428 429 ports { 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 port@0 { 434 reg = <0>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 lvds0_in_vp1: endpoint@0 { 439 reg = <0>; 440 remote-endpoint = <&vp1_out_lvds0>; 441 }; 442 443 lvds0_in_vp2: endpoint@1 { 444 reg = <1>; 445 remote-endpoint = <&vp2_out_lvds0>; 446 }; 447 }; 448 }; 449 }; 450 451 lvds1: lvds1 { 452 compatible = "rockchip,rk3568-lvds"; 453 phys = <&video_phy1>; 454 phy-names = "phy"; 455 status = "disabled"; 456 457 ports { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 461 port@0 { 462 reg = <0>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 lvds1_in_vp1: endpoint@0 { 467 reg = <0>; 468 remote-endpoint = <&vp1_out_lvds1>; 469 }; 470 471 lvds1_in_vp2: endpoint@1 { 472 reg = <1>; 473 remote-endpoint = <&vp2_out_lvds1>; 474 }; 475 }; 476 }; 477 }; 478 479 rgb: rgb { 480 compatible = "rockchip,rk3568-rgb"; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&lcdc_ctl>; 483 status = "disabled"; 484 485 ports { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 489 port@0 { 490 reg = <0>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 494 rgb_in_vp2: endpoint@0 { 495 reg = <0>; 496 remote-endpoint = <&vp2_out_rgb>; 497 }; 498 }; 499 500 }; 501 }; 502 503 }; 504 505 pipe_phy_grf0: syscon@fdc70000 { 506 compatible = "rockchip,pipe-phy-grf", "syscon"; 507 reg = <0x0 0xfdc70000 0x0 0x1000>; 508 }; 509 510 pipe_phy_grf1: syscon@fdc80000 { 511 compatible = "rockchip,pipe-phy-grf", "syscon"; 512 reg = <0x0 0xfdc80000 0x0 0x1000>; 513 }; 514 515 pipe_phy_grf2: syscon@fdc90000 { 516 compatible = "rockchip,pipe-phy-grf", "syscon"; 517 reg = <0x0 0xfdc90000 0x0 0x1000>; 518 }; 519 520 usb2phy0_grf: syscon@fdca0000 { 521 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 522 reg = <0x0 0xfdca0000 0x0 0x8000>; 523 }; 524 525 usb2phy1_grf: syscon@fdca8000 { 526 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 527 reg = <0x0 0xfdca8000 0x0 0x8000>; 528 }; 529 530 edp_phy: edp-phy@fdcb0000 { 531 compatible = "rockchip,rk3568-edp-phy"; 532 reg = <0x0 0xfdcb0000 0x0 0x8000>; 533 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>; 534 clock-names = "refclk", "pclk"; 535 resets = <&cru SRST_P_EDPPHY_GRF>; 536 reset-names = "apb"; 537 #phy-cells = <0>; 538 status = "disabled"; 539 }; 540 541 pcie30_phy_grf: syscon@fdcb8000 { 542 compatible = "rockchip,pcie30-phy-grf", "syscon"; 543 reg = <0x0 0xfdcb8000 0x0 0x10000>; 544 }; 545 546 pmucru: clock-controller@fdd00000 { 547 compatible = "rockchip,rk3568-pmucru"; 548 reg = <0x0 0xfdd00000 0x0 0x1000>; 549 rockchip,grf = <&grf>; 550 #clock-cells = <1>; 551 #reset-cells = <1>; 552 }; 553 554 cru: clock-controller@fdd20000 { 555 compatible = "rockchip,rk3568-cru"; 556 reg = <0x0 0xfdd20000 0x0 0x1000>; 557 rockchip,grf = <&grf>; 558 #clock-cells = <1>; 559 #reset-cells = <1>; 560 561 assigned-clocks = 562 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>, 563 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, 564 <&cru PLL_GPLL>, <&cru ARMCLK>, 565 <&cru ACLK_BUS>, <&cru PCLK_BUS>, 566 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, 567 <&cru HCLK_TOP>, <&cru PCLK_TOP>, 568 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, 569 <&cru PLL_NPLL>; 570 assigned-clock-rates = 571 <32768>, <200000000>, 572 <100000000>, <1000000000>, 573 <1188000000>, <600000000>, 574 <150000000>, <100000000>, 575 <300000000>, <200000000>, 576 <150000000>, <100000000>, 577 <300000000>, <150000000>, 578 <1200000000>; 579 assigned-clock-parents = 580 <&pmucru CLK_RTC32K_FRAC>; 581 }; 582 583 i2c0: i2c@fdd40000 { 584 compatible = "rockchip,rk3399-i2c"; 585 reg = <0x0 0xfdd40000 0x0 0x1000>; 586 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 587 clock-names = "i2c", "pclk"; 588 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&i2c0_xfer>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 uart0: serial@fdd50000 { 597 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 598 reg = <0x0 0xfdd50000 0x0 0x100>; 599 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 601 clock-names = "baudclk", "apb_pclk"; 602 reg-shift = <2>; 603 reg-io-width = <4>; 604 dmas = <&dmac0 0>, <&dmac0 1>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&uart0_xfer>; 607 status = "disabled"; 608 }; 609 610 pwm0: pwm@fdd70000 { 611 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 612 reg = <0x0 0xfdd70000 0x0 0x10>; 613 #pwm-cells = <3>; 614 pinctrl-names = "active"; 615 pinctrl-0 = <&pwm0m0_pins>; 616 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 617 clock-names = "pwm", "pclk"; 618 status = "disabled"; 619 }; 620 621 pwm1: pwm@fdd70010 { 622 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 623 reg = <0x0 0xfdd70010 0x0 0x10>; 624 #pwm-cells = <3>; 625 pinctrl-names = "active"; 626 pinctrl-0 = <&pwm1m0_pins>; 627 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 628 clock-names = "pwm", "pclk"; 629 status = "disabled"; 630 }; 631 632 pwm2: pwm@fdd70020 { 633 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 634 reg = <0x0 0xfdd70020 0x0 0x10>; 635 #pwm-cells = <3>; 636 pinctrl-names = "active"; 637 pinctrl-0 = <&pwm2m0_pins>; 638 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 639 clock-names = "pwm", "pclk"; 640 status = "disabled"; 641 }; 642 643 pwm3: pwm@fdd70030 { 644 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 645 reg = <0x0 0xfdd70030 0x0 0x10>; 646 #pwm-cells = <3>; 647 pinctrl-names = "active"; 648 pinctrl-0 = <&pwm3_pins>; 649 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 650 clock-names = "pwm", "pclk"; 651 status = "disabled"; 652 }; 653 654 pmu: power-management@fdd90000 { 655 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 656 reg = <0x0 0xfdd90000 0x0 0x1000>; 657 658 power: power-controller { 659 compatible = "rockchip,rk3568-power-controller"; 660 #power-domain-cells = <1>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "okay"; 664 665 /* These power domains are grouped by VD_NPU */ 666 pd_npu@RK3568_PD_NPU { 667 reg = <RK3568_PD_NPU>; 668 clocks = <&cru ACLK_NPU_PRE>, 669 <&cru HCLK_NPU_PRE>, 670 <&cru PCLK_NPU_PRE>; 671 pm_qos = <&qos_npu>; 672 }; 673 /* These power domains are grouped by VD_GPU */ 674 pd_gpu@RK3568_PD_GPU { 675 reg = <RK3568_PD_GPU>; 676 clocks = <&cru ACLK_GPU_PRE>, 677 <&cru PCLK_GPU_PRE>; 678 pm_qos = <&qos_gpu>; 679 }; 680 /* These power domains are grouped by VD_LOGIC */ 681 pd_vi@RK3568_PD_VI { 682 reg = <RK3568_PD_VI>; 683 clocks = <&cru HCLK_VI>, 684 <&cru PCLK_VI>; 685 pm_qos = <&qos_isp>, 686 <&qos_vicap0>, 687 <&qos_vicap1>; 688 }; 689 pd_vo@RK3568_PD_VO { 690 reg = <RK3568_PD_VO>; 691 clocks = <&cru HCLK_VO>, 692 <&cru PCLK_VO>, 693 <&cru ACLK_VOP_PRE>; 694 pm_qos = <&qos_hdcp>, 695 <&qos_vop_m0>, 696 <&qos_vop_m1>; 697 }; 698 pd_rga@RK3568_PD_RGA { 699 reg = <RK3568_PD_RGA>; 700 clocks = <&cru HCLK_RGA_PRE>, 701 <&cru PCLK_RGA_PRE>; 702 pm_qos = <&qos_ebc>, 703 <&qos_iep>, 704 <&qos_jpeg_dec>, 705 <&qos_jpeg_enc>, 706 <&qos_rga_rd>, 707 <&qos_rga_wr>; 708 }; 709 pd_vpu@RK3568_PD_VPU { 710 reg = <RK3568_PD_VPU>; 711 clocks = <&cru HCLK_VPU_PRE>; 712 pm_qos = <&qos_vpu>; 713 }; 714 pd_rkvdec@RK3568_PD_RKVDEC { 715 clocks = <&cru HCLK_RKVDEC_PRE>; 716 reg = <RK3568_PD_RKVDEC>; 717 pm_qos = <&qos_rkvdec>; 718 }; 719 pd_rkvenc@RK3568_PD_RKVENC { 720 reg = <RK3568_PD_RKVENC>; 721 clocks = <&cru HCLK_RKVENC_PRE>; 722 pm_qos = <&qos_rkvenc_rd_m0>, 723 <&qos_rkvenc_rd_m1>, 724 <&qos_rkvenc_wr_m0>; 725 }; 726 pd_pipe@RK3568_PD_PIPE { 727 reg = <RK3568_PD_PIPE>; 728 clocks = <&cru PCLK_PIPE>; 729 pm_qos = <&qos_pcie2x1>, 730 <&qos_pcie3x1>, 731 <&qos_pcie3x2>, 732 <&qos_sata0>, 733 <&qos_sata1>, 734 <&qos_sata2>, 735 <&qos_usb3_0>, 736 <&qos_usb3_1>; 737 }; 738 }; 739 }; 740 741 pvtm@fde00000 { 742 compatible = "rockchip,rk3568-core-pvtm"; 743 reg = <0x0 0xfde00000 0x0 0x100>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 pvtm@0 { 747 reg = <0>; 748 clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; 749 clock-names = "clk", "pclk"; 750 resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; 751 reset-names = "rts", "rst-p"; 752 thermal-zone = "soc-thermal"; 753 }; 754 }; 755 756 gpu: gpu@fde60000 { 757 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 758 reg = <0x0 0xfde60000 0x0 0x4000>; 759 760 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 763 interrupt-names = "GPU", "MMU", "JOB"; 764 765 upthreshold = <40>; 766 downdifferential = <10>; 767 768 clocks = <&cru CLK_GPU>; 769 clock-names = "clk_mali"; 770 power-domains = <&power RK3568_PD_GPU>; 771 #cooling-cells = <2>; 772 operating-points-v2 = <&gpu_opp_table>; 773 774 status = "disabled"; 775 power_model { 776 compatible = "arm,mali-simple-power-model"; 777 static-coefficient = <411000>; 778 dynamic-coefficient = <733>; 779 ts = <32000 4700 (-80) 2>; 780 thermal-zone = "gpu-thermal"; 781 }; 782 }; 783 784 gpu_opp_table: opp-table2 { 785 compatible = "operating-points-v2"; 786 787 opp-200000000 { 788 opp-hz = /bits/ 64 <200000000>; 789 opp-microvolt = <1000000>; 790 }; 791 opp-300000000 { 792 opp-hz = /bits/ 64 <300000000>; 793 opp-microvolt = <1000000>; 794 }; 795 opp-400000000 { 796 opp-hz = /bits/ 64 <400000000>; 797 opp-microvolt = <1000000>; 798 }; 799 opp-600000000 { 800 opp-hz = /bits/ 64 <600000000>; 801 opp-microvolt = <1000000>; 802 }; 803 }; 804 805 pvtm@fde80000 { 806 compatible = "rockchip,rk3568-gpu-pvtm"; 807 reg = <0x0 0xfde80000 0x0 0x100>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 pvtm@1 { 811 reg = <1>; 812 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 813 clock-names = "clk", "pclk"; 814 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 815 reset-names = "rts", "rst-p"; 816 thermal-zone = "gpu-thermal"; 817 }; 818 }; 819 820 pvtm@fde90000 { 821 compatible = "rockchip,rk3568-npu-pvtm"; 822 reg = <0x0 0xfde90000 0x0 0x100>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 pvtm@2 { 826 reg = <2>; 827 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, 828 <&cru HCLK_NPU_PRE>; 829 clock-names = "clk", "pclk", "hclk"; 830 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 831 reset-names = "rts", "rst-p"; 832 thermal-zone = "soc-thermal"; 833 }; 834 }; 835 836 vdpu: vdpu@fdea0400 { 837 compatible = "rockchip,vpu-decoder-v2"; 838 reg = <0x0 0xfdea0400 0x0 0x400>; 839 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "irq_dec"; 841 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 842 clock-names = "aclk_vcodec", "hclk_vcodec"; 843 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 844 reset-names = "video_a", "video_h"; 845 iommus = <&vdpu_mmu>; 846 power-domains = <&power RK3568_PD_VPU>; 847 rockchip,srv = <&mpp_srv>; 848 rockchip,taskqueue-node = <0>; 849 rockchip,resetgroup-node = <0>; 850 status = "disabled"; 851 }; 852 853 vdpu_mmu: iommu@fdea0800 { 854 compatible = "rockchip,iommu-v2"; 855 reg = <0x0 0xfdea0800 0x0 0x40>; 856 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 857 interrupt-names = "vdpu_mmu"; 858 clock-names = "aclk", "iface"; 859 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 860 power-domains = <&power RK3568_PD_VPU>; 861 #iommu-cells = <0>; 862 status = "disabled"; 863 }; 864 865 rk_rga: rk_rga@fdeb0000 { 866 compatible = "rockchip,rga2"; 867 reg = <0x0 0xfdeb0000 0x0 0x1000>; 868 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 870 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 871 power-domains = <&power RK3568_PD_RGA>; 872 status = "disabled"; 873 }; 874 875 ebc: ebc@fdec0000 { 876 compatible = "rockchip,rk3568-ebc-tcon"; 877 reg = <0x0 0xfdec0000 0x0 0x5000>; 878 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; 880 clock-names = "hclk", "dclk"; 881 power-domains = <&power RK3568_PD_RGA>; 882 rockchip,grf = <&grf>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&ebc_pins>; 885 status = "disabled"; 886 }; 887 888 jpegd: jpegd@fded0000 { 889 compatible = "rockchip,rkv-jpeg-decoder-v1"; 890 reg = <0x0 0xfded0000 0x0 0x400>; 891 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 893 clock-names = "aclk_vcodec", "hclk_vcodec"; 894 rockchip,normal-rates = <297000000>, <0>; 895 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; 896 reset-names = "video_a", "video_h"; 897 iommus = <&jpegd_mmu>; 898 rockchip,srv = <&mpp_srv>; 899 rockchip,taskqueue-node = <1>; 900 rockchip,resetgroup-node = <1>; 901 power-domains = <&power RK3568_PD_RGA>; 902 status = "disabled"; 903 }; 904 905 jpegd_mmu: iommu@fded0480 { 906 compatible = "rockchip,iommu-v2"; 907 reg = <0x0 0xfded0480 0x0 0x40>; 908 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "jpegd_mmu"; 910 clock-names = "aclk", "iface"; 911 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 912 power-domains = <&power RK3568_PD_RGA>; 913 #iommu-cells = <0>; 914 status = "disabled"; 915 }; 916 917 vepu: vepu@fdee0000 { 918 compatible = "rockchip,vpu-encoder-v2"; 919 reg = <0x0 0xfdee0000 0x0 0x400>; 920 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 922 clock-names = "aclk_vcodec", "hclk_vcodec"; 923 rockchip,normal-rates = <297000000>, <0>; 924 resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; 925 reset-names = "video_a", "video_h"; 926 iommus = <&vepu_mmu>; 927 rockchip,srv = <&mpp_srv>; 928 rockchip,taskqueue-node = <2>; 929 rockchip,resetgroup-node = <2>; 930 power-domains = <&power RK3568_PD_RGA>; 931 status = "disabled"; 932 }; 933 934 vepu_mmu: iommu@fdee0800 { 935 compatible = "rockchip,iommu-v2"; 936 reg = <0x0 0xfdee0800 0x0 0x40>; 937 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 938 interrupt-names = "vepu_mmu"; 939 clock-names = "aclk", "iface"; 940 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 941 power-domains = <&power RK3568_PD_RGA>; 942 #iommu-cells = <0>; 943 status = "disabled"; 944 }; 945 946 iep: iep@fdef0000 { 947 compatible = "rockchip,iep-v2"; 948 reg = <0x0 0xfdef0000 0x0 0x500>; 949 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; 951 clock-names = "aclk", "hclk", "sclk"; 952 resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, 953 <&cru SRST_IEP_CORE>; 954 reset-names = "rst_a", "rst_h", "rst_s"; 955 power-domains = <&power RK3568_PD_RGA>; 956 rockchip,srv = <&mpp_srv>; 957 rockchip,taskqueue-node = <5>; 958 rockchip,resetgroup-node = <5>; 959 iommus = <&iep_mmu>; 960 status = "disabled"; 961 }; 962 963 iep_mmu: iommu@fdef0800 { 964 compatible = "rockchip,iommu-v2"; 965 reg = <0x0 0xfdef0800 0x0 0x100>; 966 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-names = "iep_mmu"; 968 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 969 clock-names = "aclk", "iface"; 970 #iommu-cells = <0>; 971 power-domains = <&power RK3568_PD_RGA>; 972 //rockchip,disable-device-link-resume; 973 status = "disabled"; 974 }; 975 976 eink: eink@fdf00000 { 977 compatible = "rockchip,rk3568-eink-tcon"; 978 reg = <0x0 0xfdf00000 0x0 0x74>; 979 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; 981 clock-names = "pclk", "hclk"; 982 status = "disabled"; 983 }; 984 985 rkvenc: rkvenc@fdf40000 { 986 compatible = "rockchip,rkv-encoder-v1"; 987 reg = <0x0 0xfdf40000 0x0 0x400>; 988 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 989 interrupt-names = "irq_enc"; 990 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, 991 <&cru CLK_RKVENC_CORE>; 992 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 993 rockchip,normal-rates = <297000000>, <0>, <400000000>; 994 rockchip,advanced-rates = <297000000>, <0>, <500000000>; 995 rockchip,default-max-load = <2088960>; 996 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, 997 <&cru SRST_RKVENC_CORE>; 998 reset-names = "video_a", "video_h", "video_core"; 999 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1000 assigned-clock-rates = <297000000>, <297000000>; 1001 iommus = <&rkvenc_mmu>; 1002 node-name = "rkvenc"; 1003 rockchip,srv = <&mpp_srv>; 1004 rockchip,taskqueue-node = <3>; 1005 rockchip,resetgroup-node = <3>; 1006 power-domains = <&power RK3568_PD_RKVENC>; 1007 status = "disabled"; 1008 }; 1009 1010 rkvenc_mmu: iommu@fdf40f00 { 1011 compatible = "rockchip,iommu-v2"; 1012 reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; 1013 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1015 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1016 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1017 clock-names = "aclk", "iface"; 1018 rockchip,disable-mmu-reset; 1019 rockchip,enable-cmd-retry; 1020 #iommu-cells = <0>; 1021 power-domains = <&power RK3568_PD_RKVENC>; 1022 status = "disabled"; 1023 }; 1024 1025 rkvdec: rkvdec@fdf80200 { 1026 compatible = "rockchip,rkv-decoder-v2"; 1027 reg = <0x0 0xfdf80200 0x0 0x400>; 1028 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1029 interrupt-names = "irq_dec"; 1030 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 1031 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, 1032 <&cru CLK_RKVDEC_HEVC_CA>; 1033 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 1034 "clk_core", "clk_hevc_cabac"; 1035 rockchip,normal-rates = <297000000>, <0>, <297000000>, 1036 <297000000>, <400000000>; 1037 rockchip,advanced-rates = <400000000>, <0>, <400000000>, 1038 <400000000>, <500000000>; 1039 rockchip,default-max-load = <2088960>; 1040 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, 1041 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, 1042 <&cru SRST_RKVDEC_HEVC_CA>; 1043 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, 1044 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 1045 assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; 1046 reset-names = "video_a", "video_h", "video_cabac", 1047 "video_core", "video_hevc_cabac"; 1048 power-domains = <&power RK3568_PD_RKVDEC>; 1049 iommus = <&rkvdec_mmu>; 1050 rockchip,srv = <&mpp_srv>; 1051 rockchip,taskqueue-node = <4>; 1052 rockchip,resetgroup-node = <4>; 1053 status = "disabled"; 1054 }; 1055 1056 rkvdec_mmu: iommu@fdf80800 { 1057 compatible = "rockchip,iommu-v2"; 1058 reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; 1059 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1060 interrupt-names = "rkvdec_mmu"; 1061 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 1062 clock-names = "aclk", "iface"; 1063 power-domains = <&power RK3568_PD_RKVDEC>; 1064 #iommu-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 mipi_csi2: mipi-csi2@fdfb0000 { 1069 compatible = "rockchip,rk3568-mipi-csi2"; 1070 reg = <0x0 0xfdfb0000 0x0 0x10000>; 1071 reg-names = "csihost_regs"; 1072 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1074 interrupt-names = "csi-intr1", "csi-intr2"; 1075 clocks = <&cru PCLK_CSI2HOST1>, <&cru SRST_P_CSI2HOST1>; 1076 clock-names = "pclk_csi2host", "srst_csihost_p"; 1077 power-domains = <&power RK3568_PD_VI>; 1078 status = "disabled"; 1079 }; 1080 1081 rkcif: rkcif@fdfe0000 { 1082 compatible = "rockchip,rk3568-cif"; 1083 reg = <0x0 0xfdfe0000 0x0 0x8000>; 1084 reg-names = "cif_regs"; 1085 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1086 interrupt-names = "cif-intr"; 1087 1088 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 1089 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; 1090 clock-names = "aclk_cif", "hclk_cif", 1091 "dclk_cif", "iclk_cif_g"; 1092 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 1093 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 1094 <&cru SRST_I_VICAP>; 1095 reset-names = "rst_cif_a", "rst_cif_h", 1096 "rst_cif_d", "rst_cif_p", 1097 "rst_cif_i"; 1098 assigned-clocks = <&cru DCLK_VICAP>; 1099 assigned-clock-rates = <300000000>; 1100 power-domains = <&power RK3568_PD_VI>; 1101 rockchip,grf = <&grf>; 1102 iommus = <&rkcif_mmu>; 1103 status = "disabled"; 1104 }; 1105 1106 rkcif_mmu: iommu@fdfe0800 { 1107 compatible = "rockchip,iommu"; 1108 reg = <0x0 0xfdfe0800 0x0 0x100>; 1109 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupt-names = "cif_mmu"; 1111 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 1112 clock-names = "aclk", "iface"; 1113 power-domains = <&power RK3568_PD_VI>; 1114 #iommu-cells = <0>; 1115 rockchip,disable-mmu-reset; 1116 status = "disabled"; 1117 }; 1118 1119 rkcif_dvp: rkcif_dvp { 1120 compatible = "rockchip,rkcif-dvp"; 1121 rockchip,hw = <&rkcif>; 1122 iommus = <&rkcif_mmu>; 1123 status = "disabled"; 1124 }; 1125 1126 rkcif_dvp_sditf: rkcif_dvp_sditf { 1127 compatible = "rockchip,rkcif-sditf"; 1128 rockchip,cif = <&rkcif_dvp>; 1129 status = "disabled"; 1130 }; 1131 1132 rkcif_mipi_lvds: rkcif_mipi_lvds { 1133 compatible = "rockchip,rkcif-mipi-lvds"; 1134 rockchip,hw = <&rkcif>; 1135 iommus = <&rkcif_mmu>; 1136 status = "disabled"; 1137 }; 1138 1139 rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { 1140 compatible = "rockchip,rkcif-sditf"; 1141 rockchip,cif = <&rkcif_mipi_lvds>; 1142 status = "disabled"; 1143 }; 1144 1145 rkisp: rkisp@fdff0000 { 1146 compatible = "rockchip,rk3568-rkisp"; 1147 reg = <0x0 0xfdff0000 0x0 0x10000>; 1148 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1151 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 1152 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; 1153 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1154 resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; 1155 reset-names = "isp", "isp-h"; 1156 rockchip,grf = <&grf>; 1157 power-domains = <&power RK3568_PD_VI>; 1158 iommus = <&rkisp_mmu>; 1159 status = "disabled"; 1160 }; 1161 1162 rkisp_mmu: iommu@fdff1a00 { 1163 compatible = "rockchip,iommu"; 1164 reg = <0x0 0xfdff1a00 0x0 0x100>; 1165 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1166 interrupt-names = "isp_mmu"; 1167 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1168 clock-names = "aclk", "iface"; 1169 power-domains = <&power RK3568_PD_VI>; 1170 #iommu-cells = <0>; 1171 rockchip,disable-mmu-reset; 1172 status = "disabled"; 1173 }; 1174 1175 rkisp_vir0: rkisp-vir0 { 1176 compatible = "rockchip,rkisp-vir"; 1177 rockchip,hw = <&rkisp>; 1178 status = "disabled"; 1179 }; 1180 1181 rkisp_vir1: rkisp-vir1 { 1182 compatible = "rockchip,rkisp-vir"; 1183 rockchip,hw = <&rkisp>; 1184 status = "disabled"; 1185 }; 1186 1187 gmac1: ethernet@fe010000 { 1188 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1189 reg = <0x0 0xfe010000 0x0 0x10000>; 1190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1192 interrupt-names = "macirq", "eth_wake_irq"; 1193 rockchip,grf = <&grf>; 1194 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 1195 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 1196 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 1197 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 1198 clock-names = "stmmaceth", "mac_clk_rx", 1199 "mac_clk_tx", "clk_mac_refout", 1200 "aclk_mac", "pclk_mac", 1201 "clk_mac_speed", "ptp_ref"; 1202 resets = <&cru SRST_A_GMAC1>; 1203 reset-names = "stmmaceth"; 1204 1205 snps,mixed-burst; 1206 snps,tso; 1207 1208 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1209 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1210 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1211 status = "disabled"; 1212 1213 mdio1: mdio { 1214 compatible = "snps,dwmac-mdio"; 1215 #address-cells = <0x1>; 1216 #size-cells = <0x0>; 1217 }; 1218 1219 gmac1_stmmac_axi_setup: stmmac-axi-config { 1220 snps,wr_osr_lmt = <4>; 1221 snps,rd_osr_lmt = <8>; 1222 snps,blen = <0 0 0 0 16 8 4>; 1223 }; 1224 1225 gmac1_mtl_rx_setup: rx-queues-config { 1226 snps,rx-queues-to-use = <1>; 1227 queue0 {}; 1228 }; 1229 1230 gmac1_mtl_tx_setup: tx-queues-config { 1231 snps,tx-queues-to-use = <1>; 1232 queue0 {}; 1233 }; 1234 }; 1235 1236 vop: vop@fe040000 { 1237 compatible = "rockchip,rk3568-vop"; 1238 reg = <0x0 0xfe040000 0x0 0x3000>; 1239 reg-names = "regs"; 1240 rockchip,grf = <&grf>; 1241 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1243 clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 1244 iommus = <&vop_mmu>; 1245 power-domains = <&power RK3568_PD_VO>; 1246 status = "disabled"; 1247 1248 vop_out: ports { 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 1252 port@0 { 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 reg = <0>; 1256 1257 vp0_out_dsi0: endpoint@0 { 1258 reg = <0>; 1259 remote-endpoint = <&dsi0_in_vp0>; 1260 }; 1261 1262 vp0_out_dsi1: endpoint@1 { 1263 reg = <1>; 1264 remote-endpoint = <&dsi1_in_vp0>; 1265 }; 1266 1267 vp0_out_edp: endpoint@2 { 1268 reg = <2>; 1269 remote-endpoint = <&edp_in_vp0>; 1270 }; 1271 1272 vp0_out_hdmi: endpoint@3 { 1273 reg = <3>; 1274 remote-endpoint = <&hdmi_in_vp0>; 1275 }; 1276 }; 1277 1278 port@1 { 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 reg = <1>; 1282 1283 vp1_out_dsi0: endpoint@0 { 1284 reg = <0>; 1285 remote-endpoint = <&dsi0_in_vp1>; 1286 }; 1287 1288 vp1_out_dsi1: endpoint@1 { 1289 reg = <1>; 1290 remote-endpoint = <&dsi1_in_vp1>; 1291 }; 1292 1293 vp1_out_edp: endpoint@2 { 1294 reg = <2>; 1295 remote-endpoint = <&edp_in_vp1>; 1296 }; 1297 1298 vp1_out_hdmi: endpoint@3 { 1299 reg = <3>; 1300 remote-endpoint = <&hdmi_in_vp1>; 1301 }; 1302 1303 vp1_out_lvds0: endpoint@4 { 1304 reg = <4>; 1305 remote-endpoint = <&lvds0_in_vp1>; 1306 }; 1307 1308 vp1_out_lvds1: endpoint@5 { 1309 reg = <5>; 1310 remote-endpoint = <&lvds1_in_vp1>; 1311 }; 1312 1313 }; 1314 1315 port@2 { 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 1319 reg = <2>; 1320 1321 vp2_out_lvds0: endpoint@0 { 1322 reg = <0>; 1323 remote-endpoint = <&lvds0_in_vp2>; 1324 }; 1325 1326 vp2_out_lvds1: endpoint@1 { 1327 reg = <1>; 1328 remote-endpoint = <&lvds1_in_vp2>; 1329 }; 1330 1331 vp2_out_rgb: endpoint@2 { 1332 reg = <2>; 1333 remote-endpoint = <&rgb_in_vp2>; 1334 }; 1335 }; 1336 }; 1337 }; 1338 1339 vop_mmu: iommu@fe043e00 { 1340 compatible = "rockchip,iommu-v2"; 1341 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 1342 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1343 interrupt-names = "vop_mmu"; 1344 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1345 clock-names = "aclk", "iface"; 1346 #iommu-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 dsi0: dsi@fe060000 { 1351 compatible = "rockchip,rk3568-mipi-dsi"; 1352 reg = <0x0 0xfe060000 0x0 0x10000>; 1353 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>; 1355 clock-names = "pclk", "hclk", "hs_clk"; 1356 resets = <&cru SRST_P_DSITX_0>; 1357 reset-names = "apb"; 1358 phys = <&mipi_dphy0>; 1359 phy-names = "mipi_dphy"; 1360 power-domains = <&power RK3568_PD_VO>; 1361 rockchip,grf = <&grf>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 1366 ports { 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 1370 dsi0_in: port@0 { 1371 reg = <0>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 1375 dsi0_in_vp0: endpoint@0 { 1376 reg = <0>; 1377 remote-endpoint = <&vp0_out_dsi0>; 1378 }; 1379 1380 dsi0_in_vp1: endpoint@1 { 1381 reg = <1>; 1382 remote-endpoint = <&vp1_out_dsi0>; 1383 }; 1384 }; 1385 }; 1386 }; 1387 1388 dsi1: dsi@fe070000 { 1389 compatible = "rockchip,rk3568-mipi-dsi"; 1390 reg = <0x0 0xfe070000 0x0 0x10000>; 1391 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>; 1393 clock-names = "pclk", "hclk", "hs_clk"; 1394 resets = <&cru SRST_P_DSITX_1>; 1395 reset-names = "apb"; 1396 phys = <&mipi_dphy1>; 1397 phy-names = "mipi_dphy"; 1398 power-domains = <&power RK3568_PD_VO>; 1399 rockchip,grf = <&grf>; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 1404 ports { 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 1408 dsi1_in: port@0 { 1409 reg = <0>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 1413 dsi1_in_vp0: endpoint@0 { 1414 reg = <0>; 1415 remote-endpoint = <&vp0_out_dsi1>; 1416 }; 1417 1418 dsi1_in_vp1: endpoint@1 { 1419 reg = <1>; 1420 remote-endpoint = <&vp1_out_dsi1>; 1421 }; 1422 }; 1423 }; 1424 }; 1425 1426 hdmi: hdmi@fe0a0000 { 1427 compatible = "rockchip,rk3568-dw-hdmi"; 1428 reg = <0x0 0xfe0a0000 0x0 0x20000>; 1429 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1430 clocks = <&cru PCLK_HDMI_HOST>, 1431 <&cru CLK_HDMI_SFR>, 1432 <&cru CLK_HDMI_CEC>, 1433 <&pmucru PLL_HPLL>, 1434 <&cru HCLK_VOP>; 1435 clock-names = "iahb", "isfr", "cec", "ref", "hclk"; 1436 power-domains = <&power RK3568_PD_VO>; 1437 reg-io-width = <4>; 1438 rockchip,grf = <&grf>; 1439 #sound-dai-cells = <0>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 1442 status = "disabled"; 1443 1444 ports { 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 1448 hdmi_in: port { 1449 reg = <0>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 hdmi_in_vp0: endpoint@0 { 1454 reg = <0>; 1455 remote-endpoint = <&vp0_out_hdmi>; 1456 }; 1457 hdmi_in_vp1: endpoint@1 { 1458 reg = <1>; 1459 remote-endpoint = <&vp1_out_hdmi>; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 edp: edp@fe0c0000 { 1466 compatible = "rockchip,rk3568-edp"; 1467 reg = <0x0 0xfe0c0000 0x0 0x10000>; 1468 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, 1470 <&cru CLK_EDP_200M>, <&cru HCLK_VO>; 1471 clock-names = "dp", "pclk", "spdif", "hclk"; 1472 resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; 1473 reset-names = "dp", "apb"; 1474 phys = <&edp_phy>; 1475 phy-names = "dp"; 1476 power-domains = <&power RK3568_PD_VO>; 1477 status = "disabled"; 1478 1479 ports { 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 1483 edp_in: port@0 { 1484 reg = <0>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 1488 edp_in_vp0: endpoint@0 { 1489 reg = <0>; 1490 remote-endpoint = <&vp0_out_edp>; 1491 }; 1492 1493 edp_in_vp1: endpoint@1 { 1494 reg = <1>; 1495 remote-endpoint = <&vp1_out_edp>; 1496 }; 1497 }; 1498 }; 1499 }; 1500 1501 qos_gpu: qos@fe128000 { 1502 compatible = "syscon"; 1503 reg = <0x0 0xfe128000 0x0 0x20>; 1504 }; 1505 1506 qos_rkvenc_rd_m0: qos@fe138080 { 1507 compatible = "syscon"; 1508 reg = <0x0 0xfe138080 0x0 0x20>; 1509 }; 1510 1511 qos_rkvenc_rd_m1: qos@fe138100 { 1512 compatible = "syscon"; 1513 reg = <0x0 0xfe138100 0x0 0x20>; 1514 }; 1515 1516 qos_rkvenc_wr_m0: qos@fe138180 { 1517 compatible = "syscon"; 1518 reg = <0x0 0xfe138180 0x0 0x20>; 1519 }; 1520 1521 qos_isp: qos@fe148000 { 1522 compatible = "syscon"; 1523 reg = <0x0 0xfe148000 0x0 0x20>; 1524 }; 1525 1526 qos_vicap0: qos@fe148080 { 1527 compatible = "syscon"; 1528 reg = <0x0 0xfe148080 0x0 0x20>; 1529 }; 1530 1531 qos_vicap1: qos@fe148100 { 1532 compatible = "syscon"; 1533 reg = <0x0 0xfe148100 0x0 0x20>; 1534 }; 1535 1536 qos_vpu: qos@fe150000 { 1537 compatible = "syscon"; 1538 reg = <0x0 0xfe150000 0x0 0x20>; 1539 }; 1540 1541 qos_ebc: qos@fe158000 { 1542 compatible = "syscon"; 1543 reg = <0x0 0xfe158000 0x0 0x20>; 1544 }; 1545 1546 qos_iep: qos@fe158100 { 1547 compatible = "syscon"; 1548 reg = <0x0 0xfe158100 0x0 0x20>; 1549 }; 1550 1551 qos_jpeg_dec: qos@fe158180 { 1552 compatible = "syscon"; 1553 reg = <0x0 0xfe158180 0x0 0x20>; 1554 }; 1555 1556 qos_jpeg_enc: qos@fe158200 { 1557 compatible = "syscon"; 1558 reg = <0x0 0xfe158200 0x0 0x20>; 1559 }; 1560 1561 qos_rga_rd: qos@fe158280 { 1562 compatible = "syscon"; 1563 reg = <0x0 0xfe158280 0x0 0x20>; 1564 }; 1565 1566 qos_rga_wr: qos@fe158300 { 1567 compatible = "syscon"; 1568 reg = <0x0 0xfe158300 0x0 0x20>; 1569 }; 1570 1571 qos_npu: qos@fe180000 { 1572 compatible = "syscon"; 1573 reg = <0x0 0xfe180000 0x0 0x20>; 1574 }; 1575 1576 qos_pcie2x1: qos@fe190000 { 1577 compatible = "syscon"; 1578 reg = <0x0 0xfe190000 0x0 0x20>; 1579 }; 1580 1581 qos_pcie3x1: qos@fe190080 { 1582 compatible = "syscon"; 1583 reg = <0x0 0xfe190080 0x0 0x20>; 1584 }; 1585 1586 qos_pcie3x2: qos@fe190100 { 1587 compatible = "syscon"; 1588 reg = <0x0 0xfe190100 0x0 0x20>; 1589 }; 1590 1591 qos_sata0: qos@fe190200 { 1592 compatible = "syscon"; 1593 reg = <0x0 0xfe190200 0x0 0x20>; 1594 }; 1595 1596 qos_sata1: qos@fe190280 { 1597 compatible = "syscon"; 1598 reg = <0x0 0xfe190280 0x0 0x20>; 1599 }; 1600 1601 qos_sata2: qos@fe190300 { 1602 compatible = "syscon"; 1603 reg = <0x0 0xfe190300 0x0 0x20>; 1604 }; 1605 1606 qos_usb3_0: qos@fe190380 { 1607 compatible = "syscon"; 1608 reg = <0x0 0xfe190380 0x0 0x20>; 1609 }; 1610 1611 qos_usb3_1: qos@fe190400 { 1612 compatible = "syscon"; 1613 reg = <0x0 0xfe190400 0x0 0x20>; 1614 }; 1615 1616 qos_rkvdec: qos@fe198000 { 1617 compatible = "syscon"; 1618 reg = <0x0 0xfe198000 0x0 0x20>; 1619 }; 1620 1621 qos_hdcp: qos@fe1a8000 { 1622 compatible = "syscon"; 1623 reg = <0x0 0xfe1a8000 0x0 0x20>; 1624 }; 1625 1626 qos_vop_m0: qos@fe1a8080 { 1627 compatible = "syscon"; 1628 reg = <0x0 0xfe1a8080 0x0 0x20>; 1629 }; 1630 1631 qos_vop_m1: qos@fe1a8100 { 1632 compatible = "syscon"; 1633 reg = <0x0 0xfe1a8100 0x0 0x20>; 1634 }; 1635 1636 sdmmc2: dwmmc@fe000000 { 1637 compatible = "rockchip,rk3568-dw-mshc", 1638 "rockchip,rk3288-dw-mshc"; 1639 reg = <0x0 0xfe000000 0x0 0x4000>; 1640 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1641 max-frequency = <150000000>; 1642 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 1643 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 1644 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1645 fifo-depth = <0x100>; 1646 resets = <&cru SRST_SDMMC2>; 1647 reset-names = "reset"; 1648 status = "disabled"; 1649 }; 1650 1651 pcie2x1: pcie@fe260000 { 1652 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1653 #address-cells = <3>; 1654 #size-cells = <2>; 1655 bus-range = <0x0 0x1f>; 1656 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1657 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>; 1658 clock-names = "aclk_mst", "aclk_slv", 1659 "aclk_dbi", "pclk"; 1660 device_type = "pci"; 1661 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1666 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1667 linux,pci-domain = <0>; 1668 num-ib-windows = <6>; 1669 num-ob-windows = <2>; 1670 max-link-speed = <2>; 1671 msi-map = <0x0 &its 0x0 0x1000>; 1672 num-lanes = <1>; 1673 phys = <&combphy2_psq PHY_TYPE_PCIE>; 1674 phy-names = "pcie-phy"; 1675 power-domains = <&power RK3568_PD_PIPE>; 1676 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 1677 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 1678 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000 1679 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 1680 reg = <0x3 0xc0000000 0x0 0x400000>, 1681 <0x0 0xfe260000 0x0 0x10000>; 1682 reg-names = "pcie-dbi", "pcie-apb"; 1683 resets = <&cru SRST_PCIE20_POWERUP>; 1684 reset-names = "pipe"; 1685 status = "disabled"; 1686 }; 1687 1688 pcie3x1: pcie@fe270000 { 1689 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1690 #address-cells = <3>; 1691 #size-cells = <2>; 1692 bus-range = <0x0 0x1f>; 1693 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 1694 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>; 1695 clock-names = "aclk_mst", "aclk_slv", 1696 "aclk_dbi", "pclk"; 1697 device_type = "pci"; 1698 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1703 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1704 linux,pci-domain = <1>; 1705 num-ib-windows = <6>; 1706 num-ob-windows = <2>; 1707 max-link-speed = <3>; 1708 msi-map = <0x0 &its 0x3000 0x1000>; 1709 num-lanes = <1>; 1710 phys = <&pcie30phy>; 1711 phy-names = "pcie-phy"; 1712 power-domains = <&power RK3568_PD_PIPE>; 1713 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 1714 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 1715 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000 1716 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; 1717 reg = <0x3 0xc0400000 0x0 0x400000>, 1718 <0x0 0xfe270000 0x0 0x10000>; 1719 reg-names = "pcie-dbi", "pcie-apb"; 1720 resets = <&cru SRST_PCIE30X1_POWERUP>; 1721 reset-names = "pipe"; 1722 /* rockchip,bifurcation; lane1 when using 1+1 */ 1723 status = "disabled"; 1724 }; 1725 1726 pcie3x2: pcie@fe280000 { 1727 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 1728 #address-cells = <3>; 1729 #size-cells = <2>; 1730 bus-range = <0x0 0x1f>; 1731 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 1732 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>; 1733 clock-names = "aclk_mst", "aclk_slv", 1734 "aclk_dbi", "pclk"; 1735 device_type = "pci"; 1736 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1741 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1742 linux,pci-domain = <2>; 1743 num-ib-windows = <6>; 1744 num-ob-windows = <2>; 1745 max-link-speed = <3>; 1746 msi-map = <0x0 &its 0x2000 0x1000>; 1747 num-lanes = <2>; 1748 phys = <&pcie30phy>; 1749 phy-names = "pcie-phy"; 1750 power-domains = <&power RK3568_PD_PIPE>; 1751 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 1752 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 1753 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000 1754 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; 1755 reg = <0x3 0xc0800000 0x0 0x400000>, 1756 <0x0 0xfe280000 0x0 0x10000>; 1757 reg-names = "pcie-dbi", "pcie-apb"; 1758 resets = <&cru SRST_PCIE30X2_POWERUP>; 1759 reset-names = "pipe"; 1760 /* rockchip,bifurcation; lane0 when using 1+1 */ 1761 status = "disabled"; 1762 }; 1763 1764 gmac0: ethernet@fe2a0000 { 1765 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1766 reg = <0x0 0xfe2a0000 0x0 0x10000>; 1767 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1769 interrupt-names = "macirq", "eth_wake_irq"; 1770 rockchip,grf = <&grf>; 1771 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, 1772 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, 1773 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, 1774 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; 1775 clock-names = "stmmaceth", "mac_clk_rx", 1776 "mac_clk_tx", "clk_mac_refout", 1777 "aclk_mac", "pclk_mac", 1778 "clk_mac_speed", "ptp_ref"; 1779 resets = <&cru SRST_A_GMAC0>; 1780 reset-names = "stmmaceth"; 1781 1782 snps,mixed-burst; 1783 snps,tso; 1784 1785 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1786 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1787 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1788 status = "disabled"; 1789 1790 mdio0: mdio { 1791 compatible = "snps,dwmac-mdio"; 1792 #address-cells = <0x1>; 1793 #size-cells = <0x0>; 1794 }; 1795 1796 gmac0_stmmac_axi_setup: stmmac-axi-config { 1797 snps,wr_osr_lmt = <4>; 1798 snps,rd_osr_lmt = <8>; 1799 snps,blen = <0 0 0 0 16 8 4>; 1800 }; 1801 1802 gmac0_mtl_rx_setup: rx-queues-config { 1803 snps,rx-queues-to-use = <1>; 1804 queue0 {}; 1805 }; 1806 1807 gmac0_mtl_tx_setup: tx-queues-config { 1808 snps,tx-queues-to-use = <1>; 1809 queue0 {}; 1810 }; 1811 }; 1812 1813 sdmmc0: dwmmc@fe2b0000 { 1814 compatible = "rockchip,rk3568-dw-mshc", 1815 "rockchip,rk3288-dw-mshc"; 1816 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1817 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1818 max-frequency = <150000000>; 1819 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1820 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1821 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1822 fifo-depth = <0x100>; 1823 resets = <&cru SRST_SDMMC0>; 1824 reset-names = "reset"; 1825 pinctrl-names = "default"; 1826 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1827 status = "disabled"; 1828 }; 1829 1830 sdmmc1: dwmmc@fe2c0000 { 1831 compatible = "rockchip,rk3568-dw-mshc", 1832 "rockchip,rk3288-dw-mshc"; 1833 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1834 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1835 max-frequency = <150000000>; 1836 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1837 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1838 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1839 fifo-depth = <0x100>; 1840 resets = <&cru SRST_SDMMC1>; 1841 reset-names = "reset"; 1842 status = "disabled"; 1843 }; 1844 1845 sfc: sfc@fe300000 { 1846 compatible = "rockchip,sfc"; 1847 reg = <0x0 0xfe300000 0x0 0x4000>; 1848 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1849 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1850 clock-names = "clk_sfc", "hclk_sfc"; 1851 assigned-clocks = <&cru SCLK_SFC>; 1852 assigned-clock-rates = <100000000>; 1853 status = "disabled"; 1854 }; 1855 1856 sdhci: sdhci@fe310000 { 1857 compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; 1858 reg = <0x0 0xfe310000 0x0 0x10000>; 1859 max-frequency = <200000000>; 1860 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1861 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1862 assigned-clock-rates = <200000000>, <24000000>; 1863 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1864 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1865 <&cru TCLK_EMMC>; 1866 clock-names = "core", "bus", "axi", "block", "timer"; 1867 status = "disabled"; 1868 }; 1869 1870 nandc0: nandc@fe330000 { 1871 compatible = "rockchip,rk-nandc"; 1872 reg = <0x0 0xfe330000 0x0 0x4000>; 1873 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1874 nandc_id = <0>; 1875 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; 1876 clock-names = "clk_nandc", "hclk_nandc"; 1877 status = "disabled"; 1878 }; 1879 1880 crypto: crypto@fe380000 { 1881 compatible = "rockchip,rk3568-crypto"; 1882 reg = <0x0 0xfe380000 0x0 0x4000>; 1883 clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; 1884 clock-names = "sclk_crypto", "apkclk_crypto"; 1885 clock-frequency = <150000000>, <300000000>; 1886 status = "disabled"; 1887 }; 1888 1889 rng: rng@fe388000 { 1890 compatible = "rockchip,cryptov2-rng"; 1891 reg = <0x0 0xfe388000 0x0 0x2000>; 1892 status = "disabled"; 1893 }; 1894 1895 otp: otp@fe38c000 { 1896 compatible = "rockchip,rk3568-otp"; 1897 reg = <0x0 0xfe38c000 0x0 0x4000>; 1898 #address-cells = <1>; 1899 #size-cells = <1>; 1900 clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>, 1901 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; 1902 clock-names = "usr", "sbpi", "apb", "phy"; 1903 resets = <&cru SRST_OTPPHY>; 1904 reset-names = "otp_phy"; 1905 1906 /* Data cells */ 1907 cpu_code: cpu-code@2 { 1908 reg = <0x02 0x2>; 1909 }; 1910 otp_cpu_version: cpu-version@8 { 1911 reg = <0x08 0x1>; 1912 bits = <3 3>; 1913 }; 1914 mbist_vmin: mbist-vmin@9 { 1915 reg = <0x09 0x1>; 1916 bits = <0 4>; 1917 }; 1918 otp_id: id@a { 1919 reg = <0x0a 0x10>; 1920 }; 1921 cpu_leakage: cpu-leakage@1a { 1922 reg = <0x1a 0x1>; 1923 }; 1924 log_leakage: log-leakage@1b { 1925 reg = <0x1b 0x1>; 1926 }; 1927 npu_leakage: npu-leakage@1c { 1928 reg = <0x1c 0x1>; 1929 }; 1930 gpu_leakage: gpu-leakage@1d { 1931 reg = <0x1d 0x1>; 1932 }; 1933 core_pvtm:core-pvtm@2a { 1934 reg = <0x2a 0x2>; 1935 }; 1936 cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { 1937 reg = <0x2e 0x1>; 1938 }; 1939 cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { 1940 reg = <0x2f 0x1>; 1941 bits = <0 4>; 1942 }; 1943 gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { 1944 reg = <0x30 0x1>; 1945 }; 1946 gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { 1947 reg = <0x31 0x1>; 1948 bits = <0 4>; 1949 }; 1950 tsadc_trim_base_frac: tsadc-trim-base-frac@31 { 1951 reg = <0x31 0x1>; 1952 bits = <4 4>; 1953 }; 1954 tsadc_trim_base: tsadc-trim-base@32 { 1955 reg = <0x32 0x1>; 1956 }; 1957 cpu_opp_info: cpu-opp-info@36 { 1958 reg = <0x36 0x6>; 1959 }; 1960 gpu_opp_info: gpu-opp-info@3c { 1961 reg = <0x3c 0x6>; 1962 }; 1963 npu_opp_info: npu-opp-info@42 { 1964 reg = <0x42 0x6>; 1965 }; 1966 dmc_opp_info: dmc-opp-info@48 { 1967 reg = <0x48 0x6>; 1968 }; 1969 }; 1970 1971 i2s0_8ch: i2s@fe400000 { 1972 compatible = "rockchip,rk3568-i2s-tdm"; 1973 reg = <0x0 0xfe400000 0x0 0x1000>; 1974 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1975 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1976 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1977 dmas = <&dmac1 0>; 1978 dma-names = "tx"; 1979 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1980 reset-names = "tx-m", "rx-m"; 1981 rockchip,cru = <&cru>; 1982 rockchip,grf = <&grf>; 1983 rockchip,playback-only; 1984 #sound-dai-cells = <0>; 1985 status = "disabled"; 1986 }; 1987 1988 i2s1_8ch: i2s@fe410000 { 1989 compatible = "rockchip,rk3568-i2s-tdm"; 1990 reg = <0x0 0xfe410000 0x0 0x1000>; 1991 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1992 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1993 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1994 dmas = <&dmac1 2>, <&dmac1 3>; 1995 dma-names = "tx", "rx"; 1996 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1997 reset-names = "tx-m", "rx-m"; 1998 rockchip,cru = <&cru>; 1999 rockchip,grf = <&grf>; 2000 #sound-dai-cells = <0>; 2001 pinctrl-names = "default"; 2002 pinctrl-0 = <&i2s1sclktxm0 2003 &i2s1sclkrxm0 2004 &i2s1lrcktxm0 2005 &i2s1lrckrxm0 2006 &i2s1sdi0m0 2007 &i2s1sdi1m0 2008 &i2s1sdi2m0 2009 &i2s1sdi3m0 2010 &i2s1sdo0m0 2011 &i2s1sdo1m0 2012 &i2s1sdo2m0 2013 &i2s1sdo3m0>; 2014 status = "disabled"; 2015 }; 2016 2017 i2s2_2ch: i2s@fe420000 { 2018 compatible = "rockchip,rk3568-i2s-tdm"; 2019 reg = <0x0 0xfe420000 0x0 0x1000>; 2020 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 2021 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2022 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2023 dmas = <&dmac1 4>, <&dmac1 5>; 2024 dma-names = "tx", "rx"; 2025 rockchip,cru = <&cru>; 2026 rockchip,grf = <&grf>; 2027 rockchip,clk-trcm = <1>; 2028 #sound-dai-cells = <0>; 2029 pinctrl-names = "default"; 2030 pinctrl-0 = <&i2s2sclktxm0 2031 &i2s2lrcktxm0 2032 &i2s2sdim0 2033 &i2s2sdom0>; 2034 status = "disabled"; 2035 }; 2036 2037 i2s3_2ch: i2s@fe430000 { 2038 compatible = "rockchip,rk3568-i2s-tdm"; 2039 reg = <0x0 0xfe430000 0x0 0x1000>; 2040 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 2041 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; 2042 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2043 dmas = <&dmac1 6>, <&dmac1 7>; 2044 dma-names = "tx", "rx"; 2045 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 2046 reset-names = "tx-m", "rx-m"; 2047 rockchip,cru = <&cru>; 2048 rockchip,grf = <&grf>; 2049 #sound-dai-cells = <0>; 2050 pinctrl-names = "default"; 2051 pinctrl-0 = <&i2s3sclkm0 2052 &i2s3lrckm0 2053 &i2s3sdim0 2054 &i2s3sdom0>; 2055 status = "disabled"; 2056 }; 2057 2058 pdm: pdm@fe440000 { 2059 compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; 2060 reg = <0x0 0xfe440000 0x0 0x1000>; 2061 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 2062 clock-names = "pdm_clk", "pdm_hclk"; 2063 dmas = <&dmac1 9>; 2064 dma-names = "rx"; 2065 #sound-dai-cells = <0>; 2066 status = "disabled"; 2067 }; 2068 2069 vad: vad@fe450000 { 2070 compatible = "rockchip,rk3568-vad"; 2071 reg = <0x0 0xfe450000 0x0 0x10000>; 2072 reg-names = "vad"; 2073 clocks = <&cru HCLK_VAD>; 2074 clock-names = "hclk"; 2075 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2076 rockchip,audio-src = <0>; 2077 rockchip,det-channel = <0>; 2078 rockchip,mode = <0>; 2079 #sound-dai-cells = <0>; 2080 status = "disabled"; 2081 }; 2082 2083 spdif_8ch: spdif@fe460000 { 2084 compatible = "rockchip,rk3568-spdif"; 2085 reg = <0x0 0xfe460000 0x0 0x1000>; 2086 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2087 dmas = <&dmac1 1>; 2088 dma-names = "tx"; 2089 clock-names = "mclk", "hclk"; 2090 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 2091 #sound-dai-cells = <0>; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&spdifm0_pins>; 2094 status = "disabled"; 2095 }; 2096 2097 audpwm: audpwm@fe470000 { 2098 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; 2099 reg = <0x0 0xfe470000 0x0 0x1000>; 2100 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 2101 clock-names = "clk", "hclk"; 2102 dmas = <&dmac1 8>; 2103 dma-names = "tx"; 2104 #sound-dai-cells = <0>; 2105 rockchip,sample-width-bits = <11>; 2106 rockchip,interpolat-points = <1>; 2107 status = "disabled"; 2108 }; 2109 2110 dig_acodec: codec-digital@fe478000 { 2111 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; 2112 reg = <0x0 0xfe478000 0x0 0x1000>; 2113 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, 2114 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; 2115 clock-names = "adc", "dac", "i2c", "pclk"; 2116 pinctrl-names = "default"; 2117 pinctrl-0 = <&acodec_pins>; 2118 resets = <&cru SRST_ACDCDIG>; 2119 reset-names = "reset" ; 2120 rockchip,grf = <&grf>; 2121 #sound-dai-cells = <0>; 2122 status = "disabled"; 2123 }; 2124 2125 dmac0: dmac@fe530000 { 2126 compatible = "arm,pl330", "arm,primecell"; 2127 reg = <0x0 0xfe530000 0x0 0x4000>; 2128 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2130 clocks = <&cru ACLK_BUS>; 2131 clock-names = "apb_pclk"; 2132 #dma-cells = <1>; 2133 arm,pl330-periph-burst; 2134 }; 2135 2136 dmac1: dmac@fe550000 { 2137 compatible = "arm,pl330", "arm,primecell"; 2138 reg = <0x0 0xfe550000 0x0 0x4000>; 2139 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 2141 clocks = <&cru ACLK_BUS>; 2142 clock-names = "apb_pclk"; 2143 #dma-cells = <1>; 2144 arm,pl330-periph-burst; 2145 }; 2146 2147 can0: can@fe570000 { 2148 compatible = "rockchip,canfd-1.0"; 2149 reg = <0x0 0xfe570000 0x0 0x1000>; 2150 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 2151 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 2152 clock-names = "baudclk", "apb_pclk"; 2153 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 2154 reset-names = "can", "can-apb"; 2155 tx-fifo-depth = <1>; 2156 rx-fifo-depth = <6>; 2157 status = "disabled"; 2158 }; 2159 2160 can1: can@fe580000 { 2161 compatible = "rockchip,canfd-1.0"; 2162 reg = <0x0 0xfe580000 0x0 0x1000>; 2163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 2164 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 2165 clock-names = "baudclk", "apb_pclk"; 2166 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 2167 reset-names = "can", "can-apb"; 2168 tx-fifo-depth = <1>; 2169 rx-fifo-depth = <6>; 2170 status = "disabled"; 2171 }; 2172 2173 can2: can@fe590000 { 2174 compatible = "rockchip,canfd-1.0"; 2175 reg = <0x0 0xfe590000 0x0 0x1000>; 2176 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2177 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 2178 clock-names = "baudclk", "apb_pclk"; 2179 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 2180 reset-names = "can", "can-apb"; 2181 tx-fifo-depth = <1>; 2182 rx-fifo-depth = <6>; 2183 status = "disabled"; 2184 }; 2185 2186 i2c1: i2c@fe5a0000 { 2187 compatible = "rockchip,rk3399-i2c"; 2188 reg = <0x0 0xfe5a0000 0x0 0x1000>; 2189 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2190 clock-names = "i2c", "pclk"; 2191 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2192 pinctrl-names = "default"; 2193 pinctrl-0 = <&i2c1_xfer>; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 status = "disabled"; 2197 }; 2198 2199 i2c2: i2c@fe5b0000 { 2200 compatible = "rockchip,rk3399-i2c"; 2201 reg = <0x0 0xfe5b0000 0x0 0x1000>; 2202 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2203 clock-names = "i2c", "pclk"; 2204 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 2205 pinctrl-names = "default"; 2206 pinctrl-0 = <&i2c2m0_xfer>; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 status = "disabled"; 2210 }; 2211 2212 i2c3: i2c@fe5c0000 { 2213 compatible = "rockchip,rk3399-i2c"; 2214 reg = <0x0 0xfe5c0000 0x0 0x1000>; 2215 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2216 clock-names = "i2c", "pclk"; 2217 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2218 pinctrl-names = "default"; 2219 pinctrl-0 = <&i2c3m0_xfer>; 2220 #address-cells = <1>; 2221 #size-cells = <0>; 2222 status = "disabled"; 2223 }; 2224 2225 i2c4: i2c@fe5d0000 { 2226 compatible = "rockchip,rk3399-i2c"; 2227 reg = <0x0 0xfe5d0000 0x0 0x1000>; 2228 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2229 clock-names = "i2c", "pclk"; 2230 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 2231 pinctrl-names = "default"; 2232 pinctrl-0 = <&i2c4m0_xfer>; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 status = "disabled"; 2236 }; 2237 2238 i2c5: i2c@fe5e0000 { 2239 compatible = "rockchip,rk3399-i2c"; 2240 reg = <0x0 0xfe5e0000 0x0 0x1000>; 2241 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2242 clock-names = "i2c", "pclk"; 2243 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2244 pinctrl-names = "default"; 2245 pinctrl-0 = <&i2c5m0_xfer>; 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 status = "disabled"; 2249 }; 2250 2251 wdt: watchdog@fe600000 { 2252 compatible = "snps,dw-wdt"; 2253 reg = <0x0 0xfe600000 0x0 0x100>; 2254 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 2255 clock-names = "tclk", "pclk"; 2256 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2257 resets = <&cru SRST_T_WDT_NS>; 2258 reset-names = "reset"; 2259 status = "okay"; 2260 }; 2261 2262 spi0: spi@fe610000 { 2263 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2264 reg = <0x0 0xfe610000 0x0 0x1000>; 2265 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2269 clock-names = "spiclk", "apb_pclk"; 2270 dmas = <&dmac0 20>, <&dmac0 21>; 2271 dma-names = "tx", "rx"; 2272 pinctrl-names = "default", "high_speed"; 2273 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; 2274 pinctrl-1 = <&spi0clkm0_hs &spi0cs0m0 &spi0cs1m0 &spi0misom0_hs &spi0mosim0_hs>; 2275 status = "disabled"; 2276 }; 2277 2278 spi1: spi@fe620000 { 2279 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2280 reg = <0x0 0xfe620000 0x0 0x1000>; 2281 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2285 clock-names = "spiclk", "apb_pclk"; 2286 dmas = <&dmac0 22>, <&dmac0 23>; 2287 dma-names = "tx", "rx"; 2288 pinctrl-names = "default", "high_speed"; 2289 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; 2290 pinctrl-1 = <&spi1clkm0_hs &spi1cs0m0 &spi1cs1m0 &spi1misom0_hs &spi1mosim0_hs>; 2291 status = "disabled"; 2292 }; 2293 2294 spi2: spi@fe630000 { 2295 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2296 reg = <0x0 0xfe630000 0x0 0x1000>; 2297 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2301 clock-names = "spiclk", "apb_pclk"; 2302 dmas = <&dmac0 24>, <&dmac0 25>; 2303 dma-names = "tx", "rx"; 2304 pinctrl-names = "default", "high_speed"; 2305 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; 2306 pinctrl-1 = <&spi2clkm0_hs &spi2cs0m0 &spi2cs1m0 &spi2misom0_hs &spi2mosim0_hs>; 2307 status = "disabled"; 2308 }; 2309 2310 spi3: spi@fe640000 { 2311 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 2312 reg = <0x0 0xfe640000 0x0 0x1000>; 2313 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2314 #address-cells = <1>; 2315 #size-cells = <0>; 2316 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2317 clock-names = "spiclk", "apb_pclk"; 2318 dmas = <&dmac0 26>, <&dmac0 27>; 2319 dma-names = "tx", "rx"; 2320 pinctrl-names = "default", "high_speed"; 2321 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; 2322 pinctrl-1 = <&spi3clkm0_hs &spi3cs0m0 &spi3cs1m0 &spi3misom0_hs &spi3mosim0_hs>; 2323 status = "disabled"; 2324 }; 2325 2326 uart1: serial@fe650000 { 2327 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2328 reg = <0x0 0xfe650000 0x0 0x100>; 2329 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2330 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2331 clock-names = "baudclk", "apb_pclk"; 2332 reg-shift = <2>; 2333 reg-io-width = <4>; 2334 dmas = <&dmac0 2>, <&dmac0 3>; 2335 pinctrl-names = "default"; 2336 pinctrl-0 = <&uart1m0_xfer>; 2337 status = "disabled"; 2338 }; 2339 2340 uart2: serial@fe660000 { 2341 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2342 reg = <0x0 0xfe660000 0x0 0x100>; 2343 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2344 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2345 clock-names = "baudclk", "apb_pclk"; 2346 reg-shift = <2>; 2347 reg-io-width = <4>; 2348 dmas = <&dmac0 4>, <&dmac0 5>; 2349 pinctrl-names = "default"; 2350 pinctrl-0 = <&uart2m0_xfer>; 2351 status = "disabled"; 2352 }; 2353 2354 uart3: serial@fe670000 { 2355 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2356 reg = <0x0 0xfe670000 0x0 0x100>; 2357 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2358 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2359 clock-names = "baudclk", "apb_pclk"; 2360 reg-shift = <2>; 2361 reg-io-width = <4>; 2362 dmas = <&dmac0 6>, <&dmac0 7>; 2363 pinctrl-names = "default"; 2364 pinctrl-0 = <&uart3m0_xfer>; 2365 status = "disabled"; 2366 }; 2367 2368 uart4: serial@fe680000 { 2369 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2370 reg = <0x0 0xfe680000 0x0 0x100>; 2371 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2373 clock-names = "baudclk", "apb_pclk"; 2374 reg-shift = <2>; 2375 reg-io-width = <4>; 2376 dmas = <&dmac0 8>, <&dmac0 9>; 2377 pinctrl-names = "default"; 2378 pinctrl-0 = <&uart4m0_xfer>; 2379 status = "disabled"; 2380 }; 2381 2382 uart5: serial@fe690000 { 2383 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2384 reg = <0x0 0xfe690000 0x0 0x100>; 2385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 2386 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2387 clock-names = "baudclk", "apb_pclk"; 2388 reg-shift = <2>; 2389 reg-io-width = <4>; 2390 dmas = <&dmac0 10>, <&dmac0 11>; 2391 pinctrl-names = "default"; 2392 pinctrl-0 = <&uart5m0_xfer>; 2393 status = "disabled"; 2394 }; 2395 2396 uart6: serial@fe6a0000 { 2397 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2398 reg = <0x0 0xfe6a0000 0x0 0x100>; 2399 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 2400 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2401 clock-names = "baudclk", "apb_pclk"; 2402 reg-shift = <2>; 2403 reg-io-width = <4>; 2404 dmas = <&dmac0 12>, <&dmac0 13>; 2405 pinctrl-names = "default"; 2406 pinctrl-0 = <&uart6m0_xfer>; 2407 status = "disabled"; 2408 }; 2409 2410 uart7: serial@fe6b0000 { 2411 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2412 reg = <0x0 0xfe6b0000 0x0 0x100>; 2413 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2414 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2415 clock-names = "baudclk", "apb_pclk"; 2416 reg-shift = <2>; 2417 reg-io-width = <4>; 2418 dmas = <&dmac0 14>, <&dmac0 15>; 2419 pinctrl-names = "default"; 2420 pinctrl-0 = <&uart7m0_xfer>; 2421 status = "disabled"; 2422 }; 2423 2424 uart8: serial@fe6c0000 { 2425 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2426 reg = <0x0 0xfe6c0000 0x0 0x100>; 2427 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2428 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2429 clock-names = "baudclk", "apb_pclk"; 2430 reg-shift = <2>; 2431 reg-io-width = <4>; 2432 dmas = <&dmac0 16>, <&dmac0 17>; 2433 pinctrl-names = "default"; 2434 pinctrl-0 = <&uart8m0_xfer>; 2435 status = "disabled"; 2436 }; 2437 2438 uart9: serial@fe6d0000 { 2439 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2440 reg = <0x0 0xfe6d0000 0x0 0x100>; 2441 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2442 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2443 clock-names = "baudclk", "apb_pclk"; 2444 reg-shift = <2>; 2445 reg-io-width = <4>; 2446 dmas = <&dmac0 18>, <&dmac0 19>; 2447 pinctrl-names = "default"; 2448 pinctrl-0 = <&uart9m0_xfer>; 2449 status = "disabled"; 2450 }; 2451 2452 pwm4: pwm@fe6e0000 { 2453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2454 reg = <0x0 0xfe6e0000 0x0 0x10>; 2455 #pwm-cells = <3>; 2456 pinctrl-names = "active"; 2457 pinctrl-0 = <&pwm4_pins>; 2458 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2459 clock-names = "pwm", "pclk"; 2460 status = "disabled"; 2461 }; 2462 2463 pwm5: pwm@fe6e0010 { 2464 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2465 reg = <0x0 0xfe6e0010 0x0 0x10>; 2466 #pwm-cells = <3>; 2467 pinctrl-names = "active"; 2468 pinctrl-0 = <&pwm5_pins>; 2469 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2470 clock-names = "pwm", "pclk"; 2471 status = "disabled"; 2472 }; 2473 2474 pwm6: pwm@fe6e0020 { 2475 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2476 reg = <0x0 0xfe6e0020 0x0 0x10>; 2477 #pwm-cells = <3>; 2478 pinctrl-names = "active"; 2479 pinctrl-0 = <&pwm6_pins>; 2480 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2481 clock-names = "pwm", "pclk"; 2482 status = "disabled"; 2483 }; 2484 2485 pwm7: pwm@fe6e0030 { 2486 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2487 reg = <0x0 0xfe6e0030 0x0 0x10>; 2488 #pwm-cells = <3>; 2489 pinctrl-names = "active"; 2490 pinctrl-0 = <&pwm7_pins>; 2491 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2492 clock-names = "pwm", "pclk"; 2493 status = "disabled"; 2494 }; 2495 2496 pwm8: pwm@fe6f0000 { 2497 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2498 reg = <0x0 0xfe6f0000 0x0 0x10>; 2499 #pwm-cells = <3>; 2500 pinctrl-names = "active"; 2501 pinctrl-0 = <&pwm8m0_pins>; 2502 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2503 clock-names = "pwm", "pclk"; 2504 status = "disabled"; 2505 }; 2506 2507 pwm9: pwm@fe6f0010 { 2508 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2509 reg = <0x0 0xfe6f0010 0x0 0x10>; 2510 #pwm-cells = <3>; 2511 pinctrl-names = "active"; 2512 pinctrl-0 = <&pwm9m0_pins>; 2513 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2514 clock-names = "pwm", "pclk"; 2515 status = "disabled"; 2516 }; 2517 2518 pwm10: pwm@fe6f0020 { 2519 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2520 reg = <0x0 0xfe6f0020 0x0 0x10>; 2521 #pwm-cells = <3>; 2522 pinctrl-names = "active"; 2523 pinctrl-0 = <&pwm10m0_pins>; 2524 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2525 clock-names = "pwm", "pclk"; 2526 status = "disabled"; 2527 }; 2528 2529 pwm11: pwm@fe6f0030 { 2530 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2531 reg = <0x0 0xfe6f0030 0x0 0x10>; 2532 #pwm-cells = <3>; 2533 pinctrl-names = "active"; 2534 pinctrl-0 = <&pwm11m0_pins>; 2535 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2536 clock-names = "pwm", "pclk"; 2537 status = "disabled"; 2538 }; 2539 2540 pwm12: pwm@fe700000 { 2541 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2542 reg = <0x0 0xfe700000 0x0 0x10>; 2543 #pwm-cells = <3>; 2544 pinctrl-names = "active"; 2545 pinctrl-0 = <&pwm12m0_pins>; 2546 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2547 clock-names = "pwm", "pclk"; 2548 status = "disabled"; 2549 }; 2550 2551 pwm13: pwm@fe700010 { 2552 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2553 reg = <0x0 0xfe700010 0x0 0x10>; 2554 #pwm-cells = <3>; 2555 pinctrl-names = "active"; 2556 pinctrl-0 = <&pwm13m0_pins>; 2557 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2558 clock-names = "pwm", "pclk"; 2559 status = "disabled"; 2560 }; 2561 2562 pwm14: pwm@fe700020 { 2563 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2564 reg = <0x0 0xfe700020 0x0 0x10>; 2565 #pwm-cells = <3>; 2566 pinctrl-names = "active"; 2567 pinctrl-0 = <&pwm14m0_pins>; 2568 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2569 clock-names = "pwm", "pclk"; 2570 status = "disabled"; 2571 }; 2572 2573 pwm15: pwm@fe700030 { 2574 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 2575 reg = <0x0 0xfe700030 0x0 0x10>; 2576 #pwm-cells = <3>; 2577 pinctrl-names = "active"; 2578 pinctrl-0 = <&pwm15m0_pins>; 2579 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2580 clock-names = "pwm", "pclk"; 2581 status = "disabled"; 2582 }; 2583 2584 tsadc: tsadc@fe710000 { 2585 compatible = "rockchip,rk3568-tsadc"; 2586 reg = <0x0 0xfe710000 0x0 0x100>; 2587 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2588 rockchip,grf = <&grf>; 2589 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2590 clock-names = "tsadc", "apb_pclk"; 2591 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 2592 assigned-clock-rates = <17000000>, <700000>; 2593 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, 2594 <&cru SRST_TSADCPHY>; 2595 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 2596 #thermal-sensor-cells = <1>; 2597 rockchip,hw-tshut-temp = <120000>; 2598 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2599 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2600 pinctrl-names = "gpio", "otpout"; 2601 pinctrl-0 = <&tsadc_gpio>; 2602 pinctrl-1 = <&tsadc_shutorg>; 2603 status = "disabled"; 2604 }; 2605 2606 saradc: saradc@fe720000 { 2607 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 2608 reg = <0x0 0xfe720000 0x0 0x100>; 2609 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2610 #io-channel-cells = <1>; 2611 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2612 clock-names = "saradc", "apb_pclk"; 2613 resets = <&cru SRST_P_SARADC>; 2614 reset-names = "saradc-apb"; 2615 status = "disabled"; 2616 }; 2617 2618 mailbox: mailbox@fe780000 { 2619 compatible = "rockchip,rk3568-mailbox", 2620 "rockchip,rk3368-mailbox"; 2621 reg = <0x0 0xfe780000 0x0 0x1000>; 2622 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2626 clocks = <&cru PCLK_MAILBOX>; 2627 clock-names = "pclk_mailbox"; 2628 #mbox-cells = <1>; 2629 status = "disabled"; 2630 }; 2631 2632 combphy0_us: phy@fe820000 { 2633 compatible = "rockchip,rk3568-naneng-combphy"; 2634 reg = <0x0 0xfe820000 0x0 0x100>; 2635 #phy-cells = <1>; 2636 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; 2637 clock-names = "refclk", "apbclk"; 2638 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; 2639 assigned-clock-rates = <24000000>; 2640 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 2641 reset-names = "combphy-apb", "combphy"; 2642 rockchip,pipe-grf = <&pipegrf>; 2643 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 2644 status = "disabled"; 2645 }; 2646 2647 combphy1_usq: phy@fe830000 { 2648 compatible = "rockchip,rk3568-naneng-combphy"; 2649 reg = <0x0 0xfe830000 0x0 0x100>; 2650 #phy-cells = <1>; 2651 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; 2652 clock-names = "refclk", "apbclk"; 2653 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 2654 assigned-clock-rates = <24000000>; 2655 resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; 2656 reset-names = "combphy-apb", "combphy"; 2657 rockchip,pipe-grf = <&pipegrf>; 2658 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 2659 status = "disabled"; 2660 }; 2661 2662 combphy2_psq: phy@fe840000 { 2663 compatible = "rockchip,rk3568-naneng-combphy"; 2664 reg = <0x0 0xfe840000 0x0 0x100>; 2665 #phy-cells = <1>; 2666 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; 2667 clock-names = "refclk", "apbclk"; 2668 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 2669 assigned-clock-rates = <24000000>; 2670 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; 2671 reset-names = "combphy-apb", "combphy"; 2672 rockchip,pipe-grf = <&pipegrf>; 2673 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 2674 status = "disabled"; 2675 }; 2676 2677 mipi_dphy0: mipi-dphy@fe850000 { 2678 compatible = "rockchip,rk3568-mipi-dphy"; 2679 reg = <0x0 0xfe850000 0x0 0x10000>; 2680 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 2681 clock-names = "ref", "pclk"; 2682 clock-output-names = "mipi_dphy_pll"; 2683 #clock-cells = <0>; 2684 resets = <&cru SRST_P_MIPIDSIPHY0>; 2685 reset-names = "apb"; 2686 power-domains = <&power RK3568_PD_VO>; 2687 #phy-cells = <0>; 2688 rockchip,grf = <&grf>; 2689 status = "disabled"; 2690 }; 2691 2692 video_phy0: video-phy@fe850000 { 2693 compatible = "rockchip,rk3568-video-phy"; 2694 reg = <0x0 0xfe850000 0x0 0x10000>, 2695 <0x0 0xfe060000 0x0 0x10000>; 2696 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, 2697 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; 2698 clock-names = "ref", "pclk_phy", "pclk_host"; 2699 #clock-cells = <0>; 2700 resets = <&cru SRST_P_MIPIDSIPHY0>; 2701 reset-names = "rst"; 2702 power-domains = <&power RK3568_PD_VO>; 2703 #phy-cells = <0>; 2704 status = "disabled"; 2705 }; 2706 2707 mipi_dphy1: mipi-dphy@fe860000 { 2708 compatible = "rockchip,rk3568-mipi-dphy"; 2709 reg = <0x0 0xfe860000 0x0 0x10000>; 2710 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 2711 clock-names = "ref", "pclk"; 2712 clock-output-names = "mipi_dphy1_pll"; 2713 #clock-cells = <0>; 2714 resets = <&cru SRST_P_MIPIDSIPHY1>; 2715 reset-names = "apb"; 2716 power-domains = <&power RK3568_PD_VO>; 2717 #phy-cells = <0>; 2718 rockchip,grf = <&grf>; 2719 status = "disabled"; 2720 }; 2721 2722 video_phy1: video-phy@fe860000 { 2723 compatible = "rockchip,rk3568-video-phy"; 2724 reg = <0x0 0xfe860000 0x0 0x10000>, 2725 <0x0 0xfe070000 0x0 0x10000>; 2726 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, 2727 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; 2728 clock-names = "ref", "pclk_phy", "pclk_host"; 2729 #clock-cells = <0>; 2730 resets = <&cru SRST_P_MIPIDSIPHY1>; 2731 reset-names = "rst"; 2732 power-domains = <&power RK3568_PD_VO>; 2733 #phy-cells = <0>; 2734 status = "disabled"; 2735 }; 2736 2737 csi_dphy: csi-dphy@fe870000 { 2738 compatible = "rockchip,rk3568-csi-dphy"; 2739 reg = <0x0 0xfe870000 0x0 0x1000>; 2740 clocks = <&cru PCLK_MIPICSIPHY>; 2741 clock-names = "pclk"; 2742 rockchip,grf = <&grf>; 2743 status = "disabled"; 2744 }; 2745 2746 usb2phy0: usb2-phy@fe8a0000 { 2747 compatible = "rockchip,rk3568-usb2phy"; 2748 reg = <0x0 0xfe8a0000 0x0 0x10000>; 2749 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 2750 clocks = <&pmucru CLK_USBPHY0_REF>; 2751 clock-names = "phyclk"; 2752 #clock-cells = <0>; 2753 assigned-clocks = <&cru USB480M>; 2754 assigned-clock-parents = <&usb2phy0>; 2755 clock-output-names = "usb480m_phy"; 2756 rockchip,usbgrf = <&usb2phy0_grf>; 2757 status = "disabled"; 2758 2759 u2phy0_host: host-port { 2760 #phy-cells = <0>; 2761 status = "disabled"; 2762 }; 2763 2764 u2phy0_otg: otg-port { 2765 #phy-cells = <0>; 2766 status = "disabled"; 2767 }; 2768 }; 2769 2770 usb2phy1: usb2-phy@fe8b0000 { 2771 compatible = "rockchip,rk3568-usb2phy"; 2772 reg = <0x0 0xfe8b0000 0x0 0x10000>; 2773 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2774 clocks = <&pmucru CLK_USBPHY1_REF>; 2775 clock-names = "phyclk"; 2776 #clock-cells = <0>; 2777 rockchip,usbgrf = <&usb2phy1_grf>; 2778 status = "disabled"; 2779 2780 u2phy1_host: host-port { 2781 #phy-cells = <0>; 2782 status = "disabled"; 2783 }; 2784 2785 u2phy1_otg: otg-port { 2786 #phy-cells = <0>; 2787 status = "disabled"; 2788 }; 2789 }; 2790 2791 pcie30phy: phy@fe8c0000 { 2792 compatible = "rockchip,rk3568-pcie3-phy"; 2793 reg = <0x0 0xfe8c0000 0x0 0x20000>; 2794 #phy-cells = <0>; 2795 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, 2796 <&cru PCLK_PCIE30PHY>; 2797 clock-names = "refclk_m", "refclk_n", "pclk"; 2798 resets = <&cru SRST_PCIE30PHY>; 2799 reset-names = "phy"; 2800 rockchip,phy-grf = <&pcie30_phy_grf>; 2801 status = "disabled"; 2802 }; 2803 2804 pinctrl: pinctrl { 2805 compatible = "rockchip,rk3568-pinctrl"; 2806 rockchip,grf = <&grf>; 2807 rockchip,pmu = <&pmugrf>; 2808 #address-cells = <2>; 2809 #size-cells = <2>; 2810 ranges; 2811 2812 gpio0: gpio@fdd60000 { 2813 compatible = "rockchip,gpio-bank"; 2814 reg = <0x0 0xfdd60000 0x0 0x100>; 2815 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2816 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 2817 2818 gpio-controller; 2819 #gpio-cells = <2>; 2820 gpio-ranges = <&pinctrl 0 0 32>; 2821 interrupt-controller; 2822 #interrupt-cells = <2>; 2823 }; 2824 2825 gpio1: gpio@fe740000 { 2826 compatible = "rockchip,gpio-bank"; 2827 reg = <0x0 0xfe740000 0x0 0x100>; 2828 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2829 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2830 2831 gpio-controller; 2832 #gpio-cells = <2>; 2833 gpio-ranges = <&pinctrl 0 32 32>; 2834 interrupt-controller; 2835 #interrupt-cells = <2>; 2836 }; 2837 2838 gpio2: gpio@fe750000 { 2839 compatible = "rockchip,gpio-bank"; 2840 reg = <0x0 0xfe750000 0x0 0x100>; 2841 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2842 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2843 2844 gpio-controller; 2845 #gpio-cells = <2>; 2846 gpio-ranges = <&pinctrl 0 64 32>; 2847 interrupt-controller; 2848 #interrupt-cells = <2>; 2849 }; 2850 2851 gpio3: gpio@fe760000 { 2852 compatible = "rockchip,gpio-bank"; 2853 reg = <0x0 0xfe760000 0x0 0x100>; 2854 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2855 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2856 2857 gpio-controller; 2858 #gpio-cells = <2>; 2859 gpio-ranges = <&pinctrl 0 96 32>; 2860 interrupt-controller; 2861 #interrupt-cells = <2>; 2862 }; 2863 2864 gpio4: gpio@fe770000 { 2865 compatible = "rockchip,gpio-bank"; 2866 reg = <0x0 0xfe770000 0x0 0x100>; 2867 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2868 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2869 2870 gpio-controller; 2871 #gpio-cells = <2>; 2872 gpio-ranges = <&pinctrl 0 128 32>; 2873 interrupt-controller; 2874 #interrupt-cells = <2>; 2875 }; 2876 }; 2877}; 2878 2879#include "rk3568-pinctrl.dtsi" 2880