1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rv1126-cru.h> 7#include <dt-bindings/power/rv1126-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rv1126.h> 15#include "rv1126-dram-default-timing.dtsi" 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 compatible = "rockchip,rv1126"; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 dphy0 = &csi_dphy0; 41 dphy1 = &csi_dphy1; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@f00 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a7"; 51 reg = <0xf00>; 52 enable-method = "psci"; 53 clocks = <&cru ARMCLK>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 cpu-idle-states = <&CPU_SLEEP>; 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 enable-method = "psci"; 63 clocks = <&cru ARMCLK>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 }; 67 68 cpu2: cpu@f02 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a7"; 71 reg = <0xf02>; 72 enable-method = "psci"; 73 clocks = <&cru ARMCLK>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 cpu-idle-states = <&CPU_SLEEP>; 76 }; 77 78 cpu3: cpu@f03 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a7"; 81 reg = <0xf03>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 cpu-idle-states = <&CPU_SLEEP>; 86 }; 87 88 idle-states { 89 entry-method = "psci"; 90 91 CPU_SLEEP: cpu-sleep { 92 compatible = "arm,idle-state"; 93 local-timer-stop; 94 arm,psci-suspend-param = <0x0010000>; 95 entry-latency-us = <120>; 96 exit-latency-us = <250>; 97 min-residency-us = <900>; 98 }; 99 }; 100 101 }; 102 103 cpu0_opp_table: cpu0-opp-table { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 rockchip,reboot-freq = <816000>; 107 108 opp-408000000 { 109 opp-hz = /bits/ 64 <408000000>; 110 opp-microvolt = <725000 725000 1100000>; 111 clock-latency-ns = <40000>; 112 }; 113 opp-600000000 { 114 opp-hz = /bits/ 64 <600000000>; 115 opp-microvolt = <725000 725000 1000000>; 116 clock-latency-ns = <40000>; 117 }; 118 opp-816000000 { 119 opp-hz = /bits/ 64 <816000000>; 120 opp-microvolt = <725000 725000 1000000>; 121 clock-latency-ns = <40000>; 122 opp-suspend; 123 }; 124 opp-1008000000 { 125 opp-hz = /bits/ 64 <1008000000>; 126 opp-microvolt = <775000 775000 1000000>; 127 clock-latency-ns = <40000>; 128 }; 129 opp-1200000000 { 130 opp-hz = /bits/ 64 <1200000000>; 131 opp-microvolt = <825000 825000 1000000>; 132 clock-latency-ns = <40000>; 133 }; 134 opp-1296000000 { 135 opp-hz = /bits/ 64 <1296000000>; 136 opp-microvolt = <875000 875000 1000000>; 137 clock-latency-ns = <40000>; 138 }; 139 opp-1416000000 { 140 opp-hz = /bits/ 64 <1416000000>; 141 opp-microvolt = <925000 925000 1000000>; 142 clock-latency-ns = <40000>; 143 }; 144 opp-1512000000 { 145 opp-hz = /bits/ 64 <1512000000>; 146 opp-microvolt = <975000 975000 1000000>; 147 clock-latency-ns = <40000>; 148 }; 149 }; 150 151 arm-pmu { 152 compatible = "arm,cortex-a7-pmu"; 153 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 158 }; 159 160 bus_soc: bus-soc { 161 compatible = "rockchip,rv1126-bus"; 162 rockchip,busfreq-policy = "smc"; 163 soc-bus0 { 164 bus-id = <0>; 165 cfg-val = <0x00300020>; 166 enable-msk = <0x7144>; 167 status = "okay"; 168 }; 169 soc-bus1 { 170 bus-id = <1>; 171 cfg-val = <0x00300020>; 172 enable-msk = <0x70ff>; 173 status = "disabled"; 174 }; 175 soc-bus2 { 176 bus-id = <2>; 177 cfg-val = <0x00300020>; 178 enable-msk = <0x70ff>; 179 status = "disabled"; 180 }; 181 soc-bus3 { 182 bus-id = <3>; 183 cfg-val = <0x00300020>; 184 enable-msk = <0x70ff>; 185 status = "disabled"; 186 }; 187 soc-bus4 { 188 bus-id = <4>; 189 cfg-val = <0x00300020>; 190 enable-msk = <0x7011>; 191 status = "disabled"; 192 }; 193 soc-bus5 { 194 bus-id = <5>; 195 cfg-val = <0x00300020>; 196 enable-msk = <0x7011>; 197 status = "disabled"; 198 }; 199 soc-bus6 { 200 bus-id = <6>; 201 cfg-val = <0x00300020>; 202 enable-msk = <0x7011>; 203 status = "disabled"; 204 }; 205 soc-bus7 { 206 bus-id = <7>; 207 cfg-val = <0x00300020>; 208 enable-msk = <0x0>; 209 status = "disabled"; 210 }; 211 soc-bus8 { 212 bus-id = <8>; 213 cfg-val = <0x00300020>; 214 enable-msk = <0x0>; 215 status = "disabled"; 216 }; 217 soc-bus9 { 218 bus-id = <9>; 219 cfg-val = <0x00300020>; 220 enable-msk = <0x0>; 221 status = "disabled"; 222 }; 223 soc-bus10 { 224 bus-id = <10>; 225 cfg-val = <0x00300020>; 226 enable-msk = <0x0>; 227 status = "disabled"; 228 }; 229 soc-bus11 { 230 bus-id = <11>; 231 cfg-val = <0x00300020>; 232 enable-msk = <0x7000>; 233 status = "okey"; 234 }; 235 }; 236 237 display_subsystem: display-subsystem { 238 compatible = "rockchip,display-subsystem"; 239 ports = <&vop_out>; 240 status = "disabled"; 241 242 route { 243 route_dsi: route-dsi { 244 status = "disabled"; 245 logo,uboot = "logo.bmp"; 246 logo,kernel = "logo_kernel.bmp"; 247 logo,mode = "center"; 248 charge_logo,mode = "center"; 249 connect = <&vop_out_dsi>; 250 }; 251 252 route_rgb: route-rgb { 253 status = "disabled"; 254 logo,uboot = "logo.bmp"; 255 logo,kernel = "logo_kernel.bmp"; 256 logo,mode = "center"; 257 charge_logo,mode = "center"; 258 connect = <&vop_out_rgb>; 259 }; 260 }; 261 }; 262 263 fiq_debugger: fiq-debugger { 264 compatible = "rockchip,fiq-debugger"; 265 rockchip,serial-id = <2>; 266 rockchip,wake-irq = <0>; 267 rockchip,irq-mode-enable = <0>; 268 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 269 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 270 status = "disabled"; 271 }; 272 273 firmware { 274 optee: optee { 275 compatible = "linaro,optee-tz"; 276 method = "smc"; 277 status = "disabled"; 278 }; 279 }; 280 281 mpp_srv: mpp-srv { 282 compatible = "rockchip,mpp-service"; 283 rockchip,taskqueue-count = <3>; 284 rockchip,resetgroup-count = <3>; 285 status = "disabled"; 286 }; 287 288 psci: psci { 289 compatible = "arm,psci-1.0"; 290 method = "smc"; 291 }; 292 293 reserved-memory { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges; 297 298 isp_reserved: isp { 299 compatible = "shared-dma-pool"; 300 reusable; 301 size = <0x6800000>; 302 }; 303 304 ramoops: ramoops@8000000 { 305 compatible = "ramoops"; 306 reg = <0x8000000 0x100000>; 307 record-size = <0x20000>; 308 console-size = <0x40000>; 309 ftrace-size = <0x00000>; 310 pmsg-size = <0x40000>; 311 status = "disabled"; 312 }; 313 }; 314 315 rockchip_suspend: rockchip-suspend { 316 compatible = "rockchip,pm-rv1126"; 317 status = "disabled"; 318 rockchip,sleep-debug-en = <0>; 319 rockchip,sleep-mode-config = < 320 (0 321 | RKPM_SLP_ARMOFF 322 | RKPM_SLP_PMU_PMUALIVE_32K 323 | RKPM_SLP_PMU_DIS_OSC 324 | RKPM_SLP_PMIC_LP 325 ) 326 >; 327 rockchip,wakeup-config = < 328 (0 329 | RKPM_GPIO_WKUP_EN 330 ) 331 >; 332 }; 333 334 rockchip_system_monitor: rockchip-system-monitor { 335 compatible = "rockchip,system-monitor"; 336 }; 337 338 thermal_zones: thermal-zones { 339 cpu_thermal: cpu-thermal { 340 polling-delay-passive = <20>; /* milliseconds */ 341 polling-delay = <1000>; /* milliseconds */ 342 sustainable-power = <977>; /* milliwatts */ 343 344 thermal-sensors = <&cpu_tsadc 0>; 345 }; 346 347 npu_thermal: npu-thermal { 348 polling-delay-passive = <20>; /* milliseconds */ 349 polling-delay = <1000>; /* milliseconds */ 350 sustainable-power = <977>; /* milliwatts */ 351 352 thermal-sensors = <&npu_tsadc 0>; 353 }; 354 }; 355 356 timer { 357 compatible = "arm,armv7-timer"; 358 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 359 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 360 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 361 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 362 clock-frequency = <24000000>; 363 }; 364 365 xin24m: oscillator { 366 compatible = "fixed-clock"; 367 clock-frequency = <24000000>; 368 clock-output-names = "xin24m"; 369 #clock-cells = <0>; 370 }; 371 372 gmac_clkin_m0: external-gmac-clockm0 { 373 compatible = "fixed-clock"; 374 clock-frequency = <125000000>; 375 clock-output-names = "clk_gmac_rgmii_clkin_m0"; 376 #clock-cells = <0>; 377 }; 378 379 gmac_clkini_m1: external-gmac-clockm1 { 380 compatible = "fixed-clock"; 381 clock-frequency = <125000000>; 382 clock-output-names = "clk_gmac_rgmii_clkin_m1"; 383 #clock-cells = <0>; 384 }; 385 386 grf: syscon@fe000000 { 387 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 388 reg = <0xfe000000 0x20000>; 389 390 rgb: rgb { 391 compatible = "rockchip,rv1126-rgb"; 392 status = "disabled"; 393 394 ports { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 port@0 { 399 reg = <0>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 rgb_in_vop: endpoint@0 { 404 reg = <0>; 405 remote-endpoint = <&vop_out_rgb>; 406 }; 407 }; 408 409 }; 410 }; 411 }; 412 413 pmugrf: syscon@fe020000 { 414 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 415 reg = <0xfe020000 0x1000>; 416 417 pmu_io_domains: io-domains { 418 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 419 }; 420 421 reboot-mode { 422 compatible = "syscon-reboot-mode"; 423 offset = <0x200>; 424 mode-bootloader = <BOOT_BL_DOWNLOAD>; 425 mode-charge = <BOOT_CHARGING>; 426 mode-fastboot = <BOOT_FASTBOOT>; 427 mode-loader = <BOOT_BL_DOWNLOAD>; 428 mode-normal = <BOOT_NORMAL>; 429 mode-recovery = <BOOT_RECOVERY>; 430 mode-ums = <BOOT_UMS>; 431 }; 432 }; 433 434 qos_usb_host: qos@fe810000 { 435 compatible = "syscon"; 436 reg = <0xfe810000 0x20>; 437 }; 438 439 qos_usb_otg: qos@fe810080 { 440 compatible = "syscon"; 441 reg = <0xfe810080 0x20>; 442 }; 443 444 qos_npu: qos@fe850000 { 445 compatible = "syscon"; 446 reg = <0xfe850000 0x20>; 447 }; 448 449 qos_emmc: qos@fe860000 { 450 compatible = "syscon"; 451 reg = <0xfe860000 0x20>; 452 }; 453 454 qos_nandc: qos@fe860080 { 455 compatible = "syscon"; 456 reg = <0xfe860080 0x20>; 457 }; 458 459 qos_sfc: qos@fe860200 { 460 compatible = "syscon"; 461 reg = <0xfe860200 0x20>; 462 }; 463 464 qos_sdio: qos@fe86c000 { 465 compatible = "syscon"; 466 reg = <0xfe86c000 0x20>; 467 }; 468 469 qos_vepu_rd0: qos@fe870000 { 470 compatible = "syscon"; 471 reg = <0xfe870000 0x20>; 472 }; 473 474 qos_vepu_rd1: qos@fe870080 { 475 compatible = "syscon"; 476 reg = <0xfe870080 0x20>; 477 }; 478 479 qos_vepu_wr: qos@fe870100 { 480 compatible = "syscon"; 481 reg = <0xfe870100 0x20>; 482 }; 483 484 qos_ispp_m0: qos@fe880000 { 485 compatible = "syscon"; 486 reg = <0xfe880000 0x20>; 487 }; 488 489 qos_ispp_m1: qos@fe880080 { 490 compatible = "syscon"; 491 reg = <0xfe880080 0x20>; 492 }; 493 494 qos_isp: qos@fe890000 { 495 compatible = "syscon"; 496 reg = <0xfe890000 0x20>; 497 }; 498 499 qos_cif_lite: qos@fe890080 { 500 compatible = "syscon"; 501 reg = <0xfe890080 0x20>; 502 }; 503 504 qos_cif: qos@fe890100 { 505 compatible = "syscon"; 506 reg = <0xfe890100 0x20>; 507 }; 508 509 qos_iep: qos@fe8a0000 { 510 compatible = "syscon"; 511 reg = <0xfe8a0000 0x20>; 512 }; 513 514 qos_rga_rd: qos@fe8a0080 { 515 compatible = "syscon"; 516 reg = <0xfe8a0080 0x20>; 517 }; 518 519 qos_rga_wr: qos@fe8a0100 { 520 compatible = "syscon"; 521 reg = <0xfe8a0100 0x20>; 522 }; 523 524 qos_vop: qos@fe8a0180 { 525 compatible = "syscon"; 526 reg = <0xfe8a0180 0x20>; 527 }; 528 529 qos_vdpu: qos@fe8b0000 { 530 compatible = "syscon"; 531 reg = <0xfe8b0000 0x20>; 532 }; 533 534 qos_jpeg: qos@fe8c0000 { 535 compatible = "syscon"; 536 reg = <0xfe8c0000 0x20>; 537 }; 538 539 qos_crypto: qos@fe8d0000 { 540 compatible = "syscon"; 541 reg = <0xfe8d0000 0x20>; 542 }; 543 544 gic: interrupt-controller@feff0000 { 545 compatible = "arm,gic-400"; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 #address-cells = <0>; 549 550 reg = <0xfeff1000 0x1000>, 551 <0xfeff2000 0x2000>, 552 <0xfeff4000 0x2000>, 553 <0xfeff6000 0x2000>; 554 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 555 }; 556 557 arm-debug@ff010000 { 558 compatible = "rockchip,debug"; 559 reg = <0xff010000 0x1000>, 560 <0xff012000 0x1000>, 561 <0xff014000 0x1000>, 562 <0xff016000 0x1000>; 563 }; 564 565 pvtm@ff040000 { 566 compatible = "rockchip,rv1126-cpu-pvtm"; 567 reg = <0xff040000 0x100>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 pvtm@0 { 572 reg = <0>; 573 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>; 574 clock-names = "clk", "pclk"; 575 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>; 576 reset-names = "rst", "rst-p"; 577 }; 578 }; 579 580 pmu: power-management@ff3e0000 { 581 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 582 reg = <0xff3e0000 0x1000>; 583 584 power: power-controller { 585 compatible = "rockchip,rv1126-power-controller"; 586 #power-domain-cells = <1>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "okay"; 590 591 /* These power domains are grouped by VD_NPU */ 592 pd_npu@RV1126_PD_NPU { 593 reg = <RV1126_PD_NPU>; 594 clocks = <&cru ACLK_NPU>, 595 <&cru HCLK_NPU>, 596 <&cru PCLK_PDNPU>, 597 <&cru CLK_CORE_NPU>; 598 pm_qos = <&qos_npu>; 599 }; 600 /* These power domains are grouped by VD_VEPU */ 601 pd_vepu@RV1126_PD_VEPU { 602 reg = <RV1126_PD_VEPU>; 603 clocks = <&cru ACLK_VENC>, 604 <&cru HCLK_VENC>, 605 <&cru CLK_VENC_CORE>; 606 pm_qos = <&qos_vepu_rd0>, 607 <&qos_vepu_rd1>, 608 <&qos_vepu_wr>; 609 }; 610 /* These power domains are grouped by VD_LOGIC */ 611 pd_crypto@RV1126_PD_CRYPTO { 612 reg = <RV1126_PD_CRYPTO>; 613 clocks = <&cru ACLK_CRYPTO>, 614 <&cru HCLK_CRYPTO>, 615 <&cru CLK_CRYPTO_CORE>, 616 <&cru CLK_CRYPTO_PKA>; 617 pm_qos = <&qos_crypto>; 618 }; 619 pd_vi@RV1126_PD_VI { 620 reg = <RV1126_PD_VI>; 621 clocks = <&cru ACLK_ISP>, 622 <&cru HCLK_ISP>, 623 <&cru CLK_ISP>, 624 <&cru ACLK_CIF>, 625 <&cru HCLK_CIF>, 626 <&cru DCLK_CIF>, 627 <&cru CLK_CIF_OUT>, 628 <&cru CLK_MIPICSI_OUT>, 629 <&cru PCLK_CSIHOST>, 630 <&cru ACLK_CIFLITE>, 631 <&cru HCLK_CIFLITE>, 632 <&cru DCLK_CIFLITE>; 633 pm_qos = <&qos_isp>, 634 <&qos_cif_lite>, 635 <&qos_cif>; 636 }; 637 pd_vo@RV1126_PD_VO { 638 reg = <RV1126_PD_VO>; 639 clocks = <&cru ACLK_RGA>, 640 <&cru HCLK_RGA>, 641 <&cru CLK_RGA_CORE>, 642 <&cru ACLK_VOP>, 643 <&cru HCLK_VOP>, 644 <&cru DCLK_VOP>, 645 <&cru PCLK_DSIHOST>, 646 <&cru ACLK_IEP>, 647 <&cru HCLK_IEP>, 648 <&cru CLK_IEP_CORE>; 649 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 650 <&qos_vop>, <&qos_iep>; 651 }; 652 pd_ispp@RV1126_PD_ISPP { 653 reg = <RV1126_PD_ISPP>; 654 clocks = <&cru ACLK_ISPP>, 655 <&cru HCLK_ISPP>, 656 <&cru CLK_ISPP>; 657 pm_qos = <&qos_ispp_m0>, 658 <&qos_ispp_m1>; 659 }; 660 pd_vdpu@RV1126_PD_VDPU { 661 reg = <RV1126_PD_VDPU>; 662 clocks = <&cru ACLK_VDEC>, 663 <&cru HCLK_VDEC>, 664 <&cru CLK_VDEC_CORE>, 665 <&cru CLK_VDEC_CA>, 666 <&cru CLK_VDEC_HEVC_CA>, 667 <&cru ACLK_JPEG>, 668 <&cru HCLK_JPEG>; 669 pm_qos = <&qos_vdpu>, 670 <&qos_jpeg>; 671 }; 672 pd_nvm@RV1126_PD_NVM { 673 reg = <RV1126_PD_NVM>; 674 clocks = <&cru HCLK_EMMC>, 675 <&cru CLK_EMMC>, 676 <&cru HCLK_NANDC>, 677 <&cru CLK_NANDC>, 678 <&cru HCLK_SFC>, 679 <&cru HCLK_SFCXIP>, 680 <&cru SCLK_SFC>; 681 pm_qos = <&qos_emmc>, 682 <&qos_nandc>, 683 <&qos_sfc>; 684 }; 685 pd_sdio@RV1126_PD_SDIO { 686 reg = <RV1126_PD_SDIO>; 687 clocks = <&cru HCLK_SDIO>, 688 <&cru CLK_SDIO>; 689 pm_qos = <&qos_sdio>; 690 }; 691 pd_usb@RV1126_PD_USB { 692 reg = <RV1126_PD_USB>; 693 clocks = <&cru HCLK_USBHOST>, 694 <&cru HCLK_USBHOST_ARB>, 695 <&cru CLK_USBHOST_UTMI_OHCI>, 696 <&cru ACLK_USBOTG>, 697 <&cru CLK_USBOTG_REF>; 698 pm_qos = <&qos_usb_host>, 699 <&qos_usb_otg>; 700 }; 701 }; 702 }; 703 704 i2c0: i2c@ff3f0000 { 705 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 706 reg = <0xff3f0000 0x1000>; 707 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 711 clock-names = "i2c", "pclk"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&i2c0_xfer>; 714 status = "disabled"; 715 }; 716 717 i2c2: i2c@ff400000 { 718 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 719 reg = <0xff400000 0x1000>; 720 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 rockchip,grf = <&pmugrf>; 724 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; 725 clock-names = "i2c", "pclk"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&i2c2_xfer>; 728 status = "disabled"; 729 }; 730 731 amba { 732 compatible = "simple-bus"; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 ranges; 736 737 dmac: dma-controller@ff4e0000 { 738 compatible = "arm,pl330", "arm,primecell"; 739 reg = <0xff4e0000 0x4000>; 740 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 742 #dma-cells = <1>; 743 clocks = <&cru ACLK_DMAC>; 744 clock-names = "apb_pclk"; 745 }; 746 }; 747 748 uart1: serial@ff410000 { 749 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 750 reg = <0xff410000 0x100>; 751 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 752 reg-shift = <2>; 753 reg-io-width = <4>; 754 dmas = <&dmac 7>, <&dmac 6>; 755 clock-frequency = <24000000>; 756 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 757 clock-names = "baudclk", "apb_pclk"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 760 status = "disabled"; 761 }; 762 763 pwm0: pwm@ff430000 { 764 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 765 reg = <0xff430000 0x10>; 766 #pwm-cells = <3>; 767 pinctrl-names = "active"; 768 pinctrl-0 = <&pwm0m0_pins>; 769 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 770 clock-names = "pwm", "pclk"; 771 status = "disabled"; 772 }; 773 774 pwm1: pwm@ff430010 { 775 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 776 reg = <0xff430010 0x10>; 777 #pwm-cells = <3>; 778 pinctrl-names = "active"; 779 pinctrl-0 = <&pwm1m0_pins>; 780 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 781 clock-names = "pwm", "pclk"; 782 status = "disabled"; 783 }; 784 785 pwm2: pwm@ff430020 { 786 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 787 reg = <0xff430020 0x10>; 788 #pwm-cells = <3>; 789 pinctrl-names = "active"; 790 pinctrl-0 = <&pwm2m0_pins>; 791 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 792 clock-names = "pwm", "pclk"; 793 status = "disabled"; 794 }; 795 796 pwm3: pwm@ff430030 { 797 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 798 reg = <0xff430030 0x10>; 799 #pwm-cells = <3>; 800 pinctrl-names = "active"; 801 pinctrl-0 = <&pwm3m0_pins>; 802 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 803 clock-names = "pwm", "pclk"; 804 status = "disabled"; 805 }; 806 807 pwm4: pwm@ff440000 { 808 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 809 reg = <0xff440000 0x10>; 810 #pwm-cells = <3>; 811 pinctrl-names = "active"; 812 pinctrl-0 = <&pwm4m0_pins>; 813 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 814 clock-names = "pwm", "pclk"; 815 status = "disabled"; 816 }; 817 818 pwm5: pwm@ff440010 { 819 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 820 reg = <0xff440010 0x10>; 821 #pwm-cells = <3>; 822 pinctrl-names = "active"; 823 pinctrl-0 = <&pwm5m0_pins>; 824 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 825 clock-names = "pwm", "pclk"; 826 status = "disabled"; 827 }; 828 829 pwm6: pwm@ff440020 { 830 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 831 reg = <0xff440020 0x10>; 832 #pwm-cells = <3>; 833 pinctrl-names = "active"; 834 pinctrl-0 = <&pwm6m0_pins>; 835 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 836 clock-names = "pwm", "pclk"; 837 status = "disabled"; 838 }; 839 840 pwm7: pwm@ff440030 { 841 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 842 reg = <0xff440030 0x10>; 843 #pwm-cells = <3>; 844 pinctrl-names = "active"; 845 pinctrl-0 = <&pwm7m0_pins>; 846 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 847 clock-names = "pwm", "pclk"; 848 status = "disabled"; 849 }; 850 851 spi0: spi@ff450000 { 852 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 853 reg = <0xff450000 0x1000>; 854 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 clocks = <&pmucru CLK_SPI0>, <&pmucru PCLK_SPI0>; 858 clock-names = "spiclk", "apb_pclk"; 859 dmas = <&dmac 1>, <&dmac 0>; 860 dma-names = "tx", "rx"; 861 pinctrl-names = "default", "high_speed"; 862 pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>; 863 pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>; 864 status = "disabled"; 865 }; 866 867 pvtm@ff470000 { 868 compatible = "rockchip,rv1126-pmu-pvtm"; 869 reg = <0xff470000 0x100>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 pvtm@2 { 874 reg = <2>; 875 clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>; 876 clock-names = "clk", "pclk"; 877 resets = <&pmucru SRST_PMUPVTM>, 878 <&pmucru SRST_PMUPVTM_P>; 879 reset-names = "rst", "rst-p"; 880 }; 881 }; 882 883 pmucru: clock-controller@ff480000 { 884 compatible = "rockchip,rv1126-pmucru"; 885 reg = <0xff480000 0x1000>; 886 rockchip,grf = <&grf>; 887 #clock-cells = <1>; 888 #reset-cells = <1>; 889 }; 890 891 cru: clock-controller@ff490000 { 892 compatible = "rockchip,rv1126-cru"; 893 reg = <0xff490000 0x1000>; 894 rockchip,grf = <&grf>; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 898 assigned-clocks = 899 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 900 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 901 <&cru PLL_HPLL>, <&cru ARMCLK>, 902 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 903 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 904 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 905 <&cru HCLK_PDCORE_NIU>; 906 assigned-clock-rates = 907 <32768>, <1188000000>, 908 <100000000>, <500000000>, 909 <1400000000>, <600000000>, 910 <500000000>, <200000000>, 911 <100000000>, <300000000>, 912 <200000000>, <150000000>, 913 <200000000>; 914 assigned-clock-parents = 915 <&pmucru CLK_OSC0_DIV32K>; 916 }; 917 918 csi_dphy0: csi-dphy@ff4b0000 { 919 compatible = "rockchip,rv1126-csi-dphy"; 920 reg = <0xff4b0000 0x8000>; 921 clocks = <&cru PCLK_CSIPHY0>; 922 clock-names = "pclk"; 923 rockchip,grf = <&grf>; 924 status = "disabled"; 925 }; 926 927 csi_dphy1: csi-dphy@ff4b8000 { 928 compatible = "rockchip,rv1126-csi-dphy"; 929 reg = <0xff4b8000 0x8000>; 930 clocks = <&cru PCLK_CSIPHY1>; 931 clock-names = "pclk"; 932 rockchip,grf = <&grf>; 933 status = "disabled"; 934 }; 935 936 u2phy0: usb2-phy@ff4c0000 { 937 compatible = "rockchip,rv1126-usb2phy"; 938 reg = <0xff4c0000 0x8000>; 939 rockchip,grf = <&grf>; 940 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>; 941 clock-names = "phyclk", "pclk"; 942 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>; 943 reset-names = "u2phy", "u2phy-apb"; 944 #clock-cells = <0>; 945 status = "disabled"; 946 947 u2phy_otg: otg-port { 948 #phy-cells = <0>; 949 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "otg-bvalid", "otg-id", 954 "linestate", "disconnect"; 955 status = "disabled"; 956 }; 957 }; 958 959 u2phy1: usb2-phy@ff4c8000 { 960 compatible = "rockchip,rv1126-usb2phy"; 961 reg = <0xff4c8000 0x8000>; 962 rockchip,grf = <&grf>; 963 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>; 964 clock-names = "phyclk", "pclk"; 965 assigned-clocks = <&cru USB480M>; 966 assigned-clock-parents = <&u2phy1>; 967 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>; 968 reset-names = "u2phy", "u2phy-apb"; 969 #clock-cells = <0>; 970 clock-output-names = "usb480m_phy"; 971 status = "disabled"; 972 973 u2phy_host: host-port { 974 #phy-cells = <0>; 975 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 977 interrupt-names = "linestate", "disconnect"; 978 status = "disabled"; 979 }; 980 }; 981 982 mipi_dphy: mipi-dphy@ff4d0000 { 983 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy"; 984 reg = <0xff4d0000 0x500>; 985 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>; 986 assigned-clock-rates = <24000000>; 987 clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>; 988 clock-names = "ref", "pclk"; 989 clock-output-names = "mipi_dphy_pll"; 990 #clock-cells = <0>; 991 resets = <&cru SRST_DSIPHY_P>; 992 reset-names = "apb"; 993 #phy-cells = <0>; 994 rockchip,grf = <&grf>; 995 status = "disabled"; 996 }; 997 998 crypto: crypto@ff500000 { 999 compatible = "rockchip,rv1126-crypto"; 1000 reg = <0xff500000 0x10000>; 1001 clock-names = "sclk_crypto", "sclk_crypto_apk"; 1002 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 1003 clock-frequency = <200000000>, <300000000>; 1004 }; 1005 1006 rng: rng@ff500000 { 1007 compatible = "rockchip,cryptov2-rng"; 1008 reg = <0xff500000 0x2000>; 1009 status = "disabled"; 1010 }; 1011 1012 i2c1: i2c@ff510000 { 1013 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1014 reg = <0xff510000 0x1000>; 1015 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1019 clock-names = "i2c", "pclk"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&i2c1_xfer>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c3: i2c@ff520000 { 1026 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1027 reg = <0xff520000 0x1000>; 1028 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1032 clock-names = "i2c", "pclk"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&i2c3m0_xfer>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c4: i2c@ff530000 { 1039 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1040 reg = <0xff530000 0x1000>; 1041 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1045 clock-names = "i2c", "pclk"; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&i2c4m0_xfer>; 1048 status = "disabled"; 1049 }; 1050 1051 i2c5: i2c@ff540000 { 1052 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1053 reg = <0xff540000 0x1000>; 1054 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1058 clock-names = "i2c", "pclk"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&i2c5m0_xfer>; 1061 status = "disabled"; 1062 }; 1063 1064 pwm8: pwm@ff550000 { 1065 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1066 reg = <0xff550000 0x10>; 1067 #pwm-cells = <3>; 1068 pinctrl-names = "active"; 1069 pinctrl-0 = <&pwm8m0_pins>; 1070 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1071 clock-names = "pwm", "pclk"; 1072 status = "disabled"; 1073 }; 1074 1075 pwm9: pwm@ff550010 { 1076 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1077 reg = <0xff550010 0x10>; 1078 #pwm-cells = <3>; 1079 pinctrl-names = "active"; 1080 pinctrl-0 = <&pwm9m0_pins>; 1081 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1082 clock-names = "pwm", "pclk"; 1083 status = "disabled"; 1084 }; 1085 1086 pwm10: pwm@ff550020 { 1087 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1088 reg = <0xff550020 0x10>; 1089 #pwm-cells = <3>; 1090 pinctrl-names = "active"; 1091 pinctrl-0 = <&pwm10m0_pins>; 1092 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1093 clock-names = "pwm", "pclk"; 1094 status = "disabled"; 1095 }; 1096 1097 pwm11: pwm@ff550030 { 1098 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1099 reg = <0xff550030 0x10>; 1100 #pwm-cells = <3>; 1101 pinctrl-names = "active"; 1102 pinctrl-0 = <&pwm11m0_pins>; 1103 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1104 clock-names = "pwm", "pclk"; 1105 status = "disabled"; 1106 }; 1107 1108 uart0: serial@ff560000 { 1109 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1110 reg = <0xff560000 0x100>; 1111 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1112 reg-shift = <2>; 1113 reg-io-width = <4>; 1114 dmas = <&dmac 5>, <&dmac 4>; 1115 clock-frequency = <24000000>; 1116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1117 clock-names = "baudclk", "apb_pclk"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; 1120 status = "disabled"; 1121 }; 1122 1123 uart2: serial@ff570000 { 1124 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1125 reg = <0xff570000 0x100>; 1126 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1127 reg-shift = <2>; 1128 reg-io-width = <4>; 1129 dmas = <&dmac 9>, <&dmac 8>; 1130 clock-frequency = <24000000>; 1131 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1132 clock-names = "baudclk", "apb_pclk"; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&uart2m1_xfer>; 1135 status = "disabled"; 1136 }; 1137 1138 uart3: serial@ff580000 { 1139 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1140 reg = <0xff580000 0x100>; 1141 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1142 reg-shift = <2>; 1143 reg-io-width = <4>; 1144 dmas = <&dmac 11>, <&dmac 10>; 1145 clock-frequency = <24000000>; 1146 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1147 clock-names = "baudclk", "apb_pclk"; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>; 1150 status = "disabled"; 1151 }; 1152 1153 uart4: serial@ff590000 { 1154 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1155 reg = <0xff590000 0x100>; 1156 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1157 reg-shift = <2>; 1158 reg-io-width = <4>; 1159 dmas = <&dmac 13>, <&dmac 12>; 1160 clock-frequency = <24000000>; 1161 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1162 clock-names = "baudclk", "apb_pclk"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; 1165 status = "disabled"; 1166 }; 1167 1168 uart5: serial@ff5a0000 { 1169 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1170 reg = <0xff5a0000 0x100>; 1171 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1172 reg-shift = <2>; 1173 reg-io-width = <4>; 1174 dmas = <&dmac 15>, <&dmac 14>; 1175 clock-frequency = <24000000>; 1176 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1177 clock-names = "baudclk", "apb_pclk"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 1180 status = "disabled"; 1181 }; 1182 1183 spi1: spi@ff5b0000 { 1184 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 1185 reg = <0xff5b0000 0x1000>; 1186 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1190 clock-names = "spiclk", "apb_pclk"; 1191 dmas = <&dmac 3>, <&dmac 2>; 1192 dma-names = "tx", "rx"; 1193 pinctrl-names = "default", "high_speed"; 1194 pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>; 1195 pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>; 1196 status = "disabled"; 1197 }; 1198 1199 otp: otp@ff5c0000 { 1200 compatible = "rockchip,rv1126-otp"; 1201 reg = <0xff5c0000 0x1000>; 1202 #address-cells = <1>; 1203 #size-cells = <1>; 1204 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>; 1205 clock-names = "otp", "apb_pclk"; 1206 status = "disabled"; 1207 1208 /* Data cells */ 1209 otp_id: id@7 { 1210 reg = <0x07 0x10>; 1211 }; 1212 cpu_leakage: cpu-leakage@17 { 1213 reg = <0x17 0x1>; 1214 }; 1215 logic_leakage: logic-leakage@18 { 1216 reg = <0x18 0x1>; 1217 }; 1218 npu_leakage: npu-leakage@19 { 1219 reg = <0x19 0x1>; 1220 }; 1221 }; 1222 1223 saradc: saradc@ff5e0000 { 1224 compatible = "rockchip,rk3399-saradc"; 1225 reg = <0xff5e0000 0x100>; 1226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1227 #io-channel-cells = <1>; 1228 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1229 clock-names = "saradc", "apb_pclk"; 1230 resets = <&cru SRST_SARADC_P>; 1231 reset-names = "saradc-apb"; 1232 status = "disabled"; 1233 }; 1234 1235 cpu_tsadc: tsadc@ff5f0000 { 1236 compatible = "rockchip,rv1126-tsadc"; 1237 reg = <0xff5f0000 0x100>; 1238 rockchip,grf = <&grf>; 1239 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1240 assigned-clocks = <&cru CLK_CPU_TSADC>; 1241 assigned-clock-rates = <4000000>; 1242 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>, 1243 <&cru CLK_CPU_TSADCPHY>; 1244 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1245 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>, 1246 <&cru SRST_CPU_TSADCPHY>; 1247 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1248 rockchip,hw-tshut-temp = <120000>; 1249 #thermal-sensor-cells = <1>; 1250 status = "disabled"; 1251 }; 1252 1253 npu_tsadc: tsadc@ff5f8000 { 1254 compatible = "rockchip,rv1126-tsadc"; 1255 reg = <0xff5f8000 0x100>; 1256 rockchip,grf = <&grf>; 1257 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1258 assigned-clocks = <&cru CLK_NPU_TSADC>; 1259 assigned-clock-rates = <4000000>; 1260 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>, 1261 <&cru CLK_NPU_TSADCPHY>; 1262 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1263 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>, 1264 <&cru SRST_NPU_TSADCPHY>; 1265 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1266 rockchip,hw-tshut-temp = <120000>; 1267 #thermal-sensor-cells = <1>; 1268 status = "disabled"; 1269 }; 1270 1271 can: can@ff610000 { 1272 compatible = "rockchip,can-1.0"; 1273 reg = <0xff610000 0x100>; 1274 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1275 assigned-clocks = <&cru CLK_CAN>; 1276 assigned-clock-rates = <200000000>; 1277 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>; 1278 clock-names = "baudclk", "apb_pclk"; 1279 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>; 1280 reset-names = "can", "can-apb"; 1281 status = "disabled"; 1282 }; 1283 1284 rktimer: rktimer@ff660000 { 1285 compatible = "rockchip,rk3288-timer"; 1286 reg = <0xff660000 0x20>; 1287 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1289 clock-names = "pclk", "timer"; 1290 }; 1291 1292 wdt: watchdog@ff680000 { 1293 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; 1294 reg = <0xff680000 0x100>; 1295 clocks = <&cru PCLK_WDT>; 1296 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1297 resets = <&cru SRST_WDT_P>; 1298 reset-names = "reset"; 1299 status = "disabled"; 1300 }; 1301 1302 mailbox: mailbox@ff6a0000 { 1303 compatible = "rockchip,rv1126-mailbox", 1304 "rockchip,rk3368-mailbox"; 1305 reg = <0xff6a0000 0x1000>; 1306 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&cru PCLK_MAILBOX>; 1308 clock-names = "pclk_mailbox"; 1309 #mbox-cells = <1>; 1310 status = "disabled"; 1311 }; 1312 1313 hw_decompress: decompress@ff6c0000 { 1314 compatible = "rockchip,hw-decompress"; 1315 reg = <0xff6c0000 0x1000>; 1316 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1318 clock-names = "aclk", "dclk", "pclk"; 1319 resets = <&cru SRST_DECOM_D>; 1320 reset-names = "dresetn"; 1321 data-cached = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2s0_8ch: i2s@ff800000 { 1326 compatible = "rockchip,rv1126-i2s-tdm"; 1327 reg = <0xff800000 0x1000>; 1328 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>; 1330 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1331 dmas = <&dmac 20>, <&dmac 19>; 1332 dma-names = "tx", "rx"; 1333 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>; 1334 reset-names = "tx-m", "rx-m"; 1335 rockchip,cru = <&cru>; 1336 rockchip,grf = <&grf>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&i2s0m0_sclk_tx 1339 &i2s0m0_sclk_rx 1340 &i2s0m0_lrck_tx 1341 &i2s0m0_lrck_rx 1342 &i2s0m0_sdi0 1343 &i2s0m0_sdo0 1344 &i2s0m0_sdo1_sdi3 1345 &i2s0m0_sdo2_sdi2 1346 &i2s0m0_sdo3_sdi1>; 1347 status = "disabled"; 1348 }; 1349 1350 i2s1_2ch: i2s@ff810000 { 1351 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1352 reg = <0xff810000 0x1000>; 1353 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>; 1355 clock-names = "i2s_clk", "i2s_hclk"; 1356 dmas = <&dmac 22>, <&dmac 21>; 1357 dma-names = "tx", "rx"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&i2s1m0_sclk 1360 &i2s1m0_lrck 1361 &i2s1m0_sdi 1362 &i2s1m0_sdo>; 1363 status = "disabled"; 1364 }; 1365 1366 i2s2_2ch: i2s@ff820000 { 1367 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1368 reg = <0xff820000 0x1000>; 1369 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>; 1371 clock-names = "i2s_clk", "i2s_hclk"; 1372 dmas = <&dmac 24>, <&dmac 23>; 1373 dma-names = "tx", "rx"; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&i2s2m0_sclk 1376 &i2s2m0_lrck 1377 &i2s2m0_sdi 1378 &i2s2m0_sdo>; 1379 status = "disabled"; 1380 }; 1381 1382 pdm: pdm@ff830000 { 1383 compatible = "rockchip,rv1126-pdm", "rockchip,pdm"; 1384 reg = <0xff830000 0x1000>; 1385 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1386 clock-names = "pdm_clk", "pdm_hclk"; 1387 dmas = <&dmac 25>; 1388 dma-names = "rx"; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&pdmm0_clk 1391 &pdmm0_clk1 1392 &pdmm0_sdi0 1393 &pdmm0_sdi1 1394 &pdmm0_sdi2 1395 &pdmm0_sdi3>; 1396 status = "disabled"; 1397 }; 1398 1399 audpwm: audpwm@ff840000 { 1400 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1"; 1401 reg = <0xff840000 0x1000>; 1402 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 1403 clock-names = "clk", "hclk"; 1404 dmas = <&dmac 26>; 1405 dma-names = "tx"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&audpwmm0_pins>; 1408 rockchip,sample-width-bits = <11>; 1409 rockchip,interpolat-points = <1>; 1410 status = "disabled"; 1411 }; 1412 1413 dfi: dfi@ff9c0000 { 1414 reg = <0xff9c0000 0x400>; 1415 compatible = "rockchip,rv1126-dfi"; 1416 rockchip,pmugrf = <&pmugrf>; 1417 status = "disabled"; 1418 }; 1419 1420 dmc: dmc { 1421 compatible = "rockchip,rv1126-dmc"; 1422 devfreq-events = <&dfi>; 1423 clocks = <&cru SCLK_DDRCLK>; 1424 clock-names = "dmc_clk"; 1425 operating-points-v2 = <&dmc_opp_table>; 1426 ddr_timing = <&ddr_timing>; 1427 upthreshold = <40>; 1428 downdifferential = <20>; 1429 system-status-freq = < 1430 /*system status freq(KHz)*/ 1431 SYS_STATUS_NORMAL 924000 1432 SYS_STATUS_REBOOT 450000 1433 SYS_STATUS_SUSPEND 328000 1434 SYS_STATUS_VIDEO_1080P 924000 1435 SYS_STATUS_BOOST 924000 1436 SYS_STATUS_ISP 924000 1437 SYS_STATUS_PERFORMANCE 924000 1438 >; 1439 auto-min-freq = <328000>; 1440 auto-freq-en = <0>; 1441 #cooling-cells = <2>; 1442 status = "disabled"; 1443 }; 1444 1445 dmc_opp_table: dmc-opp-table { 1446 compatible = "operating-points-v2"; 1447 1448 opp-328000000 { 1449 opp-hz = /bits/ 64 <328000000>; 1450 opp-microvolt = <800000>; 1451 }; 1452 opp-450000000 { 1453 opp-hz = /bits/ 64 <450000000>; 1454 opp-microvolt = <800000>; 1455 }; 1456 opp-664000000 { 1457 opp-hz = /bits/ 64 <664000000>; 1458 opp-microvolt = <800000>; 1459 }; 1460 opp-924000000 { 1461 opp-hz = /bits/ 64 <924000000>; 1462 opp-microvolt = <800000>; 1463 }; 1464 opp-1056000000 { 1465 opp-hz = /bits/ 64 <1056000000>; 1466 opp-microvolt = <800000>; 1467 status = "disabled"; 1468 }; 1469 }; 1470 1471 rkcif: rkcif@ffae0000 { 1472 compatible = "rockchip,rv1126-cif"; 1473 reg = <0xffae0000 0x10000>; 1474 reg-names = "cif_regs"; 1475 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1476 interrupt-names = "cif-intr"; 1477 clocks = <&cru ACLK_CIF>, <&cru ACLK_CIFLITE>, 1478 <&cru HCLK_CIF>, <&cru HCLK_CIFLITE>, 1479 <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>; 1480 clock-names = "aclk_cif", "aclk_cif_lite", 1481 "hclk_cif", "hclk_cif_lite", 1482 "dclk_cif", "dclk_cif_lite"; 1483 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, 1484 <&cru SRST_CIF_D>, <&cru SRST_CIF_P>, 1485 <&cru SRST_CIF_I>, <&cru SRST_CIF_RX_P>, 1486 <&cru SRST_CIFLITE_A>, <&cru SRST_CIFLITE_H>, 1487 <&cru SRST_CIFLITE_D>, <&cru SRST_CIFLITE_RX_P>; 1488 reset-names = "rst_cif_a", "rst_cif_h", 1489 "rst_cif_d", "rst_cif_p", 1490 "rst_cif_i", "rst_cif_rx_p", 1491 "rst_cif_lite_a", "rst_cif_lite_h", 1492 "rst_cif_lite_d", "rst_cif_lite_rx_p"; 1493 assigned-clocks = <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>; 1494 assigned-clock-rates = <300000000>, <300000000>; 1495 power-domains = <&power RV1126_PD_VI>; 1496 iommus = <&rkcif_mmu>; 1497 status = "disabled"; 1498 }; 1499 1500 rkcif_mmu: iommu@ffae0800 { 1501 compatible = "rockchip,iommu"; 1502 reg = <0xffae0800 0x100>; 1503 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1504 interrupt-names = "cif_mmu"; 1505 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1506 clock-names = "aclk", "hclk"; 1507 power-domains = <&power RV1126_PD_VI>; 1508 #iommu-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 rk_rga: rk_rga@ffaf0000 { 1513 compatible = "rockchip,rga2"; 1514 reg = <0xffaf0000 0x1000>; 1515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1517 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1518 power-domains = <&power RV1126_PD_VO>; 1519 dma-coherent; 1520 status = "disable"; 1521 }; 1522 1523 vop: vop@ffb00000 { 1524 compatible = "rockchip,rv1126-vop"; 1525 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 1526 reg-names = "regs", "gamma_lut"; 1527 rockchip,grf = <&grf>; 1528 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1529 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1530 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1531 iommus = <&vop_mmu>; 1532 power-domains = <&power RV1126_PD_VO>; 1533 status = "disabled"; 1534 1535 vop_out: port { 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 1539 vop_out_rgb: endpoint@0 { 1540 reg = <0>; 1541 remote-endpoint = <&rgb_in_vop>; 1542 }; 1543 1544 vop_out_dsi: endpoint@1 { 1545 reg = <1>; 1546 remote-endpoint = <&dsi_in_vop>; 1547 }; 1548 }; 1549 }; 1550 1551 vop_mmu: iommu@ffb00f00 { 1552 compatible = "rockchip,iommu"; 1553 reg = <0xffb00f00 0x100>; 1554 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "vop_mmu"; 1556 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1557 clock-names = "aclk", "iface"; 1558 #iommu-cells = <0>; 1559 rockchip,disable-device-link-resume; 1560 power-domains = <&power RV1126_PD_VO>; 1561 status = "disabled"; 1562 }; 1563 1564 mipi_csi2: mipi-csi2@ffb10000 { 1565 compatible = "rockchip,rv1126-mipi-csi2"; 1566 reg = <0xffb10000 0x10000>; 1567 reg-names = "csihost_regs"; 1568 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1570 interrupt-names = "csi-intr1", "csi-intr2"; 1571 clocks = <&cru PCLK_CSIHOST>, <&cru SRST_CSIHOST_P>; 1572 clock-names = "pclk_csi2host", "srst_csihost_p"; 1573 power-domains = <&power RV1126_PD_VI>; 1574 status = "disabled"; 1575 }; 1576 1577 dsi: dsi@ffb30000 { 1578 compatible = "rockchip,rv1126-mipi-dsi"; 1579 reg = <0xffb30000 0x500>; 1580 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>; 1582 clock-names = "pclk", "hs_clk"; 1583 resets = <&cru SRST_DSIHOST_P>; 1584 reset-names = "apb"; 1585 phys = <&mipi_dphy>; 1586 phy-names = "mipi_dphy"; 1587 rockchip,grf = <&grf>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 power-domains = <&power RV1126_PD_VO>; 1591 status = "disabled"; 1592 1593 ports { 1594 port { 1595 dsi_in_vop: endpoint { 1596 remote-endpoint = <&vop_out_dsi>; 1597 }; 1598 }; 1599 }; 1600 }; 1601 1602 rkisp: rkisp@ffb50000 { 1603 compatible = "rockchip,rv1126-rkisp"; 1604 reg = <0xffb50000 0x10000>; 1605 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1608 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1609 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1610 <&cru CLK_ISP>; 1611 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1612 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1613 assigned-clock-rates = <500000000>, <250000000>; 1614 power-domains = <&power RV1126_PD_VI>; 1615 /* iommus = <&rkisp_mmu>; */ 1616 memory-region = <&isp_reserved>; 1617 status = "disabled"; 1618 }; 1619 1620 rkisp_mmu: iommu@ffb51a00 { 1621 compatible = "rockchip,iommu"; 1622 reg = <0xffb51a00 0x100>; 1623 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1624 interrupt-names = "isp_mmu"; 1625 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1626 clock-names = "aclk", "iface"; 1627 power-domains = <&power RV1126_PD_VI>; 1628 #iommu-cells = <0>; 1629 rockchip,disable-mmu-reset; 1630 status = "disabled"; 1631 }; 1632 1633 rkispp: rkispp@ffb60000 { 1634 compatible = "rockchip,rv1126-rkispp"; 1635 reg = <0xffb60000 0x20000>; 1636 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1638 interrupt-names = "ispp_irq", "fec_irq"; 1639 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 1640 <&cru CLK_ISPP>; 1641 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 1642 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 1643 <&cru CLK_ISPP>; 1644 assigned-clock-rates = <500000000>, <250000000>, 1645 <400000000>; 1646 power-domains = <&power RV1126_PD_ISPP>; 1647 iommus = <&rkispp_mmu>; 1648 status = "disabled"; 1649 }; 1650 1651 rkispp_mmu: iommu@ffb60e00 { 1652 compatible = "rockchip,iommu"; 1653 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>; 1654 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1657 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1"; 1658 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>; 1659 clock-names = "aclk", "iface"; 1660 power-domains = <&power RV1126_PD_ISPP>; 1661 #iommu-cells = <0>; 1662 rockchip,disable-mmu-reset; 1663 status = "disabled"; 1664 }; 1665 1666 rkvdec: rkvdec@ffb80000 { 1667 compatible = "rockchip,rkv-decoder-v1"; 1668 reg = <0xffb80000 0x400>; 1669 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1670 interrupt-names = "irq_dec"; 1671 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>, 1672 <&cru CLK_VDEC_CA>, <&cru CLK_VDEC_CORE>, 1673 <&cru CLK_VDEC_HEVC_CA>; 1674 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 1675 "clk_core", "clk_hevc_cabac"; 1676 resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>, 1677 <&cru SRST_VDEC_CA>, <&cru SRST_VDEC_CORE>, 1678 <&cru SRST_VDEC_HEVC_CA>; 1679 reset-names = "video_a", "video_h", "video_cabac", 1680 "video_core", "video_hevc_cabac"; 1681 power-domains = <&power RV1126_PD_VDPU>; 1682 iommus = <&rkvdec_mmu>; 1683 rockchip,srv = <&mpp_srv>; 1684 rockchip,taskqueue-node = <0>; 1685 rockchip,resetgroup-node = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 rkvdec_mmu: iommu@ffb80480 { 1690 compatible = "rockchip,iommu"; 1691 reg = <0xffb80480 0x40>, <0xffb804c0 0x40>; 1692 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1693 interrupt-names = "rkvdec_mmu"; 1694 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>; 1695 clock-names = "aclk", "iface"; 1696 power-domains = <&power RV1126_PD_VDPU>; 1697 #iommu-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 vepu: vepu@ffb90000 { 1702 compatible = "rockchip,vpu-encoder-v2"; 1703 reg = <0xffb90000 0x400>; 1704 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1705 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1706 clock-names = "aclk_vcodec", "hclk_vcodec"; 1707 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 1708 reset-names = "shared_video_a", "shared_video_h"; 1709 iommus = <&vpu_mmu>; 1710 rockchip,srv = <&mpp_srv>; 1711 rockchip,taskqueue-node = <1>; 1712 rockchip,resetgroup-node = <1>; 1713 power-domains = <&power RV1126_PD_VDPU>; 1714 status = "disabled"; 1715 }; 1716 1717 vdpu: vdpu@ffb90400 { 1718 compatible = "rockchip,vpu-decoder-v2"; 1719 reg = <0xffb90400 0x400>; 1720 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1721 interrupt-names = "irq_dec"; 1722 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1723 clock-names = "aclk_vcodec", "hclk_vcodec"; 1724 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 1725 reset-names = "shared_video_a", "shared_video_h"; 1726 iommus = <&vpu_mmu>; 1727 power-domains = <&power RV1126_PD_VDPU>; 1728 rockchip,srv = <&mpp_srv>; 1729 rockchip,taskqueue-node = <1>; 1730 rockchip,resetgroup-node = <1>; 1731 status = "disabled"; 1732 }; 1733 1734 vpu_mmu: iommu@ffb90800 { 1735 compatible = "rockchip,iommu"; 1736 reg = <0xffb90800 0x40>; 1737 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "vpu_mmu"; 1739 clock-names = "aclk", "iface"; 1740 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 1741 power-domains = <&power RV1126_PD_VDPU>; 1742 #iommu-cells = <0>; 1743 status = "disabled"; 1744 }; 1745 1746 rkvenc: rkvenc@ffbb0000 { 1747 compatible = "rockchip,rkv-encoder-v1"; 1748 reg = <0xffbb0000 0x400>; 1749 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1750 interrupt-names = "irq_enc"; 1751 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>, 1752 <&cru CLK_VENC_CORE>; 1753 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1754 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>, 1755 <&cru SRST_VENC_CORE>; 1756 reset-names = "video_a", "video_h", "video_core"; 1757 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>; 1758 assigned-clock-rates = <297000000>, <594000000>; 1759 operating-points-v2 = <&rkvenc_opp_table>; 1760 iommus = <&rkvenc_mmu>; 1761 node-name = "rkvenc"; 1762 rockchip,srv = <&mpp_srv>; 1763 rockchip,taskqueue-node = <2>; 1764 rockchip,resetgroup-node = <2>; 1765 power-domains = <&power RV1126_PD_VEPU>; 1766 status = "disabled"; 1767 }; 1768 1769 rkvenc_opp_table: rkvenc-opp-table { 1770 compatible = "operating-points-v2"; 1771 1772 /* The source clock is CLK_VENC_CORE */ 1773 opp-297000000 { 1774 opp-hz = /bits/ 64 <297000000>; 1775 opp-microvolt = <725000 725000 1000000>; 1776 }; 1777 opp-396000000 { 1778 opp-hz = /bits/ 64 <396000000>; 1779 opp-microvolt = <725000 725000 1000000>; 1780 }; 1781 opp-500000000 { 1782 opp-hz = /bits/ 64 <500000000>; 1783 opp-microvolt = <750000 750000 1000000>; 1784 }; 1785 opp-594000000 { 1786 opp-hz = /bits/ 64 <594000000>; 1787 opp-microvolt = <800000 800000 1000000>; 1788 }; 1789 }; 1790 1791 rkvenc_mmu: iommu@ffbb0f00 { 1792 compatible = "rockchip,iommu"; 1793 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>; 1794 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1796 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1797 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>; 1798 clock-names = "aclk", "iface"; 1799 rockchip,disable-mmu-reset; 1800 #iommu-cells = <0>; 1801 power-domains = <&power RV1126_PD_VEPU>; 1802 status = "disabled"; 1803 }; 1804 1805 pvtm@ffc00000 { 1806 compatible = "rockchip,rv1126-npu-pvtm"; 1807 reg = <0xffc00000 0x100>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 1811 pvtm@1 { 1812 reg = <1>; 1813 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>; 1814 clock-names = "clk", "pclk"; 1815 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>; 1816 reset-names = "rts", "rst-p"; 1817 }; 1818 }; 1819 1820 gmac: ethernet@ffc40000 { 1821 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 1822 reg = <0xffc40000 0x0ffff>; 1823 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1825 interrupt-names = "macirq", "eth_wake_irq"; 1826 rockchip,grf = <&grf>; 1827 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 1828 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 1829 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 1830 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 1831 clock-names = "stmmaceth", "mac_clk_rx", 1832 "mac_clk_tx", "clk_mac_refout", 1833 "aclk_mac", "pclk_mac", 1834 "clk_mac_speed", "ptp_ref"; 1835 resets = <&cru SRST_GMAC_A>; 1836 reset-names = "stmmaceth"; 1837 1838 snps,mixed-burst; 1839 snps,tso; 1840 1841 snps,axi-config = <&stmmac_axi_setup>; 1842 snps,mtl-rx-config = <&mtl_rx_setup>; 1843 snps,mtl-tx-config = <&mtl_tx_setup>; 1844 status = "disabled"; 1845 1846 mdio: mdio { 1847 compatible = "snps,dwmac-mdio"; 1848 #address-cells = <0x1>; 1849 #size-cells = <0x0>; 1850 }; 1851 1852 stmmac_axi_setup: stmmac-axi-config { 1853 snps,wr_osr_lmt = <4>; 1854 snps,rd_osr_lmt = <8>; 1855 snps,blen = <0 0 0 0 16 8 4>; 1856 }; 1857 1858 mtl_rx_setup: rx-queues-config { 1859 snps,rx-queues-to-use = <1>; 1860 queue0 {}; 1861 }; 1862 1863 mtl_tx_setup: tx-queues-config { 1864 snps,tx-queues-to-use = <1>; 1865 queue0 {}; 1866 }; 1867 }; 1868 1869 emmc: dwmmc@ffc50000 { 1870 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1871 reg = <0xffc50000 0x4000>; 1872 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1873 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 1874 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1875 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1876 fifo-depth = <0x100>; 1877 max-frequency = <200000000>; 1878 pinctrl-names = "default"; 1879 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1880 power-domains = <&power RV1126_PD_NVM>; 1881 rockchip,use-v2-tuning; 1882 status = "disabled"; 1883 }; 1884 1885 sdmmc: dwmmc@ffc60000 { 1886 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1887 reg = <0xffc60000 0x4000>; 1888 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1889 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 1890 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1891 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1892 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 1893 fifo-depth = <0x100>; 1894 max-frequency = <200000000>; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 1897 status = "disabled"; 1898 }; 1899 1900 sdio: dwmmc@ffc70000 { 1901 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1902 reg = <0xffc70000 0x4000>; 1903 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 1905 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1906 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1907 fifo-depth = <0x100>; 1908 max-frequency = <200000000>; 1909 pinctrl-names = "default"; 1910 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1911 power-domains = <&power RV1126_PD_SDIO>; 1912 status = "disabled"; 1913 }; 1914 1915 nandc: nandc@ffc80000 { 1916 compatible = "rockchip,rk-nandc"; 1917 reg = <0xffc80000 0x4000>; 1918 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1919 nandc_id = <0>; 1920 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>; 1921 clock-names = "clk_nandc", "hclk_nandc"; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&flash_pins>; 1924 power-domains = <&power RV1126_PD_NVM>; 1925 status = "disabled"; 1926 }; 1927 1928 sfc: sfc@ffc90000 { 1929 compatible = "rockchip,sfc"; 1930 reg = <0xffc90000 0x4000>; 1931 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1932 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1933 clock-names = "clk_sfc", "hclk_sfc"; 1934 pinctrl-names = "default"; 1935 pinctrl-0 = <&flash_pins>; 1936 assigned-clocks = <&cru SCLK_SFC>; 1937 assigned-clock-rates = <80000000>; 1938 power-domains = <&power RV1126_PD_NVM>; 1939 status = "disabled"; 1940 }; 1941 1942 npu: npu@ffbc0000 { 1943 compatible = "rockchip,npu"; 1944 reg = <0xffbc0000 0x4000>; 1945 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, <&cru PCLK_PDNPU>, <&cru CLK_CORE_NPU>; 1946 clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu"; 1947 assigned-clocks = <&cru CLK_CORE_NPU>; 1948 assigned-clock-rates = <396000000>; 1949 operating-points-v2 = <&npu_opp_table>; 1950 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1951 power-domains = <&power RV1126_PD_NPU>; 1952 status = "disabled"; 1953 }; 1954 1955 npu_opp_table: npu-opp-table { 1956 compatible = "operating-points-v2"; 1957 1958 opp-200000000 { 1959 opp-hz = /bits/ 64 <200000000>; 1960 opp-microvolt = <725000 725000 1000000>; 1961 }; 1962 opp-300000000 { 1963 opp-hz = /bits/ 64 <300000000>; 1964 opp-microvolt = <725000 725000 1000000>; 1965 }; 1966 opp-396000000 { 1967 opp-hz = /bits/ 64 <396000000>; 1968 opp-microvolt = <725000 725000 1000000>; 1969 }; 1970 opp-500000000 { 1971 opp-hz = /bits/ 64 <500000000>; 1972 opp-microvolt = <725000 725000 1000000>; 1973 }; 1974 opp-600000000 { 1975 opp-hz = /bits/ 64 <600000000>; 1976 opp-microvolt = <725000 725000 1000000>; 1977 }; 1978 opp-700000000 { 1979 opp-hz = /bits/ 64 <700000000>; 1980 opp-microvolt = <775000 775000 1000000>; 1981 }; 1982 opp-800000000 { 1983 opp-hz = /bits/ 64 <800000000>; 1984 opp-microvolt = <825000 825000 1000000>; 1985 }; 1986 }; 1987 1988 usbdrd: usb0 { 1989 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3"; 1990 #address-cells = <1>; 1991 #size-cells = <1>; 1992 ranges; 1993 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>, 1994 <&cru HCLK_PDUSB>; 1995 clock-names = "ref_clk", "bus_clk", "hclk"; 1996 status = "disabled"; 1997 1998 usbdrd_dwc3: dwc3@ffd00000 { 1999 compatible = "snps,dwc3"; 2000 reg = <0xffd00000 0x100000>; 2001 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2002 dr_mode = "otg"; 2003 maximum-speed = "high-speed"; 2004 phys = <&u2phy_otg>; 2005 phy-names = "usb2-phy"; 2006 phy_type = "utmi_wide"; 2007 power-domains = <&power RV1126_PD_USB>; 2008 resets = <&cru SRST_USBOTG_A>; 2009 reset-names = "usb3-otg"; 2010 snps,dis_enblslpm_quirk; 2011 snps,dis-u2-freeclk-exists-quirk; 2012 snps,dis_u2_susphy_quirk; 2013 snps,dis-del-phy-power-chg-quirk; 2014 snps,tx-ipgap-linecheck-dis-quirk; 2015 snps,xhci-trb-ent-quirk; 2016 status = "disabled"; 2017 }; 2018 }; 2019 2020 usb_host0_ehci: usb@ffe00000 { 2021 compatible = "generic-ehci"; 2022 reg = <0xffe00000 0x10000>; 2023 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2024 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2025 <&u2phy1>; 2026 clock-names = "usbhost", "arbiter", "utmi"; 2027 phys = <&u2phy_host>; 2028 phy-names = "usb"; 2029 power-domains = <&power RV1126_PD_USB>; 2030 status = "disabled"; 2031 }; 2032 2033 usb_host0_ohci: usb@ffe10000 { 2034 compatible = "generic-ohci"; 2035 reg = <0xffe10000 0x10000>; 2036 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2037 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2038 <&u2phy1>; 2039 clock-names = "usbhost", "arbiter", "utmi"; 2040 phys = <&u2phy_host>; 2041 phy-names = "usb"; 2042 power-domains = <&power RV1126_PD_USB>; 2043 status = "disabled"; 2044 }; 2045 2046 pinctrl: pinctrl { 2047 compatible = "rockchip,rv1126-pinctrl"; 2048 rockchip,grf = <&grf>; 2049 rockchip,pmu = <&pmugrf>; 2050 #address-cells = <1>; 2051 #size-cells = <1>; 2052 ranges; 2053 2054 gpio0: gpio0@ff460000 { 2055 compatible = "rockchip,gpio-bank"; 2056 reg = <0xff460000 0x100>; 2057 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2058 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 2059 2060 gpio-controller; 2061 #gpio-cells = <2>; 2062 2063 interrupt-controller; 2064 #interrupt-cells = <2>; 2065 }; 2066 2067 gpio1: gpio1@ff620000 { 2068 compatible = "rockchip,gpio-bank"; 2069 reg = <0xff620000 0x100>; 2070 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2071 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2072 2073 gpio-controller; 2074 #gpio-cells = <2>; 2075 2076 interrupt-controller; 2077 #interrupt-cells = <2>; 2078 }; 2079 2080 gpio2: gpio2@ff630000 { 2081 compatible = "rockchip,gpio-bank"; 2082 reg = <0xff630000 0x100>; 2083 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2084 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2085 2086 gpio-controller; 2087 #gpio-cells = <2>; 2088 2089 interrupt-controller; 2090 #interrupt-cells = <2>; 2091 }; 2092 2093 gpio3: gpio3@ff640000 { 2094 compatible = "rockchip,gpio-bank"; 2095 reg = <0xff640000 0x100>; 2096 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2097 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2098 2099 gpio-controller; 2100 #gpio-cells = <2>; 2101 2102 interrupt-controller; 2103 #interrupt-cells = <2>; 2104 }; 2105 2106 gpio4: gpio4@ff650000 { 2107 compatible = "rockchip,gpio-bank"; 2108 reg = <0xff650000 0x100>; 2109 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2110 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2111 2112 gpio-controller; 2113 #gpio-cells = <2>; 2114 2115 interrupt-controller; 2116 #interrupt-cells = <2>; 2117 }; 2118 }; 2119}; 2120 2121#include "rv1126-pinctrl.dtsi" 2122 2123
