1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rv1126-cru.h> 7#include <dt-bindings/power/rv1126-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rv1126.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "rv1126-dram-default-timing.dtsi" 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 compatible = "rockchip,rv1126"; 23 24 interrupt-parent = <&gic>; 25 26 aliases { 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 mmc0 = &emmc; 34 mmc1 = &sdmmc; 35 mmc2 = &sdio; 36 serial0 = &uart0; 37 serial1 = &uart1; 38 serial2 = &uart2; 39 serial3 = &uart3; 40 serial4 = &uart4; 41 serial5 = &uart5; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 dphy0 = &csi_dphy0; 45 dphy1 = &csi_dphy1; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu0: cpu@f00 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0xf00>; 56 enable-method = "psci"; 57 clocks = <&cru ARMCLK>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 dynamic-power-coefficient = <60>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP>; 62 }; 63 64 cpu1: cpu@f01 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a7"; 67 reg = <0xf01>; 68 enable-method = "psci"; 69 clocks = <&cru ARMCLK>; 70 operating-points-v2 = <&cpu0_opp_table>; 71 dynamic-power-coefficient = <60>; 72 cpu-idle-states = <&CPU_SLEEP>; 73 }; 74 75 cpu2: cpu@f02 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a7"; 78 reg = <0xf02>; 79 enable-method = "psci"; 80 clocks = <&cru ARMCLK>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 dynamic-power-coefficient = <60>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 }; 85 86 cpu3: cpu@f03 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a7"; 89 reg = <0xf03>; 90 enable-method = "psci"; 91 clocks = <&cru ARMCLK>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 dynamic-power-coefficient = <60>; 94 cpu-idle-states = <&CPU_SLEEP>; 95 }; 96 97 idle-states { 98 entry-method = "psci"; 99 100 CPU_SLEEP: cpu-sleep { 101 compatible = "arm,idle-state"; 102 local-timer-stop; 103 arm,psci-suspend-param = <0x0010000>; 104 entry-latency-us = <120>; 105 exit-latency-us = <250>; 106 min-residency-us = <900>; 107 }; 108 }; 109 110 }; 111 112 cpu0_opp_table: cpu0-opp-table { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 nvmem-cells = <&cpu_leakage>, <&cpu_performance>; 117 nvmem-cell-names = "leakage", "performance"; 118 119 rockchip,reboot-freq = <816000>; 120 121 rockchip,temp-freq-table = < 122 100000 1296000 123 >; 124 125 clocks = <&cru PLL_APLL>; 126 rockchip,bin-scaling-sel = < 127 0 5 128 1 9 129 >; 130 rockchip,bin-voltage-sel = < 131 1 0 132 >; 133 rockchip,pvtm-voltage-sel = < 134 0 100500 1 135 100501 104500 2 136 104501 109500 3 137 109501 999999 4 138 >; 139 rockchip,pvtm-freq = <408000>; 140 rockchip,pvtm-volt = <800000>; 141 rockchip,pvtm-ch = <0 0>; 142 rockchip,pvtm-sample-time = <1000>; 143 rockchip,pvtm-number = <10>; 144 rockchip,pvtm-error = <1000>; 145 rockchip,pvtm-ref-temp = <37>; 146 rockchip,pvtm-temp-prop = <(-40) 13>; 147 rockchip,pvtm-thermal-zone = "cpu-thermal"; 148 149 opp-408000000 { 150 opp-hz = /bits/ 64 <408000000>; 151 opp-microvolt = <725000 725000 1000000>; 152 opp-microvolt-L0 = <725000 725000 1000000>; 153 clock-latency-ns = <40000>; 154 }; 155 opp-600000000 { 156 opp-hz = /bits/ 64 <600000000>; 157 opp-microvolt = <725000 725000 1000000>; 158 opp-microvolt-L0 = <725000 725000 1000000>; 159 clock-latency-ns = <40000>; 160 }; 161 opp-816000000 { 162 opp-hz = /bits/ 64 <816000000>; 163 opp-microvolt = <725000 725000 1000000>; 164 opp-microvolt-L0 = <750000 750000 1000000>; 165 clock-latency-ns = <40000>; 166 opp-suspend; 167 }; 168 opp-1008000000 { 169 opp-hz = /bits/ 64 <1008000000>; 170 opp-microvolt = <775000 775000 1000000>; 171 opp-microvolt-L0 = <800000 800000 1000000>; 172 opp-microvolt-L1 = <775000 775000 1000000>; 173 opp-microvolt-L2 = <775000 775000 1000000>; 174 opp-microvolt-L3 = <750000 750000 1000000>; 175 opp-microvolt-L4 = <725000 725000 1000000>; 176 clock-latency-ns = <40000>; 177 }; 178 opp-1200000000 { 179 opp-hz = /bits/ 64 <1200000000>; 180 opp-microvolt = <850000 850000 1000000>; 181 opp-microvolt-L0 = <875000 875000 1000000>; 182 opp-microvolt-L1 = <850000 850000 1000000>; 183 opp-microvolt-L2 = <850000 850000 1000000>; 184 opp-microvolt-L3 = <825000 825000 1000000>; 185 opp-microvolt-L4 = <800000 800000 1000000>; 186 clock-latency-ns = <40000>; 187 }; 188 opp-1296000000 { 189 opp-hz = /bits/ 64 <1296000000>; 190 opp-microvolt = <875000 875000 1000000>; 191 opp-microvolt-L0 = <925000 925000 1000000>; 192 opp-microvolt-L1 = <875000 875000 1000000>; 193 opp-microvolt-L2 = <875000 875000 1000000>; 194 opp-microvolt-L3 = <850000 850000 1000000>; 195 opp-microvolt-L4 = <825000 825000 1000000>; 196 clock-latency-ns = <40000>; 197 }; 198 opp-1416000000 { 199 opp-hz = /bits/ 64 <1416000000>; 200 opp-microvolt = <925000 925000 1000000>; 201 opp-microvolt-L0 = <975000 975000 1000000>; 202 opp-microvolt-L1 = <925000 925000 1000000>; 203 opp-microvolt-L2 = <925000 925000 1000000>; 204 opp-microvolt-L3 = <900000 900000 1000000>; 205 opp-microvolt-L4 = <875000 875000 1000000>; 206 clock-latency-ns = <40000>; 207 }; 208 opp-1512000000 { 209 opp-hz = /bits/ 64 <1512000000>; 210 opp-microvolt = <975000 975000 1000000>; 211 opp-microvolt-L1 = <975000 975000 1000000>; 212 opp-microvolt-L2 = <950000 950000 1000000>; 213 opp-microvolt-L3 = <925000 925000 1000000>; 214 opp-microvolt-L4 = <900000 900000 1000000>; 215 clock-latency-ns = <40000>; 216 }; 217 }; 218 219 cpuinfo { 220 compatible = "rockchip,cpuinfo"; 221 nvmem-cells = <&otp_id>, <&otp_cpu_code>; 222 nvmem-cell-names = "id", "cpu-code"; 223 }; 224 225 arm-pmu { 226 compatible = "arm,cortex-a7-pmu"; 227 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 232 }; 233 234 bus_soc: bus-soc { 235 compatible = "rockchip,rv1126-bus"; 236 rockchip,busfreq-policy = "smc"; 237 soc-bus0 { 238 bus-id = <0>; 239 cfg-val = <0x00300020>; 240 enable-msk = <0x7144>; 241 status = "okay"; 242 }; 243 soc-bus1 { 244 bus-id = <1>; 245 cfg-val = <0x00300020>; 246 enable-msk = <0x70ff>; 247 status = "disabled"; 248 }; 249 soc-bus2 { 250 bus-id = <2>; 251 cfg-val = <0x00300020>; 252 enable-msk = <0x70ff>; 253 status = "disabled"; 254 }; 255 soc-bus3 { 256 bus-id = <3>; 257 cfg-val = <0x00300020>; 258 enable-msk = <0x70ff>; 259 status = "disabled"; 260 }; 261 soc-bus4 { 262 bus-id = <4>; 263 cfg-val = <0x00300020>; 264 enable-msk = <0x7011>; 265 status = "disabled"; 266 }; 267 soc-bus5 { 268 bus-id = <5>; 269 cfg-val = <0x00300020>; 270 enable-msk = <0x7011>; 271 status = "disabled"; 272 }; 273 soc-bus6 { 274 bus-id = <6>; 275 cfg-val = <0x00300020>; 276 enable-msk = <0x7011>; 277 status = "disabled"; 278 }; 279 soc-bus7 { 280 bus-id = <7>; 281 cfg-val = <0x00300020>; 282 enable-msk = <0x0>; 283 status = "disabled"; 284 }; 285 soc-bus8 { 286 bus-id = <8>; 287 cfg-val = <0x00300020>; 288 enable-msk = <0x0>; 289 status = "disabled"; 290 }; 291 soc-bus9 { 292 bus-id = <9>; 293 cfg-val = <0x00300020>; 294 enable-msk = <0x0>; 295 status = "disabled"; 296 }; 297 soc-bus10 { 298 bus-id = <10>; 299 cfg-val = <0x00300020>; 300 enable-msk = <0x0>; 301 status = "disabled"; 302 }; 303 soc-bus11 { 304 bus-id = <11>; 305 cfg-val = <0x00300020>; 306 enable-msk = <0x7000>; 307 status = "disabled"; 308 }; 309 }; 310 311 display_subsystem: display-subsystem { 312 compatible = "rockchip,display-subsystem"; 313 ports = <&vop_out>; 314 status = "disabled"; 315 logo-memory-region = <&drm_logo>; 316 317 route { 318 route_dsi: route-dsi { 319 status = "disabled"; 320 logo,uboot = "logo.bmp"; 321 logo,kernel = "logo_kernel.bmp"; 322 logo,mode = "center"; 323 charge_logo,mode = "center"; 324 connect = <&vop_out_dsi>; 325 }; 326 327 route_rgb: route-rgb { 328 status = "disabled"; 329 logo,uboot = "logo.bmp"; 330 logo,kernel = "logo_kernel.bmp"; 331 logo,mode = "center"; 332 charge_logo,mode = "center"; 333 connect = <&vop_out_rgb>; 334 }; 335 }; 336 }; 337 338 fiq_debugger: fiq-debugger { 339 compatible = "rockchip,fiq-debugger"; 340 rockchip,serial-id = <2>; 341 rockchip,wake-irq = <0>; 342 rockchip,irq-mode-enable = <0>; 343 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 344 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 345 status = "disabled"; 346 }; 347 348 firmware { 349 optee: optee { 350 compatible = "linaro,optee-tz"; 351 method = "smc"; 352 status = "disabled"; 353 }; 354 }; 355 356 mipi_csi2: mipi-csi2 { 357 compatible = "rockchip,rv1126-mipi-csi2"; 358 rockchip,hw = <&mipi_csi2_hw>; 359 status = "disabled"; 360 }; 361 362 mpp_srv: mpp-srv { 363 compatible = "rockchip,mpp-service"; 364 rockchip,taskqueue-count = <4>; 365 rockchip,resetgroup-count = <4>; 366 status = "disabled"; 367 }; 368 369 psci { 370 compatible = "arm,psci-1.0"; 371 method = "smc"; 372 }; 373 374 reserved-memory { 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges; 378 379 linux,cma { 380 compatible = "shared-dma-pool"; 381 inactive; 382 reusable; 383 size = <0x800000>; 384 linux,cma-default; 385 }; 386 387 drm_logo: drm-logo@00000000 { 388 compatible = "rockchip,drm-logo"; 389 reg = <0x0 0x0>; 390 }; 391 392 isp_reserved: isp { 393 compatible = "shared-dma-pool"; 394 inactive; 395 reusable; 396 size = <0x10000000>; 397 }; 398 399 ramoops: ramoops@8000000 { 400 compatible = "ramoops"; 401 reg = <0x8000000 0x100000>; 402 record-size = <0x20000>; 403 console-size = <0x40000>; 404 ftrace-size = <0x00000>; 405 pmsg-size = <0x40000>; 406 status = "disabled"; 407 }; 408 }; 409 410 rkcif_dvp: rkcif_dvp { 411 compatible = "rockchip,rkcif-dvp"; 412 rockchip,hw = <&rkcif>; 413 // iommus = <&rkcif_mmu>; 414 memory-region = <&isp_reserved>; 415 status = "disabled"; 416 }; 417 418 rkcif_dvp_sditf: rkcif_dvp_sditf { 419 compatible = "rockchip,rkcif-sditf"; 420 rockchip,cif = <&rkcif_dvp>; 421 status = "disabled"; 422 }; 423 424 rkcif_lite_mipi_lvds: rkcif_lite_mipi_lvds { 425 compatible = "rockchip,rkcif-mipi-lvds"; 426 rockchip,hw = <&rkcif_lite>; 427 iommus = <&rkcif_lite_mmu>; 428 status = "disabled"; 429 }; 430 431 rkcif_lite_sditf: rkcif_lite_sditf { 432 compatible = "rockchip,rkcif-sditf"; 433 rockchip,cif = <&rkcif_lite_mipi_lvds>; 434 status = "disabled"; 435 }; 436 437 rkcif_mipi_lvds: rkcif_mipi_lvds { 438 compatible = "rockchip,rkcif-mipi-lvds"; 439 rockchip,hw = <&rkcif>; 440 // iommus = <&rkcif_mmu>; 441 memory-region = <&isp_reserved>; 442 status = "disabled"; 443 }; 444 445 rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { 446 compatible = "rockchip,rkcif-sditf"; 447 rockchip,cif = <&rkcif_mipi_lvds>; 448 status = "disabled"; 449 }; 450 451 rockchip_suspend: rockchip-suspend { 452 compatible = "rockchip,pm-rv1126"; 453 status = "disabled"; 454 rockchip,sleep-debug-en = <0>; 455 rockchip,sleep-mode-config = < 456 (0 457 | RKPM_SLP_ARMOFF 458 | RKPM_SLP_PMU_PMUALIVE_32K 459 | RKPM_SLP_PMU_DIS_OSC 460 | RKPM_SLP_PMIC_LP 461 ) 462 >; 463 rockchip,wakeup-config = < 464 (0 465 | RKPM_GPIO_WKUP_EN 466 ) 467 >; 468 }; 469 470 rockchip_system_monitor: rockchip-system-monitor { 471 compatible = "rockchip,system-monitor"; 472 }; 473 474 thermal_zones: thermal-zones { 475 cpu_thermal: cpu-thermal { 476 polling-delay-passive = <20>; /* milliseconds */ 477 polling-delay = <1000>; /* milliseconds */ 478 sustainable-power = <875>; /* milliwatts */ 479 k_pu = <75>; 480 k_po = <175>; 481 k_i = <0>; 482 483 thermal-sensors = <&cpu_tsadc 0>; 484 485 trips { 486 threshold: trip-point-0 { 487 /* millicelsius */ 488 temperature = <75000>; 489 /* millicelsius */ 490 hysteresis = <2000>; 491 type = "passive"; 492 }; 493 target: trip-point-1 { 494 /* millicelsius */ 495 temperature = <85000>; 496 /* millicelsius */ 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 soc_crit: soc-crit { 501 /* millicelsius */ 502 temperature = <115000>; 503 /* millicelsius */ 504 hysteresis = <2000>; 505 type = "critical"; 506 }; 507 }; 508 509 cooling-maps { 510 map0 { 511 trip = <&target>; 512 cooling-device = 513 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 514 contribution = <1024>; 515 }; 516 map1 { 517 trip = <&target>; 518 cooling-device = 519 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 520 contribution = <1024>; 521 }; 522 map2 { 523 trip = <&target>; 524 cooling-device = 525 <&rkvenc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 526 contribution = <1060>; 527 }; 528 }; 529 }; 530 531 npu_thermal: npu-thermal { 532 polling-delay-passive = <20>; /* milliseconds */ 533 polling-delay = <1000>; /* milliseconds */ 534 sustainable-power = <977>; /* milliwatts */ 535 536 thermal-sensors = <&npu_tsadc 0>; 537 }; 538 }; 539 540 timer { 541 compatible = "arm,armv7-timer"; 542 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 543 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 544 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 545 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 546 clock-frequency = <24000000>; 547 }; 548 549 xin24m: oscillator { 550 compatible = "fixed-clock"; 551 clock-frequency = <24000000>; 552 clock-output-names = "xin24m"; 553 #clock-cells = <0>; 554 }; 555 556 dummy_cpll: dummy_cpll { 557 compatible = "fixed-clock"; 558 clock-frequency = <0>; 559 clock-output-names = "dummy_cpll"; 560 #clock-cells = <0>; 561 }; 562 563 gmac_clkin_m0: external-gmac-clockm0 { 564 compatible = "fixed-clock"; 565 clock-frequency = <125000000>; 566 clock-output-names = "clk_gmac_rgmii_clkin_m0"; 567 #clock-cells = <0>; 568 }; 569 570 gmac_clkini_m1: external-gmac-clockm1 { 571 compatible = "fixed-clock"; 572 clock-frequency = <125000000>; 573 clock-output-names = "clk_gmac_rgmii_clkin_m1"; 574 #clock-cells = <0>; 575 }; 576 577 grf: syscon@fe000000 { 578 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 579 reg = <0xfe000000 0x20000>; 580 581 rgb: rgb { 582 compatible = "rockchip,rv1126-rgb"; 583 status = "disabled"; 584 585 ports { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 589 port@0 { 590 reg = <0>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 rgb_in_vop: endpoint@0 { 595 reg = <0>; 596 remote-endpoint = <&vop_out_rgb>; 597 }; 598 }; 599 600 }; 601 }; 602 }; 603 604 pmugrf: syscon@fe020000 { 605 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 606 reg = <0xfe020000 0x1000>; 607 608 pmu_io_domains: io-domains { 609 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 610 }; 611 612 reboot-mode { 613 compatible = "syscon-reboot-mode"; 614 offset = <0x200>; 615 mode-bootloader = <BOOT_BL_DOWNLOAD>; 616 mode-charge = <BOOT_CHARGING>; 617 mode-fastboot = <BOOT_FASTBOOT>; 618 mode-loader = <BOOT_BL_DOWNLOAD>; 619 mode-normal = <BOOT_NORMAL>; 620 mode-recovery = <BOOT_RECOVERY>; 621 mode-ums = <BOOT_UMS>; 622 mode-panic = <BOOT_PANIC>; 623 mode-watchdog = <BOOT_WATCHDOG>; 624 }; 625 }; 626 627 qos_usb_host: qos@fe810000 { 628 compatible = "syscon"; 629 reg = <0xfe810000 0x20>; 630 }; 631 632 qos_usb_otg: qos@fe810080 { 633 compatible = "syscon"; 634 reg = <0xfe810080 0x20>; 635 }; 636 637 qos_npu: qos@fe850000 { 638 compatible = "syscon"; 639 reg = <0xfe850000 0x20>; 640 }; 641 642 qos_emmc: qos@fe860000 { 643 compatible = "syscon"; 644 reg = <0xfe860000 0x20>; 645 }; 646 647 qos_nandc: qos@fe860080 { 648 compatible = "syscon"; 649 reg = <0xfe860080 0x20>; 650 }; 651 652 qos_sfc: qos@fe860200 { 653 compatible = "syscon"; 654 reg = <0xfe860200 0x20>; 655 }; 656 657 qos_sdio: qos@fe86c000 { 658 compatible = "syscon"; 659 reg = <0xfe86c000 0x20>; 660 }; 661 662 qos_vepu_rd0: qos@fe870000 { 663 compatible = "syscon"; 664 reg = <0xfe870000 0x20>; 665 }; 666 667 qos_vepu_rd1: qos@fe870080 { 668 compatible = "syscon"; 669 reg = <0xfe870080 0x20>; 670 }; 671 672 qos_vepu_wr: qos@fe870100 { 673 compatible = "syscon"; 674 reg = <0xfe870100 0x20>; 675 }; 676 677 qos_ispp_m0: qos@fe880000 { 678 compatible = "syscon"; 679 reg = <0xfe880000 0x20>; 680 }; 681 682 qos_ispp_m1: qos@fe880080 { 683 compatible = "syscon"; 684 reg = <0xfe880080 0x20>; 685 }; 686 687 qos_isp: qos@fe890000 { 688 compatible = "syscon"; 689 reg = <0xfe890000 0x20>; 690 }; 691 692 qos_cif_lite: qos@fe890080 { 693 compatible = "syscon"; 694 reg = <0xfe890080 0x20>; 695 }; 696 697 qos_cif: qos@fe890100 { 698 compatible = "syscon"; 699 reg = <0xfe890100 0x20>; 700 }; 701 702 qos_iep: qos@fe8a0000 { 703 compatible = "syscon"; 704 reg = <0xfe8a0000 0x20>; 705 }; 706 707 qos_rga_rd: qos@fe8a0080 { 708 compatible = "syscon"; 709 reg = <0xfe8a0080 0x20>; 710 }; 711 712 qos_rga_wr: qos@fe8a0100 { 713 compatible = "syscon"; 714 reg = <0xfe8a0100 0x20>; 715 }; 716 717 qos_vop: qos@fe8a0180 { 718 compatible = "syscon"; 719 reg = <0xfe8a0180 0x20>; 720 }; 721 722 qos_vdpu: qos@fe8b0000 { 723 compatible = "syscon"; 724 reg = <0xfe8b0000 0x20>; 725 }; 726 727 qos_jpeg: qos@fe8c0000 { 728 compatible = "syscon"; 729 reg = <0xfe8c0000 0x20>; 730 }; 731 732 qos_crypto: qos@fe8d0000 { 733 compatible = "syscon"; 734 reg = <0xfe8d0000 0x20>; 735 }; 736 737 gic: interrupt-controller@feff0000 { 738 compatible = "arm,gic-400"; 739 interrupt-controller; 740 #interrupt-cells = <3>; 741 #address-cells = <0>; 742 743 reg = <0xfeff1000 0x1000>, 744 <0xfeff2000 0x2000>, 745 <0xfeff4000 0x2000>, 746 <0xfeff6000 0x2000>; 747 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 748 }; 749 750 arm-debug@ff010000 { 751 compatible = "rockchip,debug"; 752 reg = <0xff010000 0x1000>, 753 <0xff012000 0x1000>, 754 <0xff014000 0x1000>, 755 <0xff016000 0x1000>; 756 }; 757 758 pvtm@ff040000 { 759 compatible = "rockchip,rv1126-cpu-pvtm"; 760 reg = <0xff040000 0x100>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 764 pvtm@0 { 765 reg = <0>; 766 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>; 767 clock-names = "clk", "pclk"; 768 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>; 769 reset-names = "rst", "rst-p"; 770 }; 771 }; 772 773 pmu: power-management@ff3e0000 { 774 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 775 reg = <0xff3e0000 0x1000>; 776 777 power: power-controller { 778 compatible = "rockchip,rv1126-power-controller"; 779 #power-domain-cells = <1>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 status = "okay"; 783 784 /* These power domains are grouped by VD_NPU */ 785 pd_npu@RV1126_PD_NPU { 786 reg = <RV1126_PD_NPU>; 787 clocks = <&cru ACLK_NPU>, 788 <&cru HCLK_NPU>, 789 <&cru PCLK_PDNPU>, 790 <&cru CLK_CORE_NPU>; 791 pm_qos = <&qos_npu>; 792 }; 793 /* These power domains are grouped by VD_VEPU */ 794 pd_vepu@RV1126_PD_VEPU { 795 reg = <RV1126_PD_VEPU>; 796 clocks = <&cru ACLK_VENC>, 797 <&cru HCLK_VENC>, 798 <&cru CLK_VENC_CORE>; 799 pm_qos = <&qos_vepu_rd0>, 800 <&qos_vepu_rd1>, 801 <&qos_vepu_wr>; 802 }; 803 /* These power domains are grouped by VD_LOGIC */ 804 pd_crypto@RV1126_PD_CRYPTO { 805 reg = <RV1126_PD_CRYPTO>; 806 clocks = <&cru ACLK_CRYPTO>, 807 <&cru HCLK_CRYPTO>, 808 <&cru CLK_CRYPTO_CORE>, 809 <&cru CLK_CRYPTO_PKA>; 810 pm_qos = <&qos_crypto>; 811 }; 812 pd_vi@RV1126_PD_VI { 813 reg = <RV1126_PD_VI>; 814 clocks = <&cru ACLK_ISP>, 815 <&cru HCLK_ISP>, 816 <&cru CLK_ISP>, 817 <&cru ACLK_CIF>, 818 <&cru HCLK_CIF>, 819 <&cru DCLK_CIF>, 820 <&cru CLK_CIF_OUT>, 821 <&cru CLK_MIPICSI_OUT>, 822 <&cru PCLK_CSIHOST>, 823 <&cru ACLK_CIFLITE>, 824 <&cru HCLK_CIFLITE>, 825 <&cru DCLK_CIFLITE>; 826 pm_qos = <&qos_isp>, 827 <&qos_cif_lite>, 828 <&qos_cif>; 829 }; 830 pd_vo@RV1126_PD_VO { 831 reg = <RV1126_PD_VO>; 832 clocks = <&cru ACLK_RGA>, 833 <&cru HCLK_RGA>, 834 <&cru CLK_RGA_CORE>, 835 <&cru ACLK_VOP>, 836 <&cru HCLK_VOP>, 837 <&cru DCLK_VOP>, 838 <&cru PCLK_DSIHOST>, 839 <&cru ACLK_IEP>, 840 <&cru HCLK_IEP>, 841 <&cru CLK_IEP_CORE>; 842 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 843 <&qos_vop>, <&qos_iep>; 844 }; 845 pd_ispp@RV1126_PD_ISPP { 846 reg = <RV1126_PD_ISPP>; 847 clocks = <&cru ACLK_ISPP>, 848 <&cru HCLK_ISPP>, 849 <&cru CLK_ISPP>; 850 pm_qos = <&qos_ispp_m0>, 851 <&qos_ispp_m1>; 852 }; 853 pd_vdpu@RV1126_PD_VDPU { 854 reg = <RV1126_PD_VDPU>; 855 clocks = <&cru ACLK_VDEC>, 856 <&cru HCLK_VDEC>, 857 <&cru CLK_VDEC_CORE>, 858 <&cru CLK_VDEC_CA>, 859 <&cru CLK_VDEC_HEVC_CA>, 860 <&cru ACLK_JPEG>, 861 <&cru HCLK_JPEG>; 862 pm_qos = <&qos_vdpu>, 863 <&qos_jpeg>; 864 }; 865 pd_nvm@RV1126_PD_NVM { 866 reg = <RV1126_PD_NVM>; 867 clocks = <&cru HCLK_EMMC>, 868 <&cru CLK_EMMC>, 869 <&cru HCLK_NANDC>, 870 <&cru CLK_NANDC>, 871 <&cru HCLK_SFC>, 872 <&cru HCLK_SFCXIP>, 873 <&cru SCLK_SFC>; 874 pm_qos = <&qos_emmc>, 875 <&qos_nandc>, 876 <&qos_sfc>; 877 }; 878 pd_sdio@RV1126_PD_SDIO { 879 reg = <RV1126_PD_SDIO>; 880 clocks = <&cru HCLK_SDIO>, 881 <&cru CLK_SDIO>; 882 pm_qos = <&qos_sdio>; 883 }; 884 pd_usb@RV1126_PD_USB { 885 reg = <RV1126_PD_USB>; 886 clocks = <&cru HCLK_USBHOST>, 887 <&cru HCLK_USBHOST_ARB>, 888 <&cru CLK_USBHOST_UTMI_OHCI>, 889 <&cru ACLK_USBOTG>, 890 <&cru CLK_USBOTG_REF>; 891 pm_qos = <&qos_usb_host>, 892 <&qos_usb_otg>; 893 }; 894 }; 895 }; 896 897 i2c0: i2c@ff3f0000 { 898 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 899 reg = <0xff3f0000 0x1000>; 900 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 904 clock-names = "i2c", "pclk"; 905 pinctrl-names = "default"; 906 pinctrl-0 = <&i2c0_xfer>; 907 status = "disabled"; 908 }; 909 910 i2c2: i2c@ff400000 { 911 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 912 reg = <0xff400000 0x1000>; 913 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 rockchip,grf = <&pmugrf>; 917 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; 918 clock-names = "i2c", "pclk"; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&i2c2_xfer>; 921 status = "disabled"; 922 }; 923 924 amba { 925 compatible = "simple-bus"; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 ranges; 929 930 dmac: dma-controller@ff4e0000 { 931 compatible = "arm,pl330", "arm,primecell"; 932 reg = <0xff4e0000 0x4000>; 933 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 935 #dma-cells = <1>; 936 clocks = <&cru ACLK_DMAC>; 937 clock-names = "apb_pclk"; 938 arm,pl330-periph-burst; 939 }; 940 }; 941 942 uart1: serial@ff410000 { 943 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 944 reg = <0xff410000 0x100>; 945 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 946 reg-shift = <2>; 947 reg-io-width = <4>; 948 dmas = <&dmac 7>, <&dmac 6>; 949 clock-frequency = <24000000>; 950 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 951 clock-names = "baudclk", "apb_pclk"; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 954 status = "disabled"; 955 }; 956 957 pwm0: pwm@ff430000 { 958 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 959 reg = <0xff430000 0x10>; 960 #pwm-cells = <3>; 961 pinctrl-names = "active"; 962 pinctrl-0 = <&pwm0m0_pins>; 963 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 964 clock-names = "pwm", "pclk"; 965 status = "disabled"; 966 }; 967 968 pwm1: pwm@ff430010 { 969 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 970 reg = <0xff430010 0x10>; 971 #pwm-cells = <3>; 972 pinctrl-names = "active"; 973 pinctrl-0 = <&pwm1m0_pins>; 974 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 975 clock-names = "pwm", "pclk"; 976 status = "disabled"; 977 }; 978 979 pwm2: pwm@ff430020 { 980 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 981 reg = <0xff430020 0x10>; 982 #pwm-cells = <3>; 983 pinctrl-names = "active"; 984 pinctrl-0 = <&pwm2m0_pins>; 985 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 986 clock-names = "pwm", "pclk"; 987 status = "disabled"; 988 }; 989 990 pwm3: pwm@ff430030 { 991 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 992 reg = <0xff430030 0x10>; 993 #pwm-cells = <3>; 994 pinctrl-names = "active"; 995 pinctrl-0 = <&pwm3m0_pins>; 996 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 997 clock-names = "pwm", "pclk"; 998 status = "disabled"; 999 }; 1000 1001 pwm4: pwm@ff440000 { 1002 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1003 reg = <0xff440000 0x10>; 1004 #pwm-cells = <3>; 1005 pinctrl-names = "active"; 1006 pinctrl-0 = <&pwm4m0_pins>; 1007 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 1008 clock-names = "pwm", "pclk"; 1009 status = "disabled"; 1010 }; 1011 1012 pwm5: pwm@ff440010 { 1013 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1014 reg = <0xff440010 0x10>; 1015 #pwm-cells = <3>; 1016 pinctrl-names = "active"; 1017 pinctrl-0 = <&pwm5m0_pins>; 1018 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 1019 clock-names = "pwm", "pclk"; 1020 status = "disabled"; 1021 }; 1022 1023 pwm6: pwm@ff440020 { 1024 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1025 reg = <0xff440020 0x10>; 1026 #pwm-cells = <3>; 1027 pinctrl-names = "active"; 1028 pinctrl-0 = <&pwm6m0_pins>; 1029 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 1030 clock-names = "pwm", "pclk"; 1031 status = "disabled"; 1032 }; 1033 1034 pwm7: pwm@ff440030 { 1035 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1036 reg = <0xff440030 0x10>; 1037 #pwm-cells = <3>; 1038 pinctrl-names = "active"; 1039 pinctrl-0 = <&pwm7m0_pins>; 1040 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 1041 clock-names = "pwm", "pclk"; 1042 status = "disabled"; 1043 }; 1044 1045 spi0: spi@ff450000 { 1046 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 1047 reg = <0xff450000 0x1000>; 1048 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 clocks = <&pmucru CLK_SPI0>, <&pmucru PCLK_SPI0>; 1052 clock-names = "spiclk", "apb_pclk"; 1053 dmas = <&dmac 1>, <&dmac 0>; 1054 dma-names = "tx", "rx"; 1055 pinctrl-names = "default", "high_speed"; 1056 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1057 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 1058 status = "disabled"; 1059 }; 1060 1061 pvtm@ff470000 { 1062 compatible = "rockchip,rv1126-pmu-pvtm"; 1063 reg = <0xff470000 0x100>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 pvtm@2 { 1068 reg = <2>; 1069 clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>; 1070 clock-names = "clk", "pclk"; 1071 resets = <&pmucru SRST_PMUPVTM>, 1072 <&pmucru SRST_PMUPVTM_P>; 1073 reset-names = "rst", "rst-p"; 1074 }; 1075 }; 1076 1077 pmucru: clock-controller@ff480000 { 1078 compatible = "rockchip,rv1126-pmucru"; 1079 reg = <0xff480000 0x1000>; 1080 rockchip,pmugrf = <&pmugrf>; 1081 #clock-cells = <1>; 1082 #reset-cells = <1>; 1083 }; 1084 1085 cru: clock-controller@ff490000 { 1086 compatible = "rockchip,rv1126-cru"; 1087 reg = <0xff490000 0x1000>; 1088 rockchip,grf = <&grf>; 1089 #clock-cells = <1>; 1090 #reset-cells = <1>; 1091 1092 assigned-clocks = 1093 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 1094 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 1095 <&cru PLL_HPLL>, <&cru ARMCLK>, 1096 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 1097 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 1098 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 1099 <&cru HCLK_PDCORE_NIU>; 1100 assigned-clock-rates = 1101 <32768>, <1188000000>, 1102 <100000000>, <500000000>, 1103 <1400000000>, <600000000>, 1104 <500000000>, <200000000>, 1105 <100000000>, <300000000>, 1106 <200000000>, <150000000>, 1107 <200000000>; 1108 assigned-clock-parents = 1109 <&pmucru CLK_OSC0_DIV32K>; 1110 }; 1111 1112 csi_dphy0: csi-dphy@ff4b0000 { 1113 compatible = "rockchip,rv1126-csi-dphy"; 1114 reg = <0xff4b0000 0x8000>; 1115 clocks = <&cru PCLK_CSIPHY0>; 1116 clock-names = "pclk"; 1117 rockchip,grf = <&grf>; 1118 status = "disabled"; 1119 }; 1120 1121 csi_dphy1: csi-dphy@ff4b8000 { 1122 compatible = "rockchip,rv1126-csi-dphy"; 1123 reg = <0xff4b8000 0x8000>; 1124 clocks = <&cru PCLK_CSIPHY1>; 1125 clock-names = "pclk"; 1126 rockchip,grf = <&grf>; 1127 status = "disabled"; 1128 }; 1129 1130 u2phy0: usb2-phy@ff4c0000 { 1131 compatible = "rockchip,rv1126-usb2phy"; 1132 reg = <0xff4c0000 0x8000>; 1133 rockchip,grf = <&grf>; 1134 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>; 1135 clock-names = "phyclk", "pclk"; 1136 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>; 1137 reset-names = "u2phy", "u2phy-apb"; 1138 #clock-cells = <0>; 1139 status = "disabled"; 1140 1141 u2phy_otg: otg-port { 1142 #phy-cells = <0>; 1143 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "otg-bvalid", "otg-id", 1148 "linestate", "disconnect"; 1149 status = "disabled"; 1150 }; 1151 }; 1152 1153 u2phy1: usb2-phy@ff4c8000 { 1154 compatible = "rockchip,rv1126-usb2phy"; 1155 reg = <0xff4c8000 0x8000>; 1156 rockchip,grf = <&grf>; 1157 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>; 1158 clock-names = "phyclk", "pclk"; 1159 assigned-clocks = <&cru USB480M>; 1160 assigned-clock-parents = <&u2phy1>; 1161 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>; 1162 reset-names = "u2phy", "u2phy-apb"; 1163 #clock-cells = <0>; 1164 clock-output-names = "usb480m_phy"; 1165 status = "disabled"; 1166 1167 u2phy_host: host-port { 1168 #phy-cells = <0>; 1169 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "linestate", "disconnect"; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 mipi_dphy: mipi-dphy@ff4d0000 { 1177 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk3568-video-phy"; 1178 reg = <0xff4d0000 0x500>, <0xffb30000 0x500>; 1179 reg-names = "phy", "host"; 1180 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>; 1181 assigned-clock-rates = <24000000>; 1182 clocks = <&pmucru CLK_MIPIDSIPHY_REF>, 1183 <&cru PCLK_DSIPHY>, <&cru PCLK_DSIHOST>; 1184 clock-names = "ref", "pclk", "pclk_host"; 1185 #clock-cells = <0>; 1186 resets = <&cru SRST_DSIPHY_P>; 1187 reset-names = "apb"; 1188 #phy-cells = <0>; 1189 rockchip,grf = <&grf>; 1190 status = "disabled"; 1191 }; 1192 1193 rng: rng@ff500400 { 1194 compatible = "rockchip,cryptov2-rng"; 1195 reg = <0xff500400 0x80>; 1196 clocks = <&cru HCLK_CRYPTO>; 1197 clock-names = "hclk_crypto"; 1198 power-domains = <&power RV1126_PD_CRYPTO>; 1199 resets = <&cru SRST_CRYPTO_CORE>; 1200 reset-names = "reset"; 1201 status = "disabled"; 1202 }; 1203 1204 crypto: crypto@ff500000 { 1205 compatible = "rockchip,rv1126-crypto"; 1206 reg = <0xff500000 0x400>, <0xff500480 0x3B80>; 1207 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>, 1209 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1210 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 1211 power-domains = <&power RV1126_PD_CRYPTO>; 1212 resets = <&cru SRST_CRYPTO_CORE>; 1213 reset-names = "crypto-rst"; 1214 status = "disabled"; 1215 }; 1216 1217 i2c1: i2c@ff510000 { 1218 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1219 reg = <0xff510000 0x1000>; 1220 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1224 clock-names = "i2c", "pclk"; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&i2c1_xfer>; 1227 status = "disabled"; 1228 }; 1229 1230 i2c3: i2c@ff520000 { 1231 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1232 reg = <0xff520000 0x1000>; 1233 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1237 clock-names = "i2c", "pclk"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&i2c3m0_xfer>; 1240 status = "disabled"; 1241 }; 1242 1243 i2c4: i2c@ff530000 { 1244 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1245 reg = <0xff530000 0x1000>; 1246 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1250 clock-names = "i2c", "pclk"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&i2c4m0_xfer>; 1253 status = "disabled"; 1254 }; 1255 1256 i2c5: i2c@ff540000 { 1257 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 1258 reg = <0xff540000 0x1000>; 1259 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1263 clock-names = "i2c", "pclk"; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&i2c5m0_xfer>; 1266 status = "disabled"; 1267 }; 1268 1269 pwm8: pwm@ff550000 { 1270 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1271 reg = <0xff550000 0x10>; 1272 #pwm-cells = <3>; 1273 pinctrl-names = "active"; 1274 pinctrl-0 = <&pwm8m0_pins>; 1275 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1276 clock-names = "pwm", "pclk"; 1277 status = "disabled"; 1278 }; 1279 1280 pwm9: pwm@ff550010 { 1281 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1282 reg = <0xff550010 0x10>; 1283 #pwm-cells = <3>; 1284 pinctrl-names = "active"; 1285 pinctrl-0 = <&pwm9m0_pins>; 1286 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1287 clock-names = "pwm", "pclk"; 1288 status = "disabled"; 1289 }; 1290 1291 pwm10: pwm@ff550020 { 1292 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1293 reg = <0xff550020 0x10>; 1294 #pwm-cells = <3>; 1295 pinctrl-names = "active"; 1296 pinctrl-0 = <&pwm10m0_pins>; 1297 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1298 clock-names = "pwm", "pclk"; 1299 status = "disabled"; 1300 }; 1301 1302 pwm11: pwm@ff550030 { 1303 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 1304 reg = <0xff550030 0x10>; 1305 #pwm-cells = <3>; 1306 pinctrl-names = "active"; 1307 pinctrl-0 = <&pwm11m0_pins>; 1308 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1309 clock-names = "pwm", "pclk"; 1310 status = "disabled"; 1311 }; 1312 1313 uart0: serial@ff560000 { 1314 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1315 reg = <0xff560000 0x100>; 1316 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1317 reg-shift = <2>; 1318 reg-io-width = <4>; 1319 dmas = <&dmac 5>, <&dmac 4>; 1320 clock-frequency = <24000000>; 1321 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1322 clock-names = "baudclk", "apb_pclk"; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; 1325 status = "disabled"; 1326 }; 1327 1328 uart2: serial@ff570000 { 1329 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1330 reg = <0xff570000 0x100>; 1331 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1332 reg-shift = <2>; 1333 reg-io-width = <4>; 1334 dmas = <&dmac 9>, <&dmac 8>; 1335 clock-frequency = <24000000>; 1336 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1337 clock-names = "baudclk", "apb_pclk"; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&uart2m1_xfer>; 1340 status = "disabled"; 1341 }; 1342 1343 uart3: serial@ff580000 { 1344 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1345 reg = <0xff580000 0x100>; 1346 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1347 reg-shift = <2>; 1348 reg-io-width = <4>; 1349 dmas = <&dmac 11>, <&dmac 10>; 1350 clock-frequency = <24000000>; 1351 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1352 clock-names = "baudclk", "apb_pclk"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>; 1355 status = "disabled"; 1356 }; 1357 1358 uart4: serial@ff590000 { 1359 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1360 reg = <0xff590000 0x100>; 1361 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1362 reg-shift = <2>; 1363 reg-io-width = <4>; 1364 dmas = <&dmac 13>, <&dmac 12>; 1365 clock-frequency = <24000000>; 1366 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1367 clock-names = "baudclk", "apb_pclk"; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; 1370 status = "disabled"; 1371 }; 1372 1373 uart5: serial@ff5a0000 { 1374 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 1375 reg = <0xff5a0000 0x100>; 1376 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1377 reg-shift = <2>; 1378 reg-io-width = <4>; 1379 dmas = <&dmac 15>, <&dmac 14>; 1380 clock-frequency = <24000000>; 1381 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1382 clock-names = "baudclk", "apb_pclk"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 1385 status = "disabled"; 1386 }; 1387 1388 spi1: spi@ff5b0000 { 1389 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 1390 reg = <0xff5b0000 0x1000>; 1391 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1395 clock-names = "spiclk", "apb_pclk"; 1396 dmas = <&dmac 3>, <&dmac 2>; 1397 dma-names = "tx", "rx"; 1398 pinctrl-names = "default", "high_speed"; 1399 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1400 pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>; 1401 status = "disabled"; 1402 }; 1403 1404 otp: otp@ff5c0000 { 1405 compatible = "rockchip,rv1126-otp"; 1406 reg = <0xff5c0000 0x1000>; 1407 #address-cells = <1>; 1408 #size-cells = <1>; 1409 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>; 1410 clock-names = "otp", "apb_pclk"; 1411 status = "disabled"; 1412 1413 /* Data cells */ 1414 otp_cpu_code: cpu-code@2 { 1415 reg = <0x02 0x2>; 1416 }; 1417 otp_id: id@7 { 1418 reg = <0x07 0x10>; 1419 }; 1420 cpu_leakage: cpu-leakage@17 { 1421 reg = <0x17 0x1>; 1422 }; 1423 logic_leakage: logic-leakage@18 { 1424 reg = <0x18 0x1>; 1425 }; 1426 npu_leakage: npu-leakage@19 { 1427 reg = <0x19 0x1>; 1428 }; 1429 venc_leakage: venc-leakage@1a { 1430 reg = <0x1a 0x1>; 1431 }; 1432 cpu_performance: cpu-performance@1e { 1433 reg = <0x1e 0x1>; 1434 bits = <4 3>; 1435 }; 1436 npu_performance: npu-performance@1f { 1437 reg = <0x1f 0x1>; 1438 bits = <0 2>; 1439 }; 1440 venc_performance: venc-performance@1f { 1441 reg = <0x1f 0x1>; 1442 bits = <2 2>; 1443 }; 1444 cpu_tsadc_trim_l: cpu-tsadc-trim-l@23 { 1445 reg = <0x23 0x1>; 1446 }; 1447 cpu_tsadc_trim_h: cpu-tsadc-trim-h@24 { 1448 reg = <0x24 0x1>; 1449 bits = <0 4>; 1450 }; 1451 npu_tsadc_trim_l: npu-tsadc-trim-l@25 { 1452 reg = <0x25 0x1>; 1453 }; 1454 npu_tsadc_trim_h: npu-tsadc-trim-h@26 { 1455 reg = <0x26 0x1>; 1456 bits = <0 4>; 1457 }; 1458 tsadc_trim_base: tsadc-trim-base@27 { 1459 reg = <0x27 0x1>; 1460 }; 1461 }; 1462 1463 saradc: saradc@ff5e0000 { 1464 compatible = "rockchip,rk3399-saradc"; 1465 reg = <0xff5e0000 0x100>; 1466 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1467 #io-channel-cells = <1>; 1468 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1469 clock-names = "saradc", "apb_pclk"; 1470 resets = <&cru SRST_SARADC_P>; 1471 reset-names = "saradc-apb"; 1472 status = "disabled"; 1473 }; 1474 1475 cpu_tsadc: tsadc@ff5f0000 { 1476 compatible = "rockchip,rv1126-tsadc"; 1477 reg = <0xff5f0000 0x100>; 1478 rockchip,grf = <&grf>; 1479 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1480 assigned-clocks = <&cru CLK_CPU_TSADC>; 1481 assigned-clock-rates = <4000000>; 1482 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>, 1483 <&cru CLK_CPU_TSADCPHY>; 1484 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1485 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>, 1486 <&cru SRST_CPU_TSADCPHY>; 1487 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1488 rockchip,hw-tshut-temp = <120000>; 1489 #thermal-sensor-cells = <1>; 1490 nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>, <&tsadc_trim_base>; 1491 nvmem-cell-names = "trim_l", "trim_h", "trim_base"; 1492 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1493 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1494 pinctrl-names = "gpio", "otpout"; 1495 pinctrl-0 = <&tsadcm0_shut>; 1496 pinctrl-1 = <&tsadc_shutorg>; 1497 status = "disabled"; 1498 }; 1499 1500 npu_tsadc: tsadc@ff5f8000 { 1501 compatible = "rockchip,rv1126-tsadc"; 1502 reg = <0xff5f8000 0x100>; 1503 rockchip,grf = <&grf>; 1504 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1505 assigned-clocks = <&cru CLK_NPU_TSADC>; 1506 assigned-clock-rates = <4000000>; 1507 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>, 1508 <&cru CLK_NPU_TSADCPHY>; 1509 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1510 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>, 1511 <&cru SRST_NPU_TSADCPHY>; 1512 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1513 rockchip,hw-tshut-temp = <120000>; 1514 #thermal-sensor-cells = <1>; 1515 nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>, <&tsadc_trim_base>; 1516 nvmem-cell-names = "trim_l", "trim_h", "trim_base"; 1517 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1518 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1519 pinctrl-names = "gpio", "otpout"; 1520 pinctrl-0 = <&tsadcm0_shut>; 1521 pinctrl-1 = <&tsadc_shutorg>; 1522 status = "disabled"; 1523 }; 1524 1525 dcf: dcf@ff600000 { 1526 compatible = "syscon"; 1527 reg = <0xff600000 0x1000>; 1528 status = "disabled"; 1529 }; 1530 1531 can: can@ff610000 { 1532 compatible = "rockchip,can-1.0"; 1533 reg = <0xff610000 0x100>; 1534 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1535 assigned-clocks = <&cru CLK_CAN>; 1536 assigned-clock-rates = <200000000>; 1537 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>; 1538 clock-names = "baudclk", "apb_pclk"; 1539 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>; 1540 reset-names = "can", "can-apb"; 1541 status = "disabled"; 1542 }; 1543 1544 rktimer: rktimer@ff660000 { 1545 compatible = "rockchip,rk3288-timer"; 1546 reg = <0xff660000 0x20>; 1547 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1549 clock-names = "pclk", "timer"; 1550 }; 1551 1552 wdt: watchdog@ff680000 { 1553 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; 1554 reg = <0xff680000 0x100>; 1555 clocks = <&cru PCLK_WDT>; 1556 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1557 status = "disabled"; 1558 }; 1559 1560 mailbox: mailbox@ff6a0000 { 1561 compatible = "rockchip,rv1126-mailbox", 1562 "rockchip,rk3368-mailbox"; 1563 reg = <0xff6a0000 0x1000>; 1564 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cru PCLK_MAILBOX>; 1566 clock-names = "pclk_mailbox"; 1567 #mbox-cells = <1>; 1568 status = "disabled"; 1569 }; 1570 1571 hw_decompress: decompress@ff6c0000 { 1572 compatible = "rockchip,hw-decompress"; 1573 reg = <0xff6c0000 0x1000>; 1574 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1576 clock-names = "aclk", "dclk", "pclk"; 1577 resets = <&cru SRST_DECOM_D>; 1578 reset-names = "dresetn"; 1579 status = "disabled"; 1580 }; 1581 1582 i2s0_8ch: i2s@ff800000 { 1583 compatible = "rockchip,rv1126-i2s-tdm"; 1584 reg = <0xff800000 0x1000>; 1585 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>; 1587 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1588 dmas = <&dmac 20>, <&dmac 19>; 1589 dma-names = "tx", "rx"; 1590 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>; 1591 reset-names = "tx-m", "rx-m"; 1592 rockchip,cru = <&cru>; 1593 rockchip,grf = <&grf>; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&i2s0m0_sclk_tx 1596 &i2s0m0_sclk_rx 1597 &i2s0m0_lrck_tx 1598 &i2s0m0_lrck_rx 1599 &i2s0m0_sdi0 1600 &i2s0m0_sdo0 1601 &i2s0m0_sdo1_sdi3 1602 &i2s0m0_sdo2_sdi2 1603 &i2s0m0_sdo3_sdi1>; 1604 status = "disabled"; 1605 }; 1606 1607 i2s1_2ch: i2s@ff810000 { 1608 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1609 reg = <0xff810000 0x1000>; 1610 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>; 1612 clock-names = "i2s_clk", "i2s_hclk"; 1613 dmas = <&dmac 22>, <&dmac 21>; 1614 dma-names = "tx", "rx"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&i2s1m0_sclk 1617 &i2s1m0_lrck 1618 &i2s1m0_sdi 1619 &i2s1m0_sdo>; 1620 status = "disabled"; 1621 }; 1622 1623 i2s2_2ch: i2s@ff820000 { 1624 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1625 reg = <0xff820000 0x1000>; 1626 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1627 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>; 1628 clock-names = "i2s_clk", "i2s_hclk"; 1629 dmas = <&dmac 24>, <&dmac 23>; 1630 dma-names = "tx", "rx"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&i2s2m0_sclk 1633 &i2s2m0_lrck 1634 &i2s2m0_sdi 1635 &i2s2m0_sdo>; 1636 status = "disabled"; 1637 }; 1638 1639 pdm: pdm@ff830000 { 1640 compatible = "rockchip,rv1126-pdm", "rockchip,pdm"; 1641 reg = <0xff830000 0x1000>; 1642 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1643 clock-names = "pdm_clk", "pdm_hclk"; 1644 dmas = <&dmac 25>; 1645 dma-names = "rx"; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&pdmm0_clk 1648 &pdmm0_clk1 1649 &pdmm0_sdi0 1650 &pdmm0_sdi1 1651 &pdmm0_sdi2 1652 &pdmm0_sdi3>; 1653 status = "disabled"; 1654 }; 1655 1656 audpwm: audpwm@ff840000 { 1657 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1"; 1658 reg = <0xff840000 0x1000>; 1659 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 1660 clock-names = "clk", "hclk"; 1661 dmas = <&dmac 26>; 1662 dma-names = "tx"; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&audpwmm0_pins>; 1665 rockchip,sample-width-bits = <11>; 1666 rockchip,interpolat-points = <1>; 1667 status = "disabled"; 1668 }; 1669 1670 rkacdc_dig: codec-digital@ff850000 { 1671 compatible = "rockchip,rv1126-codec-digital", "rockchip,codec-digital-v1"; 1672 reg = <0xff850000 0x1000>; 1673 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru PCLK_ACDCDIG>; 1674 clock-names = "adc", "dac", "pclk"; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&acodec_pins>; 1677 resets = <&cru SRST_ACDCDIG>; 1678 reset-names = "reset" ; 1679 rockchip,grf = <&grf>; 1680 status = "disabled"; 1681 }; 1682 1683 dfi: dfi@ff9c0000 { 1684 reg = <0xff9c0000 0x400>; 1685 compatible = "rockchip,rv1126-dfi"; 1686 rockchip,pmugrf = <&pmugrf>; 1687 status = "disabled"; 1688 }; 1689 1690 dmc: dmc { 1691 compatible = "rockchip,rv1126-dmc"; 1692 dcf = <&dcf>; 1693 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1694 interrupt-names = "complete"; 1695 devfreq-events = <&dfi>; 1696 clocks = <&cru SCLK_DDRCLK>; 1697 clock-names = "dmc_clk"; 1698 operating-points-v2 = <&dmc_opp_table>; 1699 ddr_timing = <&ddr_timing>; 1700 upthreshold = <40>; 1701 downdifferential = <20>; 1702 system-status-freq = < 1703 /*system status freq(KHz)*/ 1704 SYS_STATUS_NORMAL 924000 1705 SYS_STATUS_REBOOT 328000 1706 SYS_STATUS_SUSPEND 328000 1707 SYS_STATUS_VIDEO_1080P 924000 1708 SYS_STATUS_BOOST 924000 1709 SYS_STATUS_ISP 924000 1710 SYS_STATUS_PERFORMANCE 924000 1711 >; 1712 auto-min-freq = <328000>; 1713 auto-freq-en = <1>; 1714 #cooling-cells = <2>; 1715 status = "disabled"; 1716 }; 1717 1718 dmc_opp_table: dmc-opp-table { 1719 compatible = "operating-points-v2"; 1720 1721 opp-328000000 { 1722 opp-hz = /bits/ 64 <328000000>; 1723 opp-microvolt = <800000>; 1724 }; 1725 opp-528000000 { 1726 opp-hz = /bits/ 64 <528000000>; 1727 opp-microvolt = <800000>; 1728 }; 1729 opp-784000000 { 1730 opp-hz = /bits/ 64 <784000000>; 1731 opp-microvolt = <800000>; 1732 }; 1733 opp-924000000 { 1734 opp-hz = /bits/ 64 <924000000>; 1735 opp-microvolt = <800000>; 1736 }; 1737 opp-1056000000 { 1738 opp-hz = /bits/ 64 <1056000000>; 1739 opp-microvolt = <800000>; 1740 status = "disabled"; 1741 }; 1742 }; 1743 1744 dmcdbg: dmcdbg { 1745 compatible = "rockchip,rv1126-dmcdbg"; 1746 status = "disabled"; 1747 }; 1748 1749 rkcif: rkcif@ffae0000 { 1750 compatible = "rockchip,rv1126-cif"; 1751 reg = <0xffae0000 0x8000>; 1752 reg-names = "cif_regs"; 1753 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1754 interrupt-names = "cif-intr"; 1755 clocks = <&cru ACLK_CIF>,<&cru HCLK_CIF>, 1756 <&cru DCLK_CIF>; 1757 clock-names = "aclk_cif","hclk_cif", 1758 "dclk_cif"; 1759 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, 1760 <&cru SRST_CIF_D>, <&cru SRST_CIF_P>, 1761 <&cru SRST_CIF_I>, <&cru SRST_CIF_RX_P>; 1762 reset-names = "rst_cif_a", "rst_cif_h", 1763 "rst_cif_d", "rst_cif_p", 1764 "rst_cif_i", "rst_cif_rx_p"; 1765 assigned-clocks = <&cru DCLK_CIF>; 1766 assigned-clock-rates = <300000000>; 1767 power-domains = <&power RV1126_PD_VI>; 1768 rockchip,grf = <&grf>; 1769 // iommus = <&rkcif_mmu>; 1770 memory-region = <&isp_reserved>; 1771 status = "disabled"; 1772 }; 1773 1774 rkcif_mmu: iommu@ffae0800 { 1775 compatible = "rockchip,iommu"; 1776 reg = <0xffae0800 0x100>; 1777 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1778 interrupt-names = "cif_mmu"; 1779 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1780 clock-names = "aclk", "iface"; 1781 power-domains = <&power RV1126_PD_VI>; 1782 #iommu-cells = <0>; 1783 status = "disabled"; 1784 }; 1785 1786 rkcif_lite: rkcif_lite@ffae8000 { 1787 compatible = "rockchip,rv1126-cif-lite"; 1788 reg = <0xffae8000 0x8000>; 1789 reg-names = "cif_regs"; 1790 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1791 interrupt-names = "cif-lite-intr"; 1792 clocks = <&cru ACLK_CIFLITE>,<&cru HCLK_CIFLITE>, 1793 <&cru DCLK_CIFLITE>; 1794 clock-names = "aclk_cif_lite","hclk_cif_lite", 1795 "dclk_cif_lite"; 1796 resets = <&cru SRST_CIFLITE_A>, <&cru SRST_CIFLITE_H>, 1797 <&cru SRST_CIFLITE_D>, <&cru SRST_CIFLITE_RX_P>; 1798 reset-names = "rst_cif_lite_a", "rst_cif_lite_h", 1799 "rst_cif_lite_d", "rst_cif_lite_rx_p"; 1800 assigned-clocks = <&cru DCLK_CIFLITE>; 1801 assigned-clock-rates = <300000000>; 1802 power-domains = <&power RV1126_PD_VI>; 1803 iommus = <&rkcif_lite_mmu>; 1804 status = "disabled"; 1805 }; 1806 1807 rkcif_lite_mmu: iommu@ffae8800 { 1808 compatible = "rockchip,iommu"; 1809 reg = <0xffae8800 0x100>; 1810 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1811 interrupt-names = "cif_lite_mmu"; 1812 clocks = <&cru ACLK_CIFLITE>, <&cru HCLK_CIFLITE>; 1813 clock-names = "aclk", "iface"; 1814 power-domains = <&power RV1126_PD_VI>; 1815 #iommu-cells = <0>; 1816 status = "disabled"; 1817 }; 1818 1819 rk_rga: rk_rga@ffaf0000 { 1820 compatible = "rockchip,rga2"; 1821 reg = <0xffaf0000 0x1000>; 1822 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1824 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1825 power-domains = <&power RV1126_PD_VO>; 1826 status = "disable"; 1827 }; 1828 1829 vop: vop@ffb00000 { 1830 compatible = "rockchip,rv1126-vop"; 1831 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 1832 reg-names = "regs", "gamma_lut"; 1833 rockchip,grf = <&grf>; 1834 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1835 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1836 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1837 iommus = <&vop_mmu>; 1838 power-domains = <&power RV1126_PD_VO>; 1839 status = "disabled"; 1840 1841 vop_out: port { 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 1845 vop_out_rgb: endpoint@0 { 1846 reg = <0>; 1847 remote-endpoint = <&rgb_in_vop>; 1848 }; 1849 1850 vop_out_dsi: endpoint@1 { 1851 reg = <1>; 1852 remote-endpoint = <&dsi_in_vop>; 1853 }; 1854 }; 1855 }; 1856 1857 vop_mmu: iommu@ffb00f00 { 1858 compatible = "rockchip,iommu"; 1859 reg = <0xffb00f00 0x100>; 1860 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1861 interrupt-names = "vop_mmu"; 1862 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1863 clock-names = "aclk", "iface"; 1864 #iommu-cells = <0>; 1865 rockchip,disable-device-link-resume; 1866 power-domains = <&power RV1126_PD_VO>; 1867 status = "disabled"; 1868 }; 1869 1870 mipi_csi2_hw: mipi-csi2-hw@ffb10000 { 1871 compatible = "rockchip,rv1126-mipi-csi2-hw"; 1872 reg = <0xffb10000 0x10000>; 1873 reg-names = "csihost_regs"; 1874 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupt-names = "csi-intr1", "csi-intr2"; 1877 clocks = <&cru PCLK_CSIHOST>; 1878 clock-names = "pclk_csi2host"; 1879 resets = <&cru SRST_CSIHOST_P>; 1880 reset-names = "srst_csihost_p"; 1881 power-domains = <&power RV1126_PD_VI>; 1882 status = "disabled"; 1883 }; 1884 1885 iep: iep@ffb20000 { 1886 compatible = "rockchip,rv1126-iep", "rockchip,iep-v2"; 1887 reg = <0xffb20000 0x500>; 1888 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1889 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; 1890 clock-names = "aclk", "hclk", "sclk"; 1891 resets = <&cru SRST_IEP_A>, <&cru SRST_IEP_H>, 1892 <&cru SRST_IEP_CORE>; 1893 reset-names = "rst_a", "rst_h", "rst_s"; 1894 power-domains = <&power RV1126_PD_VO>; 1895 rockchip,srv = <&mpp_srv>; 1896 rockchip,taskqueue-node = <3>; 1897 rockchip,resetgroup-node = <3>; 1898 iommus = <&iep_mmu>; 1899 status = "disabled"; 1900 }; 1901 1902 iep_mmu: iommu@ffb20800 { 1903 compatible = "rockchip,iommu"; 1904 reg = <0xffb20800 0x100>; 1905 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1906 interrupt-names = "iep_mmu"; 1907 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1908 clock-names = "aclk", "iface"; 1909 #iommu-cells = <0>; 1910 power-domains = <&power RV1126_PD_VO>; 1911 //rockchip,disable-device-link-resume; 1912 status = "disabled"; 1913 }; 1914 1915 dsi: dsi@ffb30000 { 1916 compatible = "rockchip,rv1126-mipi-dsi"; 1917 reg = <0xffb30000 0x500>; 1918 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1919 clocks = <&cru PCLK_DSIHOST>, <&cru HCLK_PDVO>; 1920 clock-names = "pclk", "hclk"; 1921 resets = <&cru SRST_DSIHOST_P>; 1922 reset-names = "apb"; 1923 phys = <&mipi_dphy>; 1924 phy-names = "dphy"; 1925 rockchip,grf = <&grf>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 power-domains = <&power RV1126_PD_VO>; 1929 status = "disabled"; 1930 1931 ports { 1932 port { 1933 dsi_in_vop: endpoint { 1934 remote-endpoint = <&vop_out_dsi>; 1935 }; 1936 }; 1937 }; 1938 }; 1939 1940 rkisp: rkisp@ffb50000 { 1941 compatible = "rockchip,rv1126-rkisp"; 1942 reg = <0xffb50000 0x10000>; 1943 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1946 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1947 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1948 <&cru CLK_ISP>; 1949 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1950 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1951 assigned-clock-rates = <500000000>, <250000000>; 1952 resets = <&cru SRST_ISP>, <&cru SRST_ISP_RX_P>; 1953 reset-names = "isp", "isp-rx-p"; 1954 power-domains = <&power RV1126_PD_VI>; 1955 iommus = <&rkisp_mmu>; 1956 memory-region = <&isp_reserved>; 1957 status = "disabled"; 1958 }; 1959 1960 rkisp_mmu: iommu@ffb51a00 { 1961 compatible = "rockchip,iommu"; 1962 reg = <0xffb51a00 0x100>; 1963 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1964 interrupt-names = "isp_mmu"; 1965 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1966 clock-names = "aclk", "iface"; 1967 power-domains = <&power RV1126_PD_VI>; 1968 #iommu-cells = <0>; 1969 rockchip,disable-mmu-reset; 1970 status = "disabled"; 1971 }; 1972 1973 rkisp_vir0: rkisp-vir0 { 1974 compatible = "rockchip,rv1126-rkisp-vir"; 1975 rockchip,hw = <&rkisp>; 1976 status = "disabled"; 1977 1978 ports { 1979 #address-cells = <1>; 1980 #size-cells = <0>; 1981 1982 port@1 { 1983 reg = <1>; 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 1987 isp0_out: endpoint@1 { 1988 reg = <1>; 1989 remote-endpoint = <&ispp0_in>; 1990 }; 1991 }; 1992 }; 1993 }; 1994 1995 rkisp_vir1: rkisp-vir1 { 1996 compatible = "rockchip,rv1126-rkisp-vir"; 1997 rockchip,hw = <&rkisp>; 1998 status = "disabled"; 1999 2000 ports { 2001 #address-cells = <1>; 2002 #size-cells = <0>; 2003 2004 port@1 { 2005 reg = <1>; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 2009 isp1_out: endpoint@1 { 2010 reg = <1>; 2011 remote-endpoint = <&ispp1_in>; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 rkisp_vir2: rkisp-vir2 { 2018 compatible = "rockchip,rv1126-rkisp-vir"; 2019 rockchip,hw = <&rkisp>; 2020 status = "disabled"; 2021 2022 ports { 2023 #address-cells = <1>; 2024 #size-cells = <0>; 2025 2026 port@1 { 2027 reg = <1>; 2028 #address-cells = <1>; 2029 #size-cells = <0>; 2030 2031 isp2_out: endpoint@1 { 2032 reg = <1>; 2033 remote-endpoint = <&ispp2_in>; 2034 }; 2035 }; 2036 }; 2037 }; 2038 2039 rkispp: rkispp@ffb60000 { 2040 compatible = "rockchip,rv1126-rkispp"; 2041 reg = <0xffb60000 0x20000>; 2042 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2044 interrupt-names = "ispp_irq", "fec_irq"; 2045 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 2046 <&cru CLK_ISPP>; 2047 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 2048 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 2049 <&cru CLK_ISPP>; 2050 assigned-clock-rates = <500000000>, <250000000>, 2051 <400000000>; 2052 power-domains = <&power RV1126_PD_ISPP>; 2053 iommus = <&rkispp_mmu>; 2054 rockchip,restart-monitor-en; 2055 status = "disabled"; 2056 }; 2057 2058 rkispp_mmu: iommu@ffb60e00 { 2059 compatible = "rockchip,iommu"; 2060 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>; 2061 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 2064 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1"; 2065 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>; 2066 clock-names = "aclk", "iface"; 2067 power-domains = <&power RV1126_PD_ISPP>; 2068 #iommu-cells = <0>; 2069 rockchip,disable-mmu-reset; 2070 status = "disabled"; 2071 }; 2072 2073 rkispp_vir0: rkispp-vir0 { 2074 compatible = "rockchip,rv1126-rkispp-vir"; 2075 rockchip,hw = <&rkispp>; 2076 status = "disabled"; 2077 2078 port { 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 2082 ispp0_in: endpoint@0 { 2083 reg = <0>; 2084 remote-endpoint = <&isp0_out>; 2085 }; 2086 }; 2087 }; 2088 2089 rkispp_vir1: rkispp-vir1 { 2090 compatible = "rockchip,rv1126-rkispp-vir"; 2091 rockchip,hw = <&rkispp>; 2092 status = "disabled"; 2093 2094 port { 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 2098 ispp1_in: endpoint@0 { 2099 reg = <0>; 2100 remote-endpoint = <&isp1_out>; 2101 }; 2102 }; 2103 }; 2104 2105 rkispp_vir2: rkispp-vir2 { 2106 compatible = "rockchip,rv1126-rkispp-vir"; 2107 rockchip,hw = <&rkispp>; 2108 status = "disabled"; 2109 2110 port { 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 2114 ispp2_in: endpoint@0 { 2115 reg = <0>; 2116 remote-endpoint = <&isp2_out>; 2117 }; 2118 }; 2119 }; 2120 2121 rkvdec: rkvdec@ffb80000 { 2122 compatible = "rockchip,rkv-decoder-v1"; 2123 reg = <0xffb80000 0x400>; 2124 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2125 interrupt-names = "irq_dec"; 2126 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>, 2127 <&cru CLK_VDEC_CA>, <&cru CLK_VDEC_CORE>, 2128 <&cru CLK_VDEC_HEVC_CA>; 2129 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 2130 "clk_core", "clk_hevc_cabac"; 2131 resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>, 2132 <&cru SRST_VDEC_CA>, <&cru SRST_VDEC_CORE>, 2133 <&cru SRST_VDEC_HEVC_CA>; 2134 reset-names = "video_a", "video_h", "video_cabac", 2135 "video_core", "video_hevc_cabac"; 2136 power-domains = <&power RV1126_PD_VDPU>; 2137 iommus = <&rkvdec_mmu>; 2138 rockchip,srv = <&mpp_srv>; 2139 rockchip,taskqueue-node = <0>; 2140 rockchip,resetgroup-node = <0>; 2141 status = "disabled"; 2142 }; 2143 2144 rkvdec_mmu: iommu@ffb80480 { 2145 compatible = "rockchip,iommu"; 2146 reg = <0xffb80480 0x40>, <0xffb804c0 0x40>; 2147 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2148 interrupt-names = "rkvdec_mmu"; 2149 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>; 2150 clock-names = "aclk", "iface"; 2151 power-domains = <&power RV1126_PD_VDPU>; 2152 #iommu-cells = <0>; 2153 status = "disabled"; 2154 }; 2155 2156 vepu: vepu@ffb90000 { 2157 compatible = "rockchip,vpu-encoder-v2"; 2158 reg = <0xffb90000 0x400>; 2159 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 2160 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 2161 clock-names = "aclk_vcodec", "hclk_vcodec"; 2162 rockchip,normal-rates = <400000000>, <0>; 2163 rockchip,advanced-rates = <500000000>, <0>; 2164 rockchip,default-max-load = <2088960>; 2165 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 2166 reset-names = "shared_video_a", "shared_video_h"; 2167 iommus = <&vpu_mmu>; 2168 rockchip,srv = <&mpp_srv>; 2169 rockchip,taskqueue-node = <1>; 2170 rockchip,resetgroup-node = <1>; 2171 power-domains = <&power RV1126_PD_VDPU>; 2172 status = "disabled"; 2173 }; 2174 2175 vdpu: vdpu@ffb90400 { 2176 compatible = "rockchip,vpu-decoder-v2"; 2177 reg = <0xffb90400 0x400>; 2178 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 2179 interrupt-names = "irq_dec"; 2180 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 2181 clock-names = "aclk_vcodec", "hclk_vcodec"; 2182 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>; 2183 reset-names = "shared_video_a", "shared_video_h"; 2184 iommus = <&vpu_mmu>; 2185 power-domains = <&power RV1126_PD_VDPU>; 2186 rockchip,srv = <&mpp_srv>; 2187 rockchip,taskqueue-node = <1>; 2188 rockchip,resetgroup-node = <1>; 2189 status = "disabled"; 2190 }; 2191 2192 vpu_mmu: iommu@ffb90800 { 2193 compatible = "rockchip,iommu"; 2194 reg = <0xffb90800 0x40>; 2195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 2196 interrupt-names = "vpu_mmu"; 2197 clock-names = "aclk", "iface"; 2198 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>; 2199 power-domains = <&power RV1126_PD_VDPU>; 2200 #iommu-cells = <0>; 2201 status = "disabled"; 2202 }; 2203 2204 rkvenc: rkvenc@ffbb0000 { 2205 compatible = "rockchip,rkv-encoder-v1"; 2206 reg = <0xffbb0000 0x400>; 2207 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 2208 interrupt-names = "irq_enc"; 2209 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>, 2210 <&cru CLK_VENC_CORE>; 2211 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 2212 rockchip,normal-rates = <297000000>, <0>, <396000000>; 2213 rockchip,advanced-rates = <297000000>, <0>, <594000000>; 2214 rockchip,default-max-load = <2088960>; 2215 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>, 2216 <&cru SRST_VENC_CORE>; 2217 reset-names = "video_a", "video_h", "video_core"; 2218 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>; 2219 assigned-clock-rates = <297000000>, <396000000>; 2220 operating-points-v2 = <&rkvenc_opp_table>; 2221 dynamic-power-coefficient = <1418>; 2222 #cooling-cells = <2>; 2223 iommus = <&rkvenc_mmu>; 2224 node-name = "rkvenc"; 2225 rockchip,srv = <&mpp_srv>; 2226 rockchip,taskqueue-node = <2>; 2227 rockchip,resetgroup-node = <2>; 2228 power-domains = <&power RV1126_PD_VEPU>; 2229 status = "disabled"; 2230 }; 2231 2232 rkvenc_opp_table: rkvenc-opp-table { 2233 compatible = "operating-points-v2"; 2234 2235 nvmem-cells = <&venc_leakage>, <&venc_performance>; 2236 nvmem-cell-names = "leakage", "performance"; 2237 2238 rockchip,temp-freq-table = < 2239 80000 500000 2240 100000 396000 2241 >; 2242 2243 clocks = <&pmucru PLL_GPLL>; 2244 rockchip,bin-scaling-sel = < 2245 0 37 2246 1 40 2247 >; 2248 rockchip,bin-voltage-sel = < 2249 1 0 2250 >; 2251 2252 rockchip,evb-irdrop = <25000>; 2253 2254 /* The source clock is CLK_VENC_CORE */ 2255 opp-297000000 { 2256 opp-hz = /bits/ 64 <297000000>; 2257 opp-microvolt = <725000 725000 1000000>; 2258 opp-microvolt-L0 = <750000 750000 1000000>; 2259 }; 2260 opp-396000000 { 2261 opp-hz = /bits/ 64 <396000000>; 2262 opp-microvolt = <725000 725000 1000000>; 2263 opp-microvolt-L0 = <775000 775000 1000000>; 2264 }; 2265 opp-500000000 { 2266 opp-hz = /bits/ 64 <500000000>; 2267 opp-microvolt = <750000 750000 1000000>; 2268 opp-microvolt-L0 = <800000 800000 1000000>; 2269 }; 2270 opp-594000000 { 2271 opp-hz = /bits/ 64 <594000000>; 2272 opp-microvolt = <825000 825000 1000000>; 2273 }; 2274 }; 2275 2276 rkvenc_mmu: iommu@ffbb0f00 { 2277 compatible = "rockchip,iommu"; 2278 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>; 2279 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 2281 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 2282 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>; 2283 clock-names = "aclk", "iface"; 2284 rockchip,disable-mmu-reset; 2285 rockchip,enable-cmd-retry; 2286 #iommu-cells = <0>; 2287 power-domains = <&power RV1126_PD_VEPU>; 2288 status = "disabled"; 2289 }; 2290 2291 pvtm@ffc00000 { 2292 compatible = "rockchip,rv1126-npu-pvtm"; 2293 reg = <0xffc00000 0x100>; 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 2297 pvtm@1 { 2298 reg = <1>; 2299 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>; 2300 clock-names = "clk", "pclk"; 2301 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>; 2302 reset-names = "rts", "rst-p"; 2303 }; 2304 }; 2305 2306 gmac: ethernet@ffc40000 { 2307 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 2308 reg = <0xffc40000 0x0ffff>; 2309 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2311 interrupt-names = "macirq", "eth_wake_irq"; 2312 rockchip,grf = <&grf>; 2313 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 2314 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 2315 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 2316 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 2317 clock-names = "stmmaceth", "mac_clk_rx", 2318 "mac_clk_tx", "clk_mac_ref", 2319 "aclk_mac", "pclk_mac", 2320 "clk_mac_speed", "ptp_ref"; 2321 resets = <&cru SRST_GMAC_A>; 2322 reset-names = "stmmaceth"; 2323 2324 snps,mixed-burst; 2325 snps,tso; 2326 2327 snps,axi-config = <&stmmac_axi_setup>; 2328 snps,mtl-rx-config = <&mtl_rx_setup>; 2329 snps,mtl-tx-config = <&mtl_tx_setup>; 2330 status = "disabled"; 2331 2332 mdio: mdio { 2333 compatible = "snps,dwmac-mdio"; 2334 #address-cells = <0x1>; 2335 #size-cells = <0x0>; 2336 }; 2337 2338 stmmac_axi_setup: stmmac-axi-config { 2339 snps,wr_osr_lmt = <4>; 2340 snps,rd_osr_lmt = <8>; 2341 snps,blen = <0 0 0 0 16 8 4>; 2342 }; 2343 2344 mtl_rx_setup: rx-queues-config { 2345 snps,rx-queues-to-use = <1>; 2346 queue0 {}; 2347 }; 2348 2349 mtl_tx_setup: tx-queues-config { 2350 snps,tx-queues-to-use = <1>; 2351 queue0 {}; 2352 }; 2353 }; 2354 2355 emmc: dwmmc@ffc50000 { 2356 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 2357 reg = <0xffc50000 0x4000>; 2358 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2359 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 2360 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 2361 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2362 fifo-depth = <0x100>; 2363 max-frequency = <200000000>; 2364 pinctrl-names = "default"; 2365 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 2366 power-domains = <&power RV1126_PD_NVM>; 2367 rockchip,use-v2-tuning; 2368 status = "disabled"; 2369 }; 2370 2371 sdmmc: dwmmc@ffc60000 { 2372 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 2373 reg = <0xffc60000 0x4000>; 2374 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 2376 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 2377 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2378 fifo-depth = <0x100>; 2379 max-frequency = <200000000>; 2380 pinctrl-names = "normal", "idle"; 2381 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 2382 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; 2383 status = "disabled"; 2384 }; 2385 2386 sdio: dwmmc@ffc70000 { 2387 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 2388 reg = <0xffc70000 0x4000>; 2389 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2390 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 2391 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 2392 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2393 fifo-depth = <0x100>; 2394 max-frequency = <200000000>; 2395 pinctrl-names = "default"; 2396 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 2397 power-domains = <&power RV1126_PD_SDIO>; 2398 status = "disabled"; 2399 }; 2400 2401 nandc: nandc@ffc80000 { 2402 compatible = "rockchip,rk-nandc"; 2403 reg = <0xffc80000 0x4000>; 2404 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2405 nandc_id = <0>; 2406 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>; 2407 clock-names = "clk_nandc", "hclk_nandc"; 2408 pinctrl-names = "default"; 2409 pinctrl-0 = <&flash_pins>; 2410 power-domains = <&power RV1126_PD_NVM>; 2411 status = "disabled"; 2412 }; 2413 2414 sfc: spi@ffc90000 { 2415 compatible = "rockchip,sfc"; 2416 reg = <0xffc90000 0x4000>; 2417 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2418 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2419 clock-names = "clk_sfc", "hclk_sfc"; 2420 pinctrl-names = "default"; 2421 pinctrl-0 = <&fspi_pins>; 2422 assigned-clocks = <&cru SCLK_SFC>; 2423 assigned-clock-rates = <80000000>; 2424 power-domains = <&power RV1126_PD_NVM>; 2425 #address-cells = <1>; 2426 #size-cells = <0>; 2427 status = "disabled"; 2428 }; 2429 2430 npu: npu@ffbc0000 { 2431 compatible = "rockchip,npu"; 2432 reg = <0xffbc0000 0x4000>; 2433 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, <&cru PCLK_PDNPU>, <&cru CLK_CORE_NPU>; 2434 clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu"; 2435 assigned-clocks = <&cru CLK_CORE_NPU>, <&cru ACLK_NPU>; 2436 assigned-clock-rates = <396000000>, <600000000>; 2437 operating-points-v2 = <&npu_opp_table>; 2438 dynamic-power-coefficient = <1343>; 2439 #cooling-cells = <2>; 2440 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2441 power-domains = <&power RV1126_PD_NPU>; 2442 status = "disabled"; 2443 }; 2444 2445 npu_opp_table: npu-opp-table { 2446 compatible = "operating-points-v2"; 2447 2448 nvmem-cells = <&npu_leakage>, <&npu_performance>; 2449 nvmem-cell-names = "leakage", "performance"; 2450 2451 rockchip,temp-freq-table = < 2452 80000 600000 2453 90000 396000 2454 100000 300000 2455 >; 2456 2457 clocks = <&pmucru PLL_GPLL>; 2458 rockchip,bin-scaling-sel = < 2459 0 23 2460 1 37 2461 2 37 2462 >; 2463 rockchip,bin-voltage-sel = < 2464 2 0 2465 >; 2466 rockchip,pvtm-voltage-sel = < 2467 0 108500 1 2468 108501 113500 2 2469 113501 999999 3 2470 >; 2471 rockchip,pvtm-freq = <396000>; 2472 rockchip,pvtm-volt = <800000>; 2473 rockchip,pvtm-ch = <1 0>; 2474 rockchip,pvtm-sample-time = <1000>; 2475 rockchip,pvtm-number = <10>; 2476 rockchip,pvtm-error = <1000>; 2477 rockchip,pvtm-ref-temp = <37>; 2478 rockchip,pvtm-temp-prop = <(-29) 0>; 2479 rockchip,pvtm-thermal-zone = "npu-thermal"; 2480 2481 opp-200000000 { 2482 opp-hz = /bits/ 64 <200000000>; 2483 opp-microvolt = <750000 750000 1000000>; 2484 opp-microvolt-L0 = <775000 775000 1000000>; 2485 }; 2486 opp-300000000 { 2487 opp-hz = /bits/ 64 <300000000>; 2488 opp-microvolt = <750000 750000 1000000>; 2489 opp-microvolt-L0 = <775000 775000 1000000>; 2490 }; 2491 opp-396000000 { 2492 opp-hz = /bits/ 64 <396000000>; 2493 opp-microvolt = <750000 750000 1000000>; 2494 opp-microvolt-L0 = <775000 775000 1000000>; 2495 }; 2496 opp-500000000 { 2497 opp-hz = /bits/ 64 <500000000>; 2498 opp-microvolt = <750000 750000 1000000>; 2499 opp-microvolt-L0 = <775000 775000 1000000>; 2500 }; 2501 opp-600000000 { 2502 opp-hz = /bits/ 64 <600000000>; 2503 opp-microvolt = <750000 750000 1000000>; 2504 opp-microvolt-L0 = <775000 775000 1000000>; 2505 }; 2506 opp-700000000 { 2507 opp-hz = /bits/ 64 <700000000>; 2508 opp-microvolt = <800000 800000 1000000>; 2509 opp-microvolt-L1 = <800000 800000 1000000>; 2510 opp-microvolt-L2 = <775000 775000 1000000>; 2511 opp-microvolt-L3 = <750000 750000 1000000>; 2512 }; 2513 opp-800000000 { 2514 opp-hz = /bits/ 64 <800000000>; 2515 opp-microvolt = <850000 850000 1000000>; 2516 opp-microvolt-L1 = <850000 850000 1000000>; 2517 opp-microvolt-L2 = <825000 825000 1000000>; 2518 opp-microvolt-L3 = <800000 800000 1000000>; 2519 }; 2520 opp-934000000 { 2521 opp-hz = /bits/ 64 <934000000>; 2522 opp-microvolt = <950000 950000 1000000>; 2523 opp-microvolt-L1 = <950000 950000 1000000>; 2524 opp-microvolt-L2 = <925000 925000 1000000>; 2525 opp-microvolt-L3 = <900000 900000 1000000>; 2526 }; 2527 }; 2528 2529 usbdrd: usb0 { 2530 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3"; 2531 #address-cells = <1>; 2532 #size-cells = <1>; 2533 ranges; 2534 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>, 2535 <&cru HCLK_PDUSB>; 2536 clock-names = "ref_clk", "bus_clk", "hclk"; 2537 status = "disabled"; 2538 2539 usbdrd_dwc3: dwc3@ffd00000 { 2540 compatible = "snps,dwc3"; 2541 reg = <0xffd00000 0x100000>; 2542 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2543 dr_mode = "otg"; 2544 maximum-speed = "high-speed"; 2545 phys = <&u2phy_otg>; 2546 phy-names = "usb2-phy"; 2547 phy_type = "utmi_wide"; 2548 power-domains = <&power RV1126_PD_USB>; 2549 resets = <&cru SRST_USBOTG_A>; 2550 reset-names = "usb3-otg"; 2551 snps,dis_enblslpm_quirk; 2552 snps,dis-u2-freeclk-exists-quirk; 2553 snps,dis_u2_susphy_quirk; 2554 snps,dis-del-phy-power-chg-quirk; 2555 snps,tx-ipgap-linecheck-dis-quirk; 2556 snps,tx-fifo-resize; 2557 snps,xhci-trb-ent-quirk; 2558 snps,usb2-lpm-disable; 2559 status = "disabled"; 2560 }; 2561 }; 2562 2563 usb_host0_ehci: usb@ffe00000 { 2564 compatible = "generic-ehci"; 2565 reg = <0xffe00000 0x10000>; 2566 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2567 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2568 <&u2phy1>; 2569 clock-names = "usbhost", "arbiter", "utmi"; 2570 phys = <&u2phy_host>; 2571 phy-names = "usb"; 2572 power-domains = <&power RV1126_PD_USB>; 2573 status = "disabled"; 2574 }; 2575 2576 usb_host0_ohci: usb@ffe10000 { 2577 compatible = "generic-ohci"; 2578 reg = <0xffe10000 0x10000>; 2579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2580 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 2581 <&u2phy1>; 2582 clock-names = "usbhost", "arbiter", "utmi"; 2583 phys = <&u2phy_host>; 2584 phy-names = "usb"; 2585 power-domains = <&power RV1126_PD_USB>; 2586 status = "disabled"; 2587 }; 2588 2589 pinctrl: pinctrl { 2590 compatible = "rockchip,rv1126-pinctrl"; 2591 rockchip,grf = <&grf>; 2592 rockchip,pmu = <&pmugrf>; 2593 #address-cells = <1>; 2594 #size-cells = <1>; 2595 ranges; 2596 2597 gpio0: gpio0@ff460000 { 2598 compatible = "rockchip,gpio-bank"; 2599 reg = <0xff460000 0x100>; 2600 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2601 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 2602 2603 gpio-controller; 2604 #gpio-cells = <2>; 2605 2606 interrupt-controller; 2607 #interrupt-cells = <2>; 2608 }; 2609 2610 gpio1: gpio1@ff620000 { 2611 compatible = "rockchip,gpio-bank"; 2612 reg = <0xff620000 0x100>; 2613 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2614 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2615 2616 gpio-controller; 2617 #gpio-cells = <2>; 2618 2619 interrupt-controller; 2620 #interrupt-cells = <2>; 2621 }; 2622 2623 gpio2: gpio2@ff630000 { 2624 compatible = "rockchip,gpio-bank"; 2625 reg = <0xff630000 0x100>; 2626 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2627 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2628 2629 gpio-controller; 2630 #gpio-cells = <2>; 2631 2632 interrupt-controller; 2633 #interrupt-cells = <2>; 2634 }; 2635 2636 gpio3: gpio3@ff640000 { 2637 compatible = "rockchip,gpio-bank"; 2638 reg = <0xff640000 0x100>; 2639 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2640 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2641 2642 gpio-controller; 2643 #gpio-cells = <2>; 2644 2645 interrupt-controller; 2646 #interrupt-cells = <2>; 2647 }; 2648 2649 gpio4: gpio4@ff650000 { 2650 compatible = "rockchip,gpio-bank"; 2651 reg = <0xff650000 0x100>; 2652 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2653 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2654 2655 gpio-controller; 2656 #gpio-cells = <2>; 2657 2658 interrupt-controller; 2659 #interrupt-cells = <2>; 2660 }; 2661 }; 2662}; 2663 2664#include "rv1126-pinctrl.dtsi" 2665 2666
