1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5#include <dt-bindings/clock/rv1106-cru.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1106"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 csi2dphy0 = &csi2_dphy0; 24 csi2dphy1 = &csi2_dphy1; 25 csi2dphy2 = &csi2_dphy2; 26 ethernet0 = &gmac; 27 gpio0 = &gpio0; 28 gpio1 = &gpio1; 29 gpio2 = &gpio2; 30 gpio3 = &gpio3; 31 gpio4 = &gpio4; 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 mmc0 = &emmc; 38 mmc1 = &sdmmc; 39 mmc2 = &sdio; 40 pwm0 = &pwm0; 41 pwm1 = &pwm1; 42 pwm2 = &pwm2; 43 pwm3 = &pwm3; 44 pwm4 = &pwm4; 45 pwm5 = &pwm5; 46 pwm6 = &pwm6; 47 pwm7 = &pwm7; 48 pwm8 = &pwm8; 49 pwm9 = &pwm9; 50 pwm10 = &pwm10; 51 pwm11 = &pwm11; 52 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 53 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 54 serial0 = &uart0; 55 serial1 = &uart1; 56 serial2 = &uart2; 57 serial3 = &uart3; 58 serial4 = &uart4; 59 serial5 = &uart5; 60 spi0 = &spi0; 61 spi1 = &spi1; 62 spi2 = &sfc; 63 }; 64 65 clocks { 66 compatible = "simple-bus"; 67 68 cpu_pvtpll: cpu-pvtpll { 69 compatible = "fixed-clock"; 70 clock-frequency = <1300000000>; 71 clock-output-names = "cpu_pvtpll"; 72 #clock-cells = <0>; 73 status = "disabled"; 74 }; 75 76 rkvenc_pvtpll: pvtpll-0 { 77 compatible = "fixed-clock"; 78 clock-frequency = <410000000>; 79 clock-output-names = "clk_pvtpll_0"; 80 #clock-cells = <0>; 81 }; 82 83 npu_pvtpll: pvtpll-1 { 84 compatible = "fixed-clock"; 85 clock-frequency = <420000000>; 86 clock-output-names = "clk_pvtpll_1"; 87 #clock-cells = <0>; 88 }; 89 90 xin24m: oscillator { 91 compatible = "fixed-clock"; 92 clock-frequency = <24000000>; 93 clock-output-names = "xin24m"; 94 #clock-cells = <0>; 95 }; 96 }; 97 98 cpus { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu0: cpu@0 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a7"; 105 reg = <0x0>; 106 clocks = <&cru ARMCLK>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 }; 109 }; 110 111 cpu0_opp_table: cpu0-opp-table { 112 compatible = "operating-points-v2"; 113 opp-shared; 114 115 nvmem-cells = <&cpu_leakage>; 116 nvmem-cell-names = "leakage"; 117 118 rockchip,pvtpll-avg-offset = <0x4001c>; 119 rockchip,pvtpll-min-rate = <1104000>; 120 rockchip,pvtpll-volt-step = <12500>; 121 rockchip,grf = <&grf>; 122 rockchip,temp-hysteresis = <5000>; 123 rockchip,low-temp = <10000>; 124 rockchip,low-temp-min-volt = <900000>; 125 126 opp-408000000 { 127 opp-hz = /bits/ 64 <408000000>; 128 opp-microvolt = <850000 850000 1000000>; 129 clock-latency-ns = <40000>; 130 }; 131 opp-600000000 { 132 opp-hz = /bits/ 64 <600000000>; 133 opp-microvolt = <850000 850000 1000000>; 134 clock-latency-ns = <40000>; 135 }; 136 opp-816000000 { 137 opp-hz = /bits/ 64 <816000000>; 138 opp-microvolt = <850000 850000 1000000>; 139 clock-latency-ns = <40000>; 140 opp-suspend; 141 }; 142 opp-1104000000 { 143 opp-hz = /bits/ 64 <1104000000>; 144 opp-microvolt = <850000 850000 1000000>; 145 clock-latency-ns = <40000>; 146 }; 147 opp-1200000000 { 148 opp-hz = /bits/ 64 <1200000000>; 149 opp-microvolt = <850000 850000 1000000>; 150 clock-latency-ns = <40000>; 151 }; 152 opp-1296000000 { 153 opp-hz = /bits/ 64 <1296000000>; 154 opp-microvolt = <875000 850000 1000000>; 155 clock-latency-ns = <40000>; 156 }; 157 opp-1416000000 { 158 opp-hz = /bits/ 64 <1416000000>; 159 opp-microvolt = <925000 850000 1000000>; 160 clock-latency-ns = <40000>; 161 }; 162 opp-1512000000 { 163 opp-hz = /bits/ 64 <1512000000>; 164 opp-microvolt = <975000 850000 1000000>; 165 clock-latency-ns = <40000>; 166 }; 167 opp-1608000000 { 168 opp-hz = /bits/ 64 <1608000000>; 169 opp-microvolt = <1000000 850000 1000000>; 170 clock-latency-ns = <40000>; 171 }; 172 }; 173 174 arm-pmu { 175 compatible = "arm,cortex-a7-pmu"; 176 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-affinity = <&cpu0>; 178 }; 179 180 cpuinfo { 181 compatible = "rockchip,cpuinfo"; 182 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 183 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 184 }; 185 186 /* dphy0 full mode */ 187 csi2_dphy0: csi2-dphy0 { 188 compatible = "rockchip,rv1106-csi2-dphy"; 189 rockchip,hw = <&csi2_dphy_hw>; 190 status = "disabled"; 191 }; 192 193 /* dphy1 split mode 01 */ 194 csi2_dphy1: csi2-dphy1 { 195 compatible = "rockchip,rv1106-csi2-dphy"; 196 rockchip,hw = <&csi2_dphy_hw>; 197 status = "disabled"; 198 }; 199 200 /* dphy2 split mode 23 */ 201 csi2_dphy2: csi2-dphy2 { 202 compatible = "rockchip,rv1106-csi2-dphy"; 203 rockchip,hw = <&csi2_dphy_hw>; 204 status = "disabled"; 205 }; 206 207 display_subsystem: display-subsystem { 208 compatible = "rockchip,display-subsystem"; 209 ports = <&vop_out>; 210 status = "disabled"; 211 212 route { 213 route_rgb: route-rgb { 214 status = "disabled"; 215 logo,uboot = "logo.bmp"; 216 logo,kernel = "logo_kernel.bmp"; 217 logo,mode = "center"; 218 charge_logo,mode = "center"; 219 connect = <&vop_out_rgb>; 220 }; 221 }; 222 }; 223 224 fiq_debugger: fiq-debugger { 225 compatible = "rockchip,fiq-debugger"; 226 rockchip,serial-id = <2>; 227 rockchip,wake-irq = <0>; 228 rockchip,irq-mode-enable = <0>; 229 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 230 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 231 status = "disabled"; 232 }; 233 234 firmware { 235 optee: optee { 236 compatible = "linaro,optee-tz"; 237 method = "smc"; 238 status = "disabled"; 239 }; 240 }; 241 242 mipi0_csi2: mipi0-csi2 { 243 compatible = "rockchip,rv1106-mipi-csi2"; 244 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; 245 status = "disabled"; 246 }; 247 248 mipi1_csi2: mipi1-csi2 { 249 compatible = "rockchip,rv1106-mipi-csi2"; 250 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; 251 status = "disabled"; 252 }; 253 254 mpp_srv: mpp-srv { 255 compatible = "rockchip,mpp-service"; 256 rockchip,taskqueue-count = <2>; 257 status = "disabled"; 258 }; 259 260 mpp_vcodec: mpp-vcodec { 261 compatible = "rockchip,vcodec"; 262 status = "disabled"; 263 }; 264 265 psci { 266 compatible = "arm,psci-1.0"; 267 method = "smc"; 268 }; 269 270 rkcif_dvp: rkcif-dvp { 271 compatible = "rockchip,rkcif-dvp"; 272 rockchip,hw = <&rkcif>; 273 status = "disabled"; 274 }; 275 276 rkcif_dvp_sditf: rkcif-dvp-sditf { 277 compatible = "rockchip,rkcif-sditf"; 278 rockchip,cif = <&rkcif_dvp>; 279 status = "disabled"; 280 }; 281 282 rkcif_mipi_lvds: rkcif-mipi-lvds { 283 compatible = "rockchip,rkcif-mipi-lvds"; 284 rockchip,hw = <&rkcif>; 285 status = "disabled"; 286 }; 287 288 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 289 compatible = "rockchip,rkcif-sditf"; 290 rockchip,cif = <&rkcif_mipi_lvds>; 291 status = "disabled"; 292 }; 293 294 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 295 compatible = "rockchip,rkcif-mipi-lvds"; 296 rockchip,hw = <&rkcif>; 297 status = "disabled"; 298 }; 299 300 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 301 compatible = "rockchip,rkcif-sditf"; 302 rockchip,cif = <&rkcif_mipi_lvds1>; 303 status = "disabled"; 304 }; 305 306 rkisp_vir0: rkisp-vir0 { 307 compatible = "rockchip,rkisp-vir"; 308 rockchip,hw = <&rkisp>; 309 dvbm = <&rkdvbm>; 310 status = "disabled"; 311 }; 312 313 rkisp_vir1: rkisp-vir1 { 314 compatible = "rockchip,rkisp-vir"; 315 rockchip,hw = <&rkisp>; 316 status = "disabled"; 317 }; 318 319 rkisp_vir2: rkisp-vir2 { 320 compatible = "rockchip,rkisp-vir"; 321 rockchip,hw = <&rkisp>; 322 status = "disabled"; 323 }; 324 325 rkisp_vir3: rkisp-vir3 { 326 compatible = "rockchip,rkisp-vir"; 327 rockchip,hw = <&rkisp>; 328 status = "disabled"; 329 }; 330 331 rockchip_system_monitor: rockchip-system-monitor { 332 compatible = "rockchip,system-monitor"; 333 334 rockchip,thermal-zone = "soc-thermal"; 335 }; 336 337 thermal_zones: thermal-zones { 338 soc_thermal: soc-thermal { 339 polling-delay-passive = <20>; /* milliseconds */ 340 polling-delay = <1000>; /* milliseconds */ 341 sustainable-power = <2100>; /* milliwatts */ 342 343 thermal-sensors = <&tsadc 0>; 344 trips { 345 threshold: trip-point-0 { 346 temperature = <75000>; 347 hysteresis = <2000>; 348 type = "passive"; 349 }; 350 target: trip-point-1 { 351 temperature = <85000>; 352 hysteresis = <2000>; 353 type = "passive"; 354 }; 355 soc_crit: soc-crit { 356 /* millicelsius */ 357 temperature = <115000>; 358 /* millicelsius */ 359 hysteresis = <2000>; 360 type = "critical"; 361 }; 362 }; 363 }; 364 }; 365 366 timer { 367 compatible = "arm,armv7-timer"; 368 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 369 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 370 clock-frequency = <24000000>; 371 }; 372 373 grf: syscon@ff000000 { 374 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; 375 reg = <0xff000000 0x68000>; 376 377 grf_cru: grf-clock-controller { 378 compatible = "rockchip,rv1106-grf-cru"; 379 #clock-cells = <1>; 380 }; 381 382 reboot_mode: reboot-mode { 383 compatible = "syscon-reboot-mode"; 384 offset = <0x20200>; 385 mode-bootloader = <BOOT_BL_DOWNLOAD>; 386 mode-charge = <BOOT_CHARGING>; 387 mode-fastboot = <BOOT_FASTBOOT>; 388 mode-loader = <BOOT_BL_DOWNLOAD>; 389 mode-normal = <BOOT_NORMAL>; 390 mode-recovery = <BOOT_RECOVERY>; 391 mode-ums = <BOOT_UMS>; 392 mode-panic = <BOOT_PANIC>; 393 mode-watchdog = <BOOT_WATCHDOG>; 394 }; 395 396 rgb: rgb { 397 compatible = "rockchip,rv1106-rgb"; 398 status = "disabled"; 399 400 ports { 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 port@0 { 405 reg = <0>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 409 rgb_in_vop: endpoint@0 { 410 reg = <0>; 411 remote-endpoint = <&vop_out_rgb>; 412 }; 413 }; 414 }; 415 }; 416 417 rknpor_powergood: rknpor-powergood { 418 compatible = "rockchip,rv1106-npor-powergood"; 419 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 420 status = "okay"; 421 }; 422 }; 423 424 rtc: rtc@ff1c0000 { 425 compatible = "rockchip,rv1106-rtc"; 426 reg = <0xff1c0000 0x1000>; 427 rockchip,grf = <&grf>; 428 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>; 430 clock-names = "pclk_phy", "pclk_test"; 431 assigned-clocks = <&cru PCLK_VI_RTC_PHY>; 432 assigned-clock-rates = <24000000>; 433 status = "disabled"; 434 }; 435 436 gic: interrupt-controller@ff1f0000 { 437 compatible = "arm,gic-400"; 438 interrupt-controller; 439 #interrupt-cells = <3>; 440 #address-cells = <0>; 441 442 reg = <0xff1f1000 0x1000>, 443 <0xff1f2000 0x2000>, 444 <0xff1f4000 0x2000>, 445 <0xff1f6000 0x2000>; 446 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 447 }; 448 449 arm-debug@ff200000 { 450 compatible = "rockchip,debug"; 451 reg = <0xff200000 0x1000>; 452 }; 453 454 pvtm@ff240000 { 455 compatible = "rockchip,rv1106-core-pvtm"; 456 reg = <0xff240000 0x100>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 460 pvtm@0 { 461 reg = <0>; 462 clocks = <&cru CLK_PVTM_CORE>; 463 clock-names = "clk"; 464 resets = <&cru SRST_PVTM_CORE>, <&cru SRST_P_PVTM_CORE>; 465 reset-names = "rst", "rst-p"; 466 }; 467 }; 468 469 pmu: power-management@ff300000 { 470 compatible = "rockchip,rv1106-pmu", "syscon"; 471 reg = <0xff300000 0x1000>; 472 }; 473 474 i2c0: i2c@ff310000 { 475 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 476 reg = <0xff310000 0x1000>; 477 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 481 clock-names = "i2c", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&i2c0m0_xfer>; 484 status = "disabled"; 485 }; 486 487 i2c1: i2c@ff320000 { 488 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 489 reg = <0xff320000 0x1000>; 490 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 494 clock-names = "i2c", "pclk"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c1m0_xfer>; 497 status = "disabled"; 498 }; 499 500 dsm: codec-digital@ff340000 { 501 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1"; 502 reg = <0xff340000 0x1000>; 503 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>; 504 clock-names = "dac", "pclk"; 505 resets = <&cru SRST_M_DSM>; 506 reset-names = "reset" ; 507 rockchip,grf = <&grf>; 508 rockchip,pwm-output-mode; 509 #sound-dai-cells = <0>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&dsmaudio_pins>; 512 status = "disabled"; 513 }; 514 515 pwm0: pwm@ff350000 { 516 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 517 reg = <0xff350000 0x10>; 518 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 519 #pwm-cells = <3>; 520 pinctrl-names = "active"; 521 pinctrl-0 = <&pwm0m0_pins>; 522 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 523 clock-names = "pwm", "pclk"; 524 status = "disabled"; 525 }; 526 527 pwm1: pwm@ff350010 { 528 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 529 reg = <0xff350010 0x10>; 530 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 531 #pwm-cells = <3>; 532 pinctrl-names = "active"; 533 pinctrl-0 = <&pwm1m0_pins>; 534 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 535 clock-names = "pwm", "pclk"; 536 status = "disabled"; 537 }; 538 539 pwm2: pwm@ff350020 { 540 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 541 reg = <0xff350020 0x10>; 542 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 543 #pwm-cells = <3>; 544 pinctrl-names = "active"; 545 pinctrl-0 = <&pwm2m0_pins>; 546 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 547 clock-names = "pwm", "pclk"; 548 status = "disabled"; 549 }; 550 551 pwm3: pwm@ff350030 { 552 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 553 reg = <0xff350030 0x10>; 554 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 556 #pwm-cells = <3>; 557 pinctrl-names = "active"; 558 pinctrl-0 = <&pwm3m0_pins>; 559 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>; 560 clock-names = "pwm", "pclk"; 561 status = "disabled"; 562 }; 563 564 pwm4: pwm@ff360000 { 565 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 566 reg = <0xff360000 0x10>; 567 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 568 #pwm-cells = <3>; 569 pinctrl-names = "active"; 570 pinctrl-0 = <&pwm4m0_pins>; 571 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 572 clock-names = "pwm", "pclk"; 573 status = "disabled"; 574 }; 575 576 pwm5: pwm@ff360010 { 577 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 578 reg = <0xff360010 0x10>; 579 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 580 #pwm-cells = <3>; 581 pinctrl-names = "active"; 582 pinctrl-0 = <&pwm5m0_pins>; 583 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 584 clock-names = "pwm", "pclk"; 585 status = "disabled"; 586 }; 587 588 pwm6: pwm@ff360020 { 589 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 590 reg = <0xff360020 0x10>; 591 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 592 #pwm-cells = <3>; 593 pinctrl-names = "active"; 594 pinctrl-0 = <&pwm6m0_pins>; 595 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 596 clock-names = "pwm", "pclk"; 597 status = "disabled"; 598 }; 599 600 pwm7: pwm@ff360030 { 601 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 602 reg = <0xff360030 0x10>; 603 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 605 #pwm-cells = <3>; 606 pinctrl-names = "active"; 607 pinctrl-0 = <&pwm7m0_pins>; 608 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 609 clock-names = "pwm", "pclk"; 610 status = "disabled"; 611 }; 612 613 pmu_mailbox: mailbox@ff378000 { 614 compatible = "rockchip,rv1106-mailbox", 615 "rockchip,rk3368-mailbox"; 616 reg = <0xff378000 0x200>; 617 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cru PCLK_PMU_MAILBOX>; 619 clock-names = "pclk_mailbox"; 620 #mbox-cells = <1>; 621 status = "disabled"; 622 }; 623 624 pmuioc: syscon@ff388000 { 625 compatible = "rockchip,rv1106-pmuioc", "syscon"; 626 reg = <0xff388000 0x1000>; 627 }; 628 629 pvtm@ff390000 { 630 compatible = "rockchip,rv1106-pmu-pvtm"; 631 reg = <0xff390000 0x100>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 pvtm@0 { 636 reg = <1>; 637 clocks = <&cru CLK_PVTM_PMU>, <&cru PCLK_PVTM_PMU>; 638 clock-names = "clk", "pclk"; 639 resets = <&cru SRST_PVTM_PMU>, <&cru SRST_P_PVTM_PMU>; 640 reset-names = "rst", "rst-p"; 641 }; 642 }; 643 644 cru: clock-controller@ff3a0000 { 645 compatible = "rockchip,rv1106-cru"; 646 reg = <0xff3a0000 0x20000>; 647 rockchip,grf = <&grf>; 648 #clock-cells = <1>; 649 #reset-cells = <1>; 650 651 assigned-clocks = 652 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 653 <&cru ARMCLK>, 654 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, 655 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, 656 <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, 657 <&cru HCLK_PMU_ROOT>; 658 assigned-clock-rates = 659 <1188000000>, <1000000000>, 660 <1104000000>, 661 <400000000>, <200000000>, 662 <100000000>, <300000000>, 663 <100000000>, <100000000>, 664 <200000000>; 665 }; 666 667 saradc: saradc@ff3c0000 { 668 compatible = "rockchip,rv1106-saradc"; 669 reg = <0xff3c0000 0x200>; 670 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 671 #io-channel-cells = <1>; 672 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 673 clock-names = "saradc", "apb_pclk"; 674 resets = <&cru SRST_P_SARADC>; 675 reset-names = "saradc-apb"; 676 status = "disabled"; 677 }; 678 679 tsadc: tsadc@ff3c8000 { 680 compatible = "rockchip,rv1106-tsadc"; 681 reg = <0xff3c8000 0x1000>; 682 rockchip,grf = <&grf>; 683 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; 685 clock-names = "tsadc", "apb_pclk", "tsen"; 686 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 687 assigned-clock-rates = <1000000>, <12000000>; 688 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 689 reset-names = "tsadc", "tsadc-apb"; 690 #thermal-sensor-cells = <1>; 691 rockchip,hw-tshut-temp = <120000>; 692 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 693 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 694 status = "disabled"; 695 }; 696 697 otp: otp@ff3d0000 { 698 compatible = "rockchip,rv1106-otp"; 699 reg = <0xff3d0000 0x4000>; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 703 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>, 704 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>; 705 clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 706 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, 707 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>, 708 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>; 709 reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc"; 710 711 /* Data cells */ 712 cpu_code: cpu-code@2 { 713 reg = <0x02 0x2>; 714 }; 715 otp_cpu_version: cpu-version@8 { 716 reg = <0x08 0x1>; 717 bits = <3 3>; 718 }; 719 otp_id: id@a { 720 reg = <0x0a 0x10>; 721 }; 722 cpu_leakage: cpu-leakage@1a { 723 reg = <0x1a 0x1>; 724 }; 725 log_leakage: log-leakage@1b { 726 reg = <0x1b 0x1>; 727 }; 728 macphy_bgs: macphy-bgs@2d { 729 reg = <0x2d 0x1>; 730 }; 731 macphy_txlevel: macphy-txlevel@2e { 732 reg = <0x2e 0x2>; 733 }; 734 }; 735 736 u2phy: usb2-phy@ff3e0000 { 737 compatible = "rockchip,rv1106-usb2phy"; 738 reg = <0xff3e0000 0x8000>; 739 rockchip,usbgrf = <&grf>; 740 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 741 clock-names = "phyclk", "pclk"; 742 resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>; 743 reset-names = "u2phy", "u2phy-apb"; 744 #clock-cells = <0>; 745 status = "disabled"; 746 747 u2phy_otg: otg-port { 748 #phy-cells = <0>; 749 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "otg-bvalid", "otg-id", 754 "linestate", "disconnect"; 755 status = "disabled"; 756 }; 757 }; 758 759 csi2_dphy_hw: csi2-dphy-hw@ff3e8000 { 760 compatible = "rockchip,rv1106-csi2-dphy-hw"; 761 reg = <0xff3e8000 0x8000>; 762 clocks = <&cru PCLK_MIPICSIPHY>; 763 clock-names = "pclk"; 764 resets = <&cru SRST_P_MIPICSIPHY>; 765 reset-names = "srst_p_csiphy"; 766 rockchip,grf = <&grf>; 767 status = "disabled"; 768 }; 769 770 dmac: dma-controller@ff420000 { 771 compatible = "arm,pl330", "arm,primecell"; 772 reg = <0xff420000 0x4000>; 773 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 782 #dma-cells = <1>; 783 clocks = <&cru ACLK_DMAC>; 784 clock-names = "apb_pclk"; 785 arm,pl330-periph-burst; 786 }; 787 788 crypto: crypto@ff440000 { 789 compatible = "rockchip,crypto-v3"; 790 reg = <0xff440000 0x2000>; 791 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 793 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 794 clock-names = "aclk", "hclk", "sclk", "pka"; 795 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 796 assigned-clock-rates = <200000000>, <200000000>; 797 resets = <&cru SRST_CORE_CRYPTO>; 798 reset-names = "crypto-rst"; 799 status = "disabled"; 800 }; 801 802 rng: rng@ff448000 { 803 compatible = "rockchip,trngv1"; 804 reg = <0xff448000 0x200>; 805 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cru HCLK_TRNG_NS>; 807 clock-names = "hclk_trng"; 808 resets = <&cru SRST_H_TRNG_NS>; 809 reset-names = "reset"; 810 status = "disabled"; 811 }; 812 813 i2c2: i2c@ff450000 { 814 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 815 reg = <0xff450000 0x1000>; 816 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 820 clock-names = "i2c", "pclk"; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&i2c2m0_xfer>; 823 status = "disabled"; 824 }; 825 826 i2c3: i2c@ff460000 { 827 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 828 reg = <0xff460000 0x1000>; 829 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 833 clock-names = "i2c", "pclk"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&i2c3m0_xfer>; 836 status = "disabled"; 837 }; 838 839 i2c4: i2c@ff470000 { 840 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; 841 reg = <0xff470000 0x1000>; 842 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 846 clock-names = "i2c", "pclk"; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&i2c4m0_xfer>; 849 status = "disabled"; 850 }; 851 852 acodec: acodec@ff480000 { 853 compatible = "rockchip,rv1106-codec"; 854 reg = <0xff480000 0x1000>; 855 rockchip,grf = <&grf>; 856 clocks = <&cru PCLK_ACODEC>, 857 <&cru MCLK_ACODEC_TX>, 858 <&cru MCLK_I2S0_8CH_TX>; 859 clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu"; 860 resets = <&cru SRST_P_ACODEC>; 861 reset-names = "acodec-reset"; 862 acodec,micbias; 863 init-mic-gain = <0x22>; /* Left:20dB Right:20dB */ 864 status = "disabled"; 865 }; 866 867 pwm8: pwm@ff490000 { 868 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 869 reg = <0xff490000 0x10>; 870 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 871 #pwm-cells = <3>; 872 pinctrl-names = "active"; 873 pinctrl-0 = <&pwm8m0_pins>; 874 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 875 clock-names = "pwm", "pclk"; 876 status = "disabled"; 877 }; 878 879 pwm9: pwm@ff490010 { 880 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 881 reg = <0xff490010 0x10>; 882 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 883 #pwm-cells = <3>; 884 pinctrl-names = "active"; 885 pinctrl-0 = <&pwm9m0_pins>; 886 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 887 clock-names = "pwm", "pclk"; 888 status = "disabled"; 889 }; 890 891 pwm10: pwm@ff490020 { 892 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 893 reg = <0xff490020 0x10>; 894 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 895 #pwm-cells = <3>; 896 pinctrl-names = "active"; 897 pinctrl-0 = <&pwm10m0_pins>; 898 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 899 clock-names = "pwm", "pclk"; 900 status = "disabled"; 901 }; 902 903 pwm11: pwm@ff490030 { 904 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm"; 905 reg = <0xff490030 0x10>; 906 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 908 #pwm-cells = <3>; 909 pinctrl-names = "active"; 910 pinctrl-0 = <&pwm11m0_pins>; 911 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 912 clock-names = "pwm", "pclk"; 913 status = "disabled"; 914 }; 915 916 uart0: serial@ff4a0000 { 917 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 918 reg = <0xff4a0000 0x100>; 919 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 920 reg-shift = <2>; 921 reg-io-width = <4>; 922 dmas = <&dmac 7>, <&dmac 6>; 923 clock-frequency = <24000000>; 924 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 925 clock-names = "baudclk", "apb_pclk"; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&uart0m0_xfer>; 928 status = "disabled"; 929 }; 930 931 uart1: serial@ff4b0000 { 932 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 933 reg = <0xff4b0000 0x100>; 934 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 935 reg-shift = <2>; 936 reg-io-width = <4>; 937 dmas = <&dmac 9>, <&dmac 8>; 938 clock-frequency = <24000000>; 939 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 940 clock-names = "baudclk", "apb_pclk"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 943 status = "disabled"; 944 }; 945 946 uart2: serial@ff4c0000 { 947 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 948 reg = <0xff4c0000 0x100>; 949 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 950 reg-shift = <2>; 951 reg-io-width = <4>; 952 dmas = <&dmac 11>, <&dmac 10>; 953 clock-frequency = <24000000>; 954 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 955 clock-names = "baudclk", "apb_pclk"; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&uart2m1_xfer>; 958 status = "disabled"; 959 }; 960 961 uart3: serial@ff4d0000 { 962 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 963 reg = <0xff4d0000 0x100>; 964 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 965 reg-shift = <2>; 966 reg-io-width = <4>; 967 dmas = <&dmac 13>, <&dmac 12>; 968 clock-frequency = <24000000>; 969 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 970 clock-names = "baudclk", "apb_pclk"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&uart3m0_xfer>; 973 status = "disabled"; 974 }; 975 976 uart4: serial@ff4e0000 { 977 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 978 reg = <0xff4e0000 0x100>; 979 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 980 reg-shift = <2>; 981 reg-io-width = <4>; 982 dmas = <&dmac 15>, <&dmac 14>; 983 clock-frequency = <24000000>; 984 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 985 clock-names = "baudclk", "apb_pclk"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&uart4m0_xfer>; 988 status = "disabled"; 989 }; 990 991 uart5: serial@ff4f0000 { 992 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; 993 reg = <0xff4f0000 0x100>; 994 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 995 reg-shift = <2>; 996 reg-io-width = <4>; 997 dmas = <&dmac 17>, <&dmac 16>; 998 clock-frequency = <24000000>; 999 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1000 clock-names = "baudclk", "apb_pclk"; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 1003 status = "disabled"; 1004 }; 1005 1006 spi0: spi@ff500000 { 1007 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 1008 reg = <0xff500000 0x1000>; 1009 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>; 1013 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1014 dmas = <&dmac 1>, <&dmac 0>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1018 status = "disabled"; 1019 }; 1020 1021 spi1: spi@ff510000 { 1022 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi"; 1023 reg = <0xff510000 0x1000>; 1024 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1028 clock-names = "spiclk", "apb_pclk"; 1029 assigned-clocks = <&cru CLK_SPI1>; 1030 assigned-clock-rates = <200000000>; 1031 dmas = <&dmac 3>, <&dmac 2>; 1032 dma-names = "tx", "rx"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1035 status = "disabled"; 1036 }; 1037 1038 hw_decompress: decompress@ff520000 { 1039 compatible = "rockchip,hw-decompress"; 1040 reg = <0xff520000 0x1000>; 1041 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1043 clock-names = "aclk", "dclk", "pclk"; 1044 resets = <&cru SRST_D_DECOM>; 1045 reset-names = "dresetn"; 1046 status = "disabled"; 1047 }; 1048 1049 ioc: syscon@ff538000 { 1050 compatible = "rockchip,rv1106-ioc", "syscon"; 1051 reg = <0xff538000 0x40000>; 1052 }; 1053 1054 wdt: watchdog@ff5a0000 { 1055 compatible = "rockchip,rv1106-wdt", "snps,dw-wdt"; 1056 reg = <0xff5a0000 0x100>; 1057 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1058 clock-names = "tclk", "pclk"; 1059 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1060 status = "disabled"; 1061 }; 1062 1063 mailbox: mailbox@ff5c0000 { 1064 compatible = "rockchip,rv1106-mailbox", 1065 "rockchip,rk3368-mailbox"; 1066 reg = <0xff5c0000 0x200>; 1067 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru PCLK_MAILBOX>; 1069 clock-names = "pclk_mailbox"; 1070 #mbox-cells = <1>; 1071 status = "disabled"; 1072 }; 1073 1074 npu: npu@ff660000 { 1075 compatible = "rockchip,rv1106-rknpu"; 1076 reg = <0xff660000 0x10000>; 1077 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; 1079 clock-names = "aclk", "hclk"; 1080 assigned-clocks = <&cru ACLK_RKNN>; 1081 assigned-clock-rates = <420000000>; 1082 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; 1083 reset-names = "srst_a", "srst_h"; 1084 status = "disabled"; 1085 }; 1086 1087 system_sram: sram@ff6c0000 { 1088 compatible = "mmio-sram"; 1089 reg = <0xff6c0000 0x40000>; 1090 #address-cells = <1>; 1091 #size-cells = <1>; 1092 ranges = <0 0xff6c0000 0x40000>; 1093 rkisp_sram: rkisp-sram@0 { 1094 reg = <0x0 0x3f000>; 1095 }; 1096 hpmcu_sram: hpmcu-sram@3f000 { 1097 reg = <0x3f000 0x1000>; 1098 }; 1099 }; 1100 1101 rga2: rga@ff980000 { 1102 compatible = "rockchip,rga2_core0"; 1103 reg = <0xff980000 0x1000>; 1104 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 1106 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 1107 status = "disabled"; 1108 }; 1109 1110 vop: vop@ff990000 { 1111 compatible = "rockchip,rv1106-vop"; 1112 reg = <0xff990000 0x200>; 1113 reg-names = "regs"; 1114 rockchip,grf = <&grf>; 1115 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1117 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1118 status = "disabled"; 1119 1120 vop_out: port { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 vop_out_rgb: endpoint@0 { 1125 reg = <0>; 1126 remote-endpoint = <&rgb_in_vop>; 1127 }; 1128 }; 1129 }; 1130 1131 sdio: mmc@ff9a0000 { 1132 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1133 reg = <0xff9a0000 0x4000>; 1134 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1136 <&grf_cru SCLK_SDIO_DRV>, <&grf_cru SCLK_SDIO_SAMPLE>; 1137 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1138 fifo-depth = <0x100>; 1139 max-frequency = <200000000>; 1140 status = "disabled"; 1141 }; 1142 1143 rkisp: rkisp@ffa00000 { 1144 compatible = "rockchip,rv1106-rkisp"; 1145 reg = <0xffa00000 0x7f00>; 1146 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1149 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1150 clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>, 1151 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>; 1152 clock-names = "aclk_isp", "hclk_isp", 1153 "clk_isp_core", "clk_isp_core_vicap"; 1154 rockchip,sram = <&rkisp_sram>; 1155 status = "disabled"; 1156 }; 1157 1158 rkcif: rkcif@ffa10000 { 1159 compatible = "rockchip,rv1106-cif"; 1160 reg = <0xffa10000 0x10000>; 1161 reg-names = "cif_regs"; 1162 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1163 interrupt-names = "cif-intr"; 1164 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 1165 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>, 1166 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>, 1167 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>, 1168 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>, 1169 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>; 1170 clock-names = "aclk_cif","hclk_cif", 1171 "dclk_cif", "pclk_cif", 1172 "i0clk_cif", "i1clk_cif", 1173 "rx0clk_cif", "rx1clk_cif", 1174 "isp0clk_cif", "sclk_m0_cif", 1175 "sclk_m1_cif", "pclk_vepu_cif"; 1176 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 1177 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 1178 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>, 1179 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>, 1180 <&cru SRST_VICAP_ISP0>, <&cru SRST_P_VICAP_VEPU>; 1181 reset-names = "rst_cif_a","rst_cif_h", 1182 "rst_cif_d", "rst_cif_p", 1183 "rst_cif_i0", "rst_cif_i1", 1184 "rst_cif_rx0", "rst_cif_rx1", 1185 "rst_cif_isp0", "rst_cif_pclk_vepu"; 1186 rockchip,grf = <&grf>; 1187 status = "disabled"; 1188 }; 1189 1190 mipi0_csi2_hw: mipi-csi2-hw@ffa20000 { 1191 compatible = "rockchip,rv1106-mipi-csi2-hw"; 1192 reg = <0xffa20000 0x10000>; 1193 reg-names = "csihost_regs"; 1194 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-names = "csi-intr1", "csi-intr2"; 1197 clocks = <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>; 1198 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 1199 resets = <&cru SRST_P_CSIHOST0>; 1200 reset-names = "srst_csihost_p"; 1201 status = "okay"; 1202 }; 1203 1204 mipi1_csi2_hw: mipi-csi2-hw@ffa30000 { 1205 compatible = "rockchip,rv1106-mipi-csi2-hw"; 1206 reg = <0xffa30000 0x10000>; 1207 reg-names = "csihost_regs"; 1208 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1210 interrupt-names = "csi-intr1", "csi-intr2"; 1211 clocks = <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>; 1212 clock-names = "pclk_csi2host", "clk_rxbyte_hs"; 1213 resets = <&cru SRST_P_CSIHOST1>; 1214 reset-names = "srst_csihost_p"; 1215 status = "okay"; 1216 }; 1217 1218 rkvenc: rkvenc@ffa50000 { 1219 compatible = "rockchip,rkv-encoder-rv1106"; 1220 reg = <0xffa50000 0x6000>; 1221 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1222 interrupt-names = "irq_rkvenc"; 1223 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; 1224 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1225 rockchip,normal-rates = <300000000>, <0>, <410000000>; 1226 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; 1227 assigned-clock-rates = <300000000>, <400000000>; 1228 resets = <&cru SRST_A_VEPU>, <&cru SRST_H_VEPU>, <&cru SRST_CORE_VEPU>; 1229 reset-names = "video_a", "video_h", "video_core"; 1230 rockchip,srv = <&mpp_srv>; 1231 rockchip,taskqueue-node = <0>; 1232 dvbm = <&rkdvbm>; 1233 status = "disabled"; 1234 }; 1235 1236 rkvenc_pp: rkvenc-pp@ffa60000 { 1237 compatible = "rockchip,rkvenc-pp-rv1106"; 1238 reg = <0xffa60000 0x900>; 1239 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1240 interrupt-names = "irq_rkvenc_pp"; 1241 clocks = <&cru ACLK_VEPU_PP>, <&cru HCLK_VEPU_PP>; 1242 clock-names = "aclk_vepu_pp", "hclk_vepu_pp"; 1243 assigned-clocks = <&cru ACLK_VEPU_PP>, <&cru HCLK_VEPU_PP>; 1244 resets = <&cru SRST_A_VEPU_PP>, <&cru SRST_H_VEPU_PP>; 1245 rockchip,srv = <&mpp_srv>; 1246 rockchip,taskqueue-node = <1>; 1247 status = "disabled"; 1248 }; 1249 1250 rkdvbm: rkdvbm@ffa70000 { 1251 compatible = "rockchip,rk-dvbm"; 1252 reg = <0xffa70000 0x90>; 1253 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "irq_rkdvbm"; 1255 clocks = <&cru CLK_CORE_VEPU_DVBM>; 1256 clock-names = "clk_core"; 1257 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>; 1258 assigned-clock-rates = <200000000>; 1259 resets = <&cru SRST_CORE_VEPU_DVBM>; 1260 reset-names = "dvbm_rst"; 1261 status = "disabled"; 1262 }; 1263 1264 gmac: ethernet@ffa80000 { 1265 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a"; 1266 reg = <0xffa80000 0x10000>; 1267 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-names = "macirq", "eth_wake_irq"; 1270 rockchip,grf = <&grf>; 1271 clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>, 1272 <&cru ACLK_MAC>, <&cru PCLK_MAC>; 1273 clock-names = "stmmaceth", "clk_mac_ref", 1274 "aclk_mac", "pclk_mac"; 1275 resets = <&cru SRST_A_MAC>; 1276 reset-names = "stmmaceth"; 1277 1278 snps,mixed-burst; 1279 snps,tso; 1280 1281 tx-dma-size = <256>; 1282 rx-dma-size = <128>; 1283 1284 snps,axi-config = <&stmmac_axi_setup>; 1285 snps,mtl-rx-config = <&mtl_rx_setup>; 1286 snps,mtl-tx-config = <&mtl_tx_setup>; 1287 1288 phy-mode = "rmii"; 1289 clock_in_out = "input"; 1290 phy-handle = <&rmii_phy>; 1291 1292 /* FLOW_OFF: 0, FLOW_RX: 1, FLOW_TX: 2, FLOW_AUTO: 3 */ 1293 snps,flow-ctrl = <0>; 1294 1295 nvmem-cells = <&macphy_bgs>; 1296 nvmem-cell-names = "bgs"; 1297 status = "disabled"; 1298 1299 mdio: mdio { 1300 compatible = "snps,dwmac-mdio"; 1301 #address-cells = <0x1>; 1302 #size-cells = <0x0>; 1303 rmii_phy: ethernet-phy@2 { 1304 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 1305 reg = <2>; 1306 clocks = <&cru CLK_MACPHY>; 1307 resets = <&cru SRST_MACPHY>; 1308 phy-is-integrated; 1309 nvmem-cells = <&macphy_txlevel>; 1310 nvmem-cell-names = "txlevel"; 1311 bgs,increment = <2>; 1312 }; 1313 }; 1314 1315 stmmac_axi_setup: stmmac-axi-config { 1316 snps,wr_osr_lmt = <4>; 1317 snps,rd_osr_lmt = <8>; 1318 snps,blen = <0 0 0 0 16 8 4>; 1319 }; 1320 1321 mtl_rx_setup: rx-queues-config { 1322 snps,rx-queues-to-use = <1>; 1323 queue0 { 1324 status = "okay"; 1325 }; 1326 }; 1327 1328 mtl_tx_setup: tx-queues-config { 1329 snps,tx-queues-to-use = <1>; 1330 queue0 { 1331 status = "okay"; 1332 }; 1333 }; 1334 }; 1335 1336 emmc: mmc@ffa90000 { 1337 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1338 reg = <0xffa90000 0x4000>; 1339 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>, 1341 <&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>; 1342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1343 fifo-depth = <0x100>; 1344 max-frequency = <200000000>; 1345 rockchip,use-v2-tuning; 1346 status = "disabled"; 1347 }; 1348 1349 sdmmc: mmc@ffaa0000 { 1350 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc"; 1351 reg = <0xffaa0000 0x4000>; 1352 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>, 1354 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 1355 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1356 fifo-depth = <0x100>; 1357 max-frequency = <200000000>; 1358 status = "disabled"; 1359 }; 1360 1361 sfc: spi@ffac0000 { 1362 compatible = "rockchip,sfc"; 1363 reg = <0xffac0000 0x4000>; 1364 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1366 clock-names = "clk_sfc", "hclk_sfc"; 1367 assigned-clocks = <&cru SCLK_SFC>; 1368 assigned-clock-rates = <75000000>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 rve: rve@ffad0000 { 1375 compatible = "rockchip,rve"; 1376 reg = <0xffad0000 0x1000>; 1377 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cru ACLK_IVE>, <&cru HCLK_IVE>; 1379 clock-names = "aclk_rve", "hclk_rve"; 1380 status = "disabled"; 1381 }; 1382 1383 i2s0_8ch: i2s@ffae0000 { 1384 compatible = "rockchip,rv1106-i2s-tdm"; 1385 reg = <0xffae0000 0x1000>; 1386 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1387 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>; 1388 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1389 dmas = <&dmac 22>, <&dmac 21>; 1390 dma-names = "tx", "rx"; 1391 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1392 reset-names = "tx-m", "rx-m"; 1393 rockchip,clk-trcm = <1>; 1394 #sound-dai-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 usbdrd: usbdrd { 1399 compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3"; 1400 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>, 1401 <&cru ACLK_USBOTG>; 1402 clock-names = "ref", "utmi", "bus"; 1403 #address-cells = <1>; 1404 #size-cells = <1>; 1405 ranges; 1406 status = "disabled"; 1407 1408 usbdrd_dwc3: usb@ffb00000 { 1409 compatible = "snps,dwc3"; 1410 reg = <0xffb00000 0x100000>; 1411 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1412 resets = <&cru SRST_A_USBOTG>; 1413 reset-names = "usb3-otg"; 1414 dr_mode = "otg"; 1415 maximum-speed = "high-speed"; 1416 phys = <&u2phy_otg>; 1417 phy-names = "usb2-phy"; 1418 phy_type = "utmi_wide"; 1419 snps,dis_enblslpm_quirk; 1420 snps,dis-u2-freeclk-exists-quirk; 1421 snps,dis_u2_susphy_quirk; 1422 snps,dis-del-phy-power-chg-quirk; 1423 snps,dis-tx-ipgap-linecheck-quirk; 1424 snps,usb2-gadget-lpm-disable; 1425 snps,usb2-lpm-disable; 1426 status = "disabled"; 1427 }; 1428 }; 1429 1430 pinctrl: pinctrl { 1431 compatible = "rockchip,rv1106-pinctrl"; 1432 rockchip,grf = <&ioc>; 1433 rockchip,pmu = <&pmuioc>; 1434 #address-cells = <1>; 1435 #size-cells = <1>; 1436 ranges; 1437 1438 gpio0: gpio@ff380000 { 1439 compatible = "rockchip,gpio-bank"; 1440 reg = <0xff380000 0x100>; 1441 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1442 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 1443 1444 gpio-controller; 1445 #gpio-cells = <2>; 1446 gpio-ranges = <&pinctrl 0 0 32>; 1447 interrupt-controller; 1448 #interrupt-cells = <2>; 1449 }; 1450 1451 gpio1: gpio@ff530000 { 1452 compatible = "rockchip,gpio-bank"; 1453 reg = <0xff530000 0x100>; 1454 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1456 1457 gpio-controller; 1458 #gpio-cells = <2>; 1459 gpio-ranges = <&pinctrl 0 32 32>; 1460 interrupt-controller; 1461 #interrupt-cells = <2>; 1462 }; 1463 1464 gpio2: gpio@ff540000 { 1465 compatible = "rockchip,gpio-bank"; 1466 reg = <0xff540000 0x100>; 1467 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1469 1470 gpio-controller; 1471 #gpio-cells = <2>; 1472 gpio-ranges = <&pinctrl 0 64 32>; 1473 interrupt-controller; 1474 #interrupt-cells = <2>; 1475 }; 1476 1477 gpio3: gpio@ff550000 { 1478 compatible = "rockchip,gpio-bank"; 1479 reg = <0xff550000 0x100>; 1480 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1482 1483 gpio-controller; 1484 #gpio-cells = <2>; 1485 gpio-ranges = <&pinctrl 0 96 32>; 1486 interrupt-controller; 1487 #interrupt-cells = <2>; 1488 }; 1489 1490 gpio4: gpio@ff560000 { 1491 compatible = "rockchip,gpio-bank"; 1492 reg = <0xff560000 0x100>; 1493 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1495 1496 gpio-controller; 1497 #gpio-cells = <2>; 1498 gpio-ranges = <&pinctrl 0 128 32>; 1499 interrupt-controller; 1500 #interrupt-cells = <2>; 1501 }; 1502 }; 1503}; 1504 1505#include "rv1106-pinctrl.dtsi" 1506
