Home
last modified time | relevance | path

Searched refs:div (Results 1 – 25 of 181) sorted by relevance

12345678

/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dclk.c35 u32 val, ctrl, xtal, pll, div; in get_clocks() local
45 div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
47 pll = xtal / div; in get_clocks()
50 div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
52 pll *= div; in get_clocks()
53 div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
55 if (!div) in get_clocks()
56 div = 1; in get_clocks()
57 pll >>= div; in get_clocks()
60 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c24 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
188 u32 sel, con, div; in rk3506_armclk_get_rate() local
193 div = (con & CLK_CORE_SRC_DIV_MASK) >> CLK_CORE_SRC_DIV_SHIFT; in rk3506_armclk_get_rate()
204 return DIV_TO_RATE(prate, div); in rk3506_armclk_get_rate()
212 u32 con, sel, div, old_div; in rk3506_armclk_set_rate() local
233 div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); in rk3506_armclk_set_rate()
237 div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); in rk3506_armclk_set_rate()
241 div = DIV_ROUND_UP(priv->gpll_hz, new_rate); in rk3506_armclk_set_rate()
244 assert(div - 1 <= 31); in rk3506_armclk_set_rate()
250 (div - 1) << CLK_CORE_SRC_DIV_SHIFT); in rk3506_armclk_set_rate()
[all …]
H A Dclk_rv1108.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
66 const struct pll_div *div) in rkclk_set_pll() argument
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
[all …]
H A Dclk_rk3562.c20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
205 u32 sel, con, div; in rk3562_bus_get_rate() local
212 div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
217 div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
222 div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
233 return DIV_TO_RATE(rate, div); in rk3562_bus_get_rate()
240 u32 sel, div; in rk3562_bus_set_rate() local
244 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_bus_set_rate()
247 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_bus_set_rate()
255 ((div - 1) << ACLK_BUS_DIV_SHIFT)); in rk3562_bus_set_rate()
[all …]
H A Dclk_rk3576.c22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
179 div = (con & ACLK_BUS_ROOT_DIV_MASK) >> in rk3576_bus_get_clk()
182 rate = DIV_TO_RATE(priv->cpll_hz , div); in rk3576_bus_get_clk()
184 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3576_bus_get_clk()
278 u32 con, sel, div, rate, prate; in rk3576_top_get_clk() local
283 div = (con & ACLK_TOP_DIV_MASK) >> in rk3576_top_get_clk()
293 return DIV_TO_RATE(prate, div); in rk3576_top_get_clk()
296 div = (con & ACLK_TOP_MID_DIV_MASK) >> in rk3576_top_get_clk()
304 return DIV_TO_RATE(prate, div); in rk3576_top_get_clk()
[all …]
H A Dclk_rk3588.c22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
286 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
291 div = (con & ACLK_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
299 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
302 div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
310 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
656 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
661 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3588_adc_get_clk()
668 return DIV_TO_RATE(prate, div); in rk3588_adc_get_clk()
671 div = (con & CLK_TSADC_DIV_MASK) >> in rk3588_adc_get_clk()
[all …]
H A Dclk_rk3036.c47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
63 const struct pll_div *div) in rkclk_set_pll() argument
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
75 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
90 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
246 uint div, mux; in rockchip_mmc_get_clk() local
[all …]
H A Dclk_rk3399.c46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll() argument
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
375 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
378 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
392 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
397 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
[all …]
H A Dclk_rk3368.c62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config() argument
165 div->nr = best_div->nr; in pll_para_config()
166 div->nf = best_div->nf; in pll_para_config()
167 div->no = best_div->no; in pll_para_config()
168 div->nb = best_div->nb; in pll_para_config()
186 div->no = no; in pll_para_config()
209 div->nr = nr; in pll_para_config()
210 div->nf = nf; in pll_para_config()
250 const struct pll_div *div) in rkclk_set_pll() argument
[all …]
H A Dclk_rk3328.c25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
170 u32 div, con; in rk3328_i2c_get_clk() local
175 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
179 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
183 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
187 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
194 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_i2c_get_clk()
262 u8 div; in rk3328_gmac2io_set_clk() local
269 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
270 if (div <= 0x1f) in rk3328_gmac2io_set_clk()
[all …]
H A Dclk_rk3288.c210 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
236 const struct pll_div *div) in rkclk_set_pll() argument
241 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
242 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
245 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
251 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
252 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
255 if (div->nb) in rkclk_set_pll()
256 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, div->nb - 1); in rkclk_set_pll()
258 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dclk.c35 u32 val, xtal, pll, div; in get_clocks() local
43 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
45 pll = xtal / div; in get_clocks()
48 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
50 pll *= div; in get_clocks()
51 div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
53 if (!div) in get_clocks()
54 div = 1; in get_clocks()
55 pll >>= div; in get_clocks()
60 div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/
H A Dclock.c138 unsigned long div; in s5pc110_get_arm_clk() local
142 div = readl(&clk->div0); in s5pc110_get_arm_clk()
145 apll_ratio = div & 0x7; in s5pc110_get_arm_clk()
158 unsigned long div; in s5pc100_get_arm_clk() local
162 div = readl(&clk->div0); in s5pc100_get_arm_clk()
165 arm_ratio = (div >> 4) & 0x7; in s5pc100_get_arm_clk()
167 apll_ratio = div & 0x1; in s5pc100_get_arm_clk()
181 uint div, d0_bus_ratio; in get_hclk() local
183 div = readl(&clk->div0); in get_hclk()
185 d0_bus_ratio = (div >> 8) & 0x7; in get_hclk()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c42 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
57 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> in mxs_get_pclk()
59 return XTAL_FREQ_MHZ / div; in mxs_get_pclk()
65 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; in mxs_get_pclk()
66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_pclk()
74 uint32_t div; in mxs_get_hclk() local
83 div = clkctrl & CLKCTRL_HBUS_DIV_MASK; in mxs_get_hclk()
84 return mxs_get_pclk() / div; in mxs_get_hclk()
92 uint32_t clkctrl, clkseq, div; in mxs_get_emiclk() local
100 div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> in mxs_get_emiclk()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/
H A Dgeneric.c74 ulong div; in imx_get_armclk() local
79 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) in imx_get_armclk()
82 return fref / div; in imx_get_armclk()
90 ulong div; in imx_get_ahbclk() local
92 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) in imx_get_ahbclk()
95 return fref / div; in imx_get_ahbclk()
108 ulong div; in imx_get_perclk() local
110 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); in imx_get_perclk()
111 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; in imx_get_perclk()
113 return fref / div; in imx_get_perclk()
[all …]
/rk3399_rockchip-uboot/lib/
H A Dtiny-printf.c43 unsigned long div) in div_out() argument
47 while (*num >= div) { in div_out()
48 *num -= div; in div_out()
170 unsigned long div; in pointer() local
198 div = 1UL << (sizeof(long) * 8 - 4); in pointer()
199 for (; div; div /= 0x10) in pointer()
200 div_out(info, &num, div); in pointer()
210 unsigned long div; in _vprintf() local
250 div = 1000000000; in _vprintf()
254 div *= div * 10; in _vprintf()
[all …]
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A Ddcu.c18 unsigned long long div; in dcu_set_pixel_clock() local
20 div = (unsigned long long)(gd->bus_clk / 1000); in dcu_set_pixel_clock()
21 div *= (unsigned long long)pixclock; in dcu_set_pixel_clock()
22 do_div(div, 1000000000); in dcu_set_pixel_clock()
24 return div; in dcu_set_pixel_clock()
/rk3399_rockchip-uboot/board/freescale/ls1021aiot/
H A Ddcu.c18 unsigned long long div; in dcu_set_pixel_clock() local
20 div = (unsigned long long)(gd->bus_clk / 1000); in dcu_set_pixel_clock()
21 div *= (unsigned long long)pixclock; in dcu_set_pixel_clock()
22 do_div(div, 1000000000); in dcu_set_pixel_clock()
24 return div; in dcu_set_pixel_clock()
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c117 unsigned int div; in exynos_get_pll_clk() local
159 div = PLL_DIV_1024; in exynos_get_pll_clk()
161 div = PLL_DIV_65535; in exynos_get_pll_clk()
164 div = PLL_DIV_65536; in exynos_get_pll_clk()
168 fout = (m + k / div) * (freq / (p * (1 << s))); in exynos_get_pll_clk()
369 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate() local
379 div = readl(&clk->div_peric0); in exynos5_get_periph_rate()
387 div = readl(&clk->div_peric3); in exynos5_get_periph_rate()
391 div = sub_div = readl(&clk->div_mau); in exynos5_get_periph_rate()
395 div = sub_div = readl(&clk->div_peric1); in exynos5_get_periph_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
113 if (divider_exists(&cd->div)) { in peri_clk_enable()
114 reg = readl(base + cd->div.offset); in peri_clk_enable()
115 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
116 c->div - 1); in peri_clk_enable()
117 writel(reg, base + cd->div.offset); in peri_clk_enable()
166 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
183 div = ref->clk.rate / rate; in peri_clk_set_rate()
184 if (div == 0) in peri_clk_set_rate()
185 div = 1; in peri_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
113 if (divider_exists(&cd->div)) { in peri_clk_enable()
114 reg = readl(base + cd->div.offset); in peri_clk_enable()
115 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
116 c->div - 1); in peri_clk_enable()
117 writel(reg, base + cd->div.offset); in peri_clk_enable()
166 unsigned long new_rate = 0, div = 1; in peri_clk_set_rate() local
183 div = ref->clk.rate / rate; in peri_clk_set_rate()
184 if (div == 0) in peri_clk_set_rate()
185 div = 1; in peri_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c299 u32 mux, div = 0; in rk628_cru_clk_get_rate_sclk_vop() local
309 rk628_i2c_read(rk628, CRU_CLKSEL_CON13, &div); in rk628_cru_clk_get_rate_sclk_vop()
310 m = div >> 16 & 0xffff; in rk628_cru_clk_get_rate_sclk_vop()
311 n = div & 0xffff; in rk628_cru_clk_get_rate_sclk_vop()
320 u32 mux = 0, div = 0; in rk628_cru_clk_get_rate_clk_imodet() local
330 rk628_i2c_read(rk628, CRU_CLKSEL_CON05, &div); in rk628_cru_clk_get_rate_clk_imodet()
331 n = div & 0x1f; in rk628_cru_clk_get_rate_clk_imodet()
362 u32 mux, div = 0; in rk628_cru_clk_get_rate_uart_src() local
371 rk628_i2c_read(rk628, CRU_CLKSEL_CON21, &div); in rk628_cru_clk_get_rate_uart_src()
372 div &= CLK_UART_SRC_DIV_MASK; in rk628_cru_clk_get_rate_uart_src()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dam33xx-clocks.dtsi24 clock-div = <1>;
32 clock-div = <1>;
40 clock-div = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
88 clock-div = <1>;
96 clock-div = <1>;
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/s5p-common/
H A Dpwm.c45 unsigned int div; in pwm_calc_tin() local
49 for (div = 2; div <= 16; div *= 2) { in pwm_calc_tin()
50 if ((tin_parent_rate / (div << 16)) < freq) in pwm_calc_tin()
51 return tin_parent_rate / div; in pwm_calc_tin()
115 int pwm_init(int pwm_id, int div, int invert) in pwm_init() argument
141 val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); in pwm_init()
153 ((prescaler + 1) * (1 << div)); in pwm_init()
/rk3399_rockchip-uboot/arch/arm/mach-at91/armv7/
H A Dclock.c42 unsigned mul, div; in at91_pll_rate() local
44 div = reg & 0xff; in at91_pll_rate()
46 if (div && mul) { in at91_pll_rate()
47 freq /= div; in at91_pll_rate()
153 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) in at91_enable_periph_generated_clk() argument
162 if (div > 0xff) in at91_enable_periph_generated_clk()
200 AT91_PMC_PCR_GCKDIV_(div) | in at91_enable_periph_generated_clk()
219 u32 regval, clk_source, div; in at91_get_periph_generated_clk() local
251 div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET); in at91_get_periph_generated_clk()
252 div += 1; in at91_get_periph_generated_clk()
[all …]

12345678