210 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
236 			 const struct pll_div *div)  in rkclk_set_pll()  argument
241 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;  in rkclk_set_pll()
242 	uint output_hz = vco_hz / div->no;  in rkclk_set_pll()
245 	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);  in rkclk_set_pll()
251 		     ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));  in rkclk_set_pll()
252 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);  in rkclk_set_pll()
255 	if (div->nb)  in rkclk_set_pll()
256 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, div->nb - 1);  in rkclk_set_pll()
258 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);  in rkclk_set_pll()
355 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()  argument
379 		div->nr = best_div->nr;  in pll_para_config()
380 		div->nf = best_div->nf;  in pll_para_config()
381 		div->no = best_div->no;  in pll_para_config()
382 		div->nb = best_div->nb;  in pll_para_config()
400 	div->no = no;  in pll_para_config()
423 		div->nr = nr;  in pll_para_config()
424 		div->nf = nf;  in pll_para_config()
450 		u8 div;  in rockchip_mac_set_clk()  local
461 		div = DIV_ROUND_UP(pll_rate, freq) - 1;  in rockchip_mac_set_clk()
462 		if (div <= 0x1f)  in rockchip_mac_set_clk()
464 				     div << MAC_DIV_CON_SHIFT);  in rockchip_mac_set_clk()
466 			debug("Unsupported div for gmac:%d\n", div);  in rockchip_mac_set_clk()
468 		return DIV_TO_RATE(pll_rate, div);  in rockchip_mac_set_clk()
718 	uint div, mux;  in rockchip_mmc_get_clk()  local
727 		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;  in rockchip_mmc_get_clk()
733 		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;  in rockchip_mmc_get_clk()
739 		div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;  in rockchip_mmc_get_clk()
746 	return DIV_TO_RATE(src_rate, div) / 2;  in rockchip_mmc_get_clk()
802 	uint div, mux;  in rockchip_spi_get_clk()  local
809 		div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;  in rockchip_spi_get_clk()
814 		div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;  in rockchip_spi_get_clk()
819 		div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;  in rockchip_spi_get_clk()
826 	return DIV_TO_RATE(gclk_rate, div);  in rockchip_spi_get_clk()
865 	uint div, mux;  in rockchip_aclk_peri_get_clk()  local
871 	div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;  in rockchip_aclk_peri_get_clk()
876 	rate = DIV_TO_RATE(parent_rate, div);  in rockchip_aclk_peri_get_clk()
883 	uint div, mux;  in rockchip_aclk_cpu_get_clk()  local
889 	div = (con & PD_BUS_ACLK_DIV0_MASK) >> PD_BUS_ACLK_DIV0_SHIFT;  in rockchip_aclk_cpu_get_clk()
894 	parent_rate = DIV_TO_RATE(parent_rate, div);  in rockchip_aclk_cpu_get_clk()
896 	div = (con & PD_BUS_ACLK_DIV1_MASK) >> PD_BUS_ACLK_DIV1_SHIFT;  in rockchip_aclk_cpu_get_clk()
897 	rate = DIV_TO_RATE(parent_rate, div);  in rockchip_aclk_cpu_get_clk()
904 	uint div;  in rockchip_pclk_peri_get_clk()  local
910 	div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;  in rockchip_pclk_peri_get_clk()
911 	rate = parent_rate / (1 << div);  in rockchip_pclk_peri_get_clk()
918 	uint div;  in rockchip_pclk_cpu_get_clk()  local
924 	div = (con & PD_BUS_PCLK_DIV_MASK) >> PD_BUS_PCLK_DIV_SHIFT;  in rockchip_pclk_cpu_get_clk()
925 	rate = DIV_TO_RATE(parent_rate, div);  in rockchip_pclk_cpu_get_clk()
948 	u32 div, val;  in rockchip_saradc_get_clk()  local
951 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rockchip_saradc_get_clk()
954 	return DIV_TO_RATE(OSC_HZ, div);  in rockchip_saradc_get_clk()
973 	u32 div, val;  in rockchip_tsadc_get_clk()  local
976 	div = bitfield_extract(val, CLK_TSADC_DIV_CON_SHIFT,  in rockchip_tsadc_get_clk()
979 	return DIV_TO_RATE(32768, div);  in rockchip_tsadc_get_clk()
1000 	u32 div, val;  in rockchip_crypto_get_clk()  local
1003 	div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT;  in rockchip_crypto_get_clk()
1005 	return DIV_TO_RATE(rockchip_aclk_cpu_get_clk(cru), div);  in rockchip_crypto_get_clk()
1026 	u32 div, con, parent;  in rk3288_alive_get_clk()  local
1029 	div = (con & PCLK_ALIVE_DIV_CON_MASK) >>  in rk3288_alive_get_clk()
1032 	return DIV_TO_RATE(parent, div);  in rk3288_alive_get_clk()