25 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
170 	u32 div, con;  in rk3328_i2c_get_clk()  local
175 		div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;  in rk3328_i2c_get_clk()
179 		div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;  in rk3328_i2c_get_clk()
183 		div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;  in rk3328_i2c_get_clk()
187 		div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;  in rk3328_i2c_get_clk()
194 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_i2c_get_clk()
262 		u8 div;  in rk3328_gmac2io_set_clk()  local
269 		div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rk3328_gmac2io_set_clk()
270 		if (div <= 0x1f)  in rk3328_gmac2io_set_clk()
272 				     div << GMAC2IO_CLK_DIV_SHIFT);  in rk3328_gmac2io_set_clk()
274 			debug("Unsupported div for gmac:%d\n", div);  in rk3328_gmac2io_set_clk()
276 		return DIV_TO_RATE(pll_rate, div);  in rk3328_gmac2io_set_clk()
286 	u8 div;  in rk3328_gmac2phy_src_set_clk()  local
293 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rk3328_gmac2phy_src_set_clk()
294 	if (div <= 0x1f)  in rk3328_gmac2phy_src_set_clk()
296 			     div << GMAC2PHY_CLK_DIV_SHIFT);  in rk3328_gmac2phy_src_set_clk()
298 		debug("Unsupported div for gmac:%d\n", div);  in rk3328_gmac2phy_src_set_clk()
300 	return DIV_TO_RATE(pll_rate, div);  in rk3328_gmac2phy_src_set_clk()
319 	u32 div, con, con_id;  in rk3328_mmc_get_clk()  local
335 	div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;  in rk3328_mmc_get_clk()
339 		return DIV_TO_RATE(OSC_HZ, div) / 2;  in rk3328_mmc_get_clk()
341 		return DIV_TO_RATE(priv->gpll_hz, div) / 2;  in rk3328_mmc_get_clk()
387 	u32 div, con, mux, p_rate;  in rk3328_spi_get_clk()  local
390 	div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;  in rk3328_spi_get_clk()
397 	return DIV_TO_RATE(p_rate, div);  in rk3328_spi_get_clk()
403 	u32 div = priv->gpll_hz / hz;  in rk3328_spi_set_clk()  local
408 		     (div - 1) << CLK_SPI_DIV_CON_SHIFT);  in rk3328_spi_set_clk()
410 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_spi_set_clk()
417 	u32 div, con;  in rk3328_pwm_get_clk()  local
420 	div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;  in rk3328_pwm_get_clk()
422 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_pwm_get_clk()
428 	u32 div = priv->gpll_hz / hz;  in rk3328_pwm_set_clk()  local
433 		     (div - 1) << CLK_PWM_DIV_CON_SHIFT);  in rk3328_pwm_set_clk()
435 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_pwm_set_clk()
441 	u32 div, val;  in rk3328_saradc_get_clk()  local
444 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rk3328_saradc_get_clk()
447 	return DIV_TO_RATE(OSC_HZ, div);  in rk3328_saradc_get_clk()
468 	u32 div, val;  in rk3328_tsadc_get_clk()  local
471 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rk3328_tsadc_get_clk()
474 	return DIV_TO_RATE(OSC_HZ, div);  in rk3328_tsadc_get_clk()
495 	u32 div, con, parent;  in rk3328_vop_get_clk()  local
501 		div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT;  in rk3328_vop_get_clk()
507 		div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT;  in rk3328_vop_get_clk()
514 		div = (con & HCLK_VIO_DIV_CON_MASK) >> HCLK_VIO_DIV_CON_SHIFT;  in rk3328_vop_get_clk()
520 	return DIV_TO_RATE(parent, div);  in rk3328_vop_get_clk()
587 	u32 div, con, parent;  in rk3328_bus_get_clk()  local
592 		div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT;  in rk3328_bus_get_clk()
597 		div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT;  in rk3328_bus_get_clk()
602 		div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT;  in rk3328_bus_get_clk()
609 	return DIV_TO_RATE(parent, div);  in rk3328_bus_get_clk()
661 	u32 div, con, parent;  in rk3328_peri_get_clk()  local
666 		div = (con & ACLK_PERI_DIV_CON_MASK) >> ACLK_PERI_DIV_CON_SHIFT;  in rk3328_peri_get_clk()
671 		div = (con & HCLK_PERI_DIV_CON_MASK) >> HCLK_PERI_DIV_CON_SHIFT;  in rk3328_peri_get_clk()
676 		div = (con & PCLK_PERI_DIV_CON_MASK) >> PCLK_PERI_DIV_CON_SHIFT;  in rk3328_peri_get_clk()
683 	return DIV_TO_RATE(parent, div);  in rk3328_peri_get_clk()
737 	u32 div, con, parent;  in rk3328_crypto_get_clk()  local
742 		div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT;  in rk3328_crypto_get_clk()
749 	return DIV_TO_RATE(parent, div);  in rk3328_crypto_get_clk()