46 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)  in rkclk_set_pll()  argument
369 	u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;  in rkclk_set_pll()
370 	u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;  in rkclk_set_pll()
374 			   pll_con, div->fbdiv, div->refdiv, div->postdiv1,  in rkclk_set_pll()
375 			   div->postdiv2, vco_khz, output_khz);  in rkclk_set_pll()
378 	       div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);  in rkclk_set_pll()
392 		     div->fbdiv << PLL_FBDIV_SHIFT);  in rkclk_set_pll()
396 		     (div->postdiv2 << PLL_POSTDIV2_SHIFT) |  in rkclk_set_pll()
397 		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) |  in rkclk_set_pll()
398 		     (div->refdiv << PLL_REFDIV_SHIFT));  in rkclk_set_pll()
445 static int pll_para_config(u32 freq_hz, struct pll_div *div)  in pll_para_config()  argument
476 	div->postdiv1 = postdiv1;  in pll_para_config()
477 	div->postdiv2 = postdiv2;  in pll_para_config()
496 		div->refdiv = refdiv;  in pll_para_config()
497 		div->fbdiv = fbdiv;  in pll_para_config()
586 	u32 div, con;  in rk3399_i2c_get_clk()  local
591 		div = I2C_CLK_DIV_VALUE(con, 1);  in rk3399_i2c_get_clk()
595 		div = I2C_CLK_DIV_VALUE(con, 2);  in rk3399_i2c_get_clk()
599 		div = I2C_CLK_DIV_VALUE(con, 3);  in rk3399_i2c_get_clk()
603 		div = I2C_CLK_DIV_VALUE(con, 5);  in rk3399_i2c_get_clk()
607 		div = I2C_CLK_DIV_VALUE(con, 6);  in rk3399_i2c_get_clk()
611 		div = I2C_CLK_DIV_VALUE(con, 7);  in rk3399_i2c_get_clk()
618 	return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_i2c_get_clk()
701 	u32 div, val;  in rk3399_spi_get_clk()  local
714 	div = bitfield_extract(val, spiclk->div_shift,  in rk3399_spi_get_clk()
717 	return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_spi_get_clk()
754 	u32 div = 1;  in rk3399_vop_set_clk()  local
769 	div = GPLL_HZ / aclk_vop;  in rk3399_vop_set_clk()
770 	assert(div - 1 <= 31);  in rk3399_vop_set_clk()
775 		     (div - 1) << ACLK_VOP_DIV_CON_SHIFT);  in rk3399_vop_set_clk()
779 		     (div - 1) << ACLK_VOP_DIV_CON_SHIFT);  in rk3399_vop_set_clk()
801 	u32 div, con;  in rk3399_mmc_get_clk()  local
808 		div = 2;  in rk3399_mmc_get_clk()
812 		div = 1;  in rk3399_mmc_get_clk()
818 	div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;  in rk3399_mmc_get_clk()
821 		return DIV_TO_RATE(OSC_HZ, div);  in rk3399_mmc_get_clk()
823 		return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_mmc_get_clk()
960 	u32 div, val;  in rk3399_saradc_get_clk()  local
963 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rk3399_saradc_get_clk()
966 	return DIV_TO_RATE(OSC_HZ, div);  in rk3399_saradc_get_clk()
985 	u32 div, val;  in rk3399_tsadc_get_clk()  local
988 	div = bitfield_extract(val, CLK_TSADC_SEL_SHIFT,  in rk3399_tsadc_get_clk()
991 	return DIV_TO_RATE(OSC_HZ, div);  in rk3399_tsadc_get_clk()
1012 	u32 div, con, parent;  in rk3399_crypto_get_clk()  local
1017 		div = (con & CRYPTO0_DIV_MASK) >> CRYPTO0_DIV_SHIFT;  in rk3399_crypto_get_clk()
1022 		div = (con & CRYPTO1_DIV_MASK) >> CRYPTO1_DIV_SHIFT;  in rk3399_crypto_get_clk()
1029 	return DIV_TO_RATE(parent, div);  in rk3399_crypto_get_clk()
1070 	u32 div, con, parent;  in rk3399_peri_get_clk()  local
1075 		div = (con & ACLK_PERIHP_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1081 		div = (con & PCLK_PERIHP_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1087 		div = (con & HCLK_PERIHP_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1093 		div = (con & ACLK_PERILP0_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1099 		div = (con & HCLK_PERILP0_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1105 		div = (con & PCLK_PERILP0_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1111 		div = (con & HCLK_PERILP1_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1117 		div = (con & PCLK_PERILP1_DIV_CON_MASK) >>  in rk3399_peri_get_clk()
1125 	return DIV_TO_RATE(parent, div);  in rk3399_peri_get_clk()
1131 	u32 div, con, parent;  in rk3399_alive_get_clk()  local
1134 	div = (con & PCLK_ALIVE_DIV_CON_MASK) >>  in rk3399_alive_get_clk()
1137 	return DIV_TO_RATE(parent, div);  in rk3399_alive_get_clk()
1601 	u32 div, con;  in rk3399_i2c_get_pmuclk()  local
1606 		div = I2C_CLK_DIV_VALUE(con, 0);  in rk3399_i2c_get_pmuclk()
1610 		div = I2C_CLK_DIV_VALUE(con, 4);  in rk3399_i2c_get_pmuclk()
1614 		div = I2C_CLK_DIV_VALUE(con, 8);  in rk3399_i2c_get_pmuclk()
1621 	return DIV_TO_RATE(PPLL_HZ, div);  in rk3399_i2c_get_pmuclk()
1655 	u32 div, con;  in rk3399_pwm_get_clk()  local
1659 	div = con & PMU_PCLK_DIV_CON_MASK;  in rk3399_pwm_get_clk()
1661 	return DIV_TO_RATE(PPLL_HZ, div);  in rk3399_pwm_get_clk()