62 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()  argument
165 		div->nr = best_div->nr;  in pll_para_config()
166 		div->nf = best_div->nf;  in pll_para_config()
167 		div->no = best_div->no;  in pll_para_config()
168 		div->nb = best_div->nb;  in pll_para_config()
186 	div->no = no;  in pll_para_config()
209 		div->nr = nr;  in pll_para_config()
210 		div->nf = nf;  in pll_para_config()
250 			 const struct pll_div *div)  in rkclk_set_pll()  argument
254 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;  in rkclk_set_pll()
255 	uint output_hz = vco_hz / div->no;  in rkclk_set_pll()
258 	      pll, div->nf, div->nr, div->no, vco_hz, output_hz);  in rkclk_set_pll()
265 		     ((div->nr - 1) << PLL_NR_SHIFT) |  in rkclk_set_pll()
266 		     ((div->no - 1) << PLL_OD_SHIFT));  in rkclk_set_pll()
267 	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);  in rkclk_set_pll()
272 	if (div->nb)  in rkclk_set_pll()
273 		clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, div->nb - 1);  in rkclk_set_pll()
275 		clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);  in rkclk_set_pll()
295 	u32 div, con, con_id, rate;  in rk3368_mmc_get_clk()  local
327 	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;  in rk3368_mmc_get_clk()
328 	rate = DIV_TO_RATE(pll_rate, div);  in rk3368_mmc_get_clk()
358 		u32 div = DIV_ROUND_UP(parent_rate, rate);  in rk3368_mmc_find_best_rate_and_parent()  local
359 		u32 adj_div = div;  in rk3368_mmc_find_best_rate_and_parent()
363 		      __func__, rate, parents[i].mux, parents[i].rate, div);  in rk3368_mmc_find_best_rate_and_parent()
366 		if ((div - 1) > MMC_CLK_DIV_MASK)  in rk3368_mmc_find_best_rate_and_parent()
376 		*best_div = div - 1;  in rk3368_mmc_find_best_rate_and_parent()
390 	u32 con_id, mux = 0, div = 0;  in rk3368_mmc_set_clk()  local
393 	rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);  in rk3368_mmc_set_clk()
411 		     mux | div);  in rk3368_mmc_set_clk()
462 		u8 div;  in rk3368_gmac_set_clk()  local
474 		div = DIV_ROUND_UP(pll_rate, set_rate) - 1;  in rk3368_gmac_set_clk()
475 		if (div <= 0x1f)  in rk3368_gmac_set_clk()
477 				     div << GMAC_DIV_CON_SHIFT);  in rk3368_gmac_set_clk()
479 			debug("Unsupported div for gmac:%d\n", div);  in rk3368_gmac_set_clk()
481 		return DIV_TO_RATE(pll_rate, div);  in rk3368_gmac_set_clk()
517 	u32 div, val;  in rk3368_spi_get_clk()  local
530 	div = extract_bits(val, 7, spiclk->div_shift);  in rk3368_spi_get_clk()
532 	debug("%s: div 0x%x\n", __func__, div);  in rk3368_spi_get_clk()
533 	return DIV_TO_RATE(GPLL_HZ, div);  in rk3368_spi_get_clk()
565 	u32 div, val;  in rk3368_saradc_get_clk()  local
568 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rk3368_saradc_get_clk()
571 	return DIV_TO_RATE(OSC_HZ, div);  in rk3368_saradc_get_clk()
590 	u32 div, con, parent;  in rk3368_bus_get_clk()  local
595 		div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT;  in rk3368_bus_get_clk()
600 		div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT;  in rk3368_bus_get_clk()
609 		div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT;  in rk3368_bus_get_clk()
616 	return DIV_TO_RATE(parent, div);  in rk3368_bus_get_clk()
664 	u32 div, con, parent;  in rk3368_peri_get_clk()  local
669 		div = (con & ACLK_PERI_DIV_CON_MASK) >> ACLK_PERI_DIV_CON_SHIFT;  in rk3368_peri_get_clk()
674 		div = (con & HCLK_PERI_DIV_CON_MASK) >> HCLK_PERI_DIV_CON_SHIFT;  in rk3368_peri_get_clk()
683 		div = (con & PCLK_PERI_DIV_CON_MASK) >> PCLK_PERI_DIV_CON_SHIFT;  in rk3368_peri_get_clk()
690 	return DIV_TO_RATE(parent, div);  in rk3368_peri_get_clk()
740 	u32 div, con, parent, sel;  in rk3368_vop_get_clk()  local
745 		div = con & DCLK_VOP_DIV_MASK;  in rk3368_vop_get_clk()
750 		div = con & ACLK_VOP_DIV_MASK;  in rk3368_vop_get_clk()
765 	return DIV_TO_RATE(parent, div);  in rk3368_vop_get_clk()
828 	u32 div, con, parent;  in rk3368_alive_get_clk()  local
831 	div = (con & PCLK_ALIVE_DIV_CON_MASK) >>  in rk3368_alive_get_clk()
834 	return DIV_TO_RATE(parent, div);  in rk3368_alive_get_clk()
840 	u32 div, val;  in rk3368_crypto_get_rate()  local
843 	div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT;  in rk3368_crypto_get_rate()
845 	return DIV_TO_RATE(rk3368_bus_get_clk(priv->cru, ACLK_BUS), div);  in rk3368_crypto_get_rate()