22 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
172 	u32 con, sel, div, rate;  in rk3576_bus_get_clk()  local
179 		div = (con & ACLK_BUS_ROOT_DIV_MASK) >>  in rk3576_bus_get_clk()
182 			rate = DIV_TO_RATE(priv->cpll_hz , div);  in rk3576_bus_get_clk()
184 			rate = DIV_TO_RATE(priv->gpll_hz, div);  in rk3576_bus_get_clk()
278 	u32 con, sel, div, rate, prate;  in rk3576_top_get_clk()  local
283 		div = (con & ACLK_TOP_DIV_MASK) >>  in rk3576_top_get_clk()
293 		return DIV_TO_RATE(prate, div);  in rk3576_top_get_clk()
296 		div = (con & ACLK_TOP_MID_DIV_MASK) >>  in rk3576_top_get_clk()
304 		return DIV_TO_RATE(prate, div);  in rk3576_top_get_clk()
694 	u32 div, sel, con, prate;  in rk3576_adc_get_clk()  local
699 		div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;  in rk3576_adc_get_clk()
706 		return DIV_TO_RATE(prate, div);  in rk3576_adc_get_clk()
709 		div = (con & CLK_TSADC_DIV_MASK) >>  in rk3576_adc_get_clk()
712 		return DIV_TO_RATE(prate, div);  in rk3576_adc_get_clk()
765 	u32 sel, con, prate, div = 0;  in rk3576_mmc_get_clk()  local
771 		div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;  in rk3576_mmc_get_clk()
780 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
784 		div = (con & CCLK_SDMMC0_SRC_DIV_MASK) >> CCLK_SDMMC0_SRC_DIV_SHIFT;  in rk3576_mmc_get_clk()
793 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
797 		div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;  in rk3576_mmc_get_clk()
806 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
819 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
822 		div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;  in rk3576_mmc_get_clk()
831 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
834 		div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;  in rk3576_mmc_get_clk()
843 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
846 		div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;  in rk3576_mmc_get_clk()
852 		return DIV_TO_RATE(prate, div);  in rk3576_mmc_get_clk()
863 	int src_clk, div = 0;  in rk3576_mmc_set_clk()  local
876 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_mmc_set_clk()
879 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_mmc_set_clk()
882 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_mmc_set_clk()
898 			div = DIV_ROUND_UP(priv->spll_hz, rate);  in rk3576_mmc_set_clk()
901 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_mmc_set_clk()
915 			     (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);  in rk3576_mmc_set_clk()
923 			     (div - 1) << CCLK_SDMMC0_SRC_DIV_SHIFT);  in rk3576_mmc_set_clk()
931 			     (div - 1) << CCLK_EMMC_DIV_SHIFT);  in rk3576_mmc_set_clk()
938 			     (div - 1) << SCLK_FSPI_DIV_SHIFT);  in rk3576_mmc_set_clk()
945 			     (div - 1) << SCLK_FSPI_DIV_SHIFT);  in rk3576_mmc_set_clk()
957 			     (div - 1) << DCLK_DECOM_DIV_SHIFT);  in rk3576_mmc_set_clk()
972 	u32 div, sel, con, parent = 0;  in rk3576_aclk_vop_get_clk()  local
978 		div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;  in rk3576_aclk_vop_get_clk()
990 		return DIV_TO_RATE(parent, div);  in rk3576_aclk_vop_get_clk()
993 		div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;  in rk3576_aclk_vop_get_clk()
1003 		return DIV_TO_RATE(parent, div);  in rk3576_aclk_vop_get_clk()
1006 		div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;  in rk3576_aclk_vop_get_clk()
1016 		return DIV_TO_RATE(parent, div);  in rk3576_aclk_vop_get_clk()
1047 	int src_clk, div;  in rk3576_aclk_vop_set_clk()  local
1054 			div = 1;  in rk3576_aclk_vop_set_clk()
1057 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1060 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1066 			     (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);  in rk3576_aclk_vop_set_clk()
1071 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1074 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1080 			     (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);  in rk3576_aclk_vop_set_clk()
1085 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1088 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1094 			     (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);  in rk3576_aclk_vop_set_clk()
1131 	u32 div, sel, con, parent;  in rk3576_dclk_vop_get_clk()  local
1137 		div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;  in rk3576_dclk_vop_get_clk()
1143 		div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;  in rk3576_dclk_vop_get_clk()
1149 		div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;  in rk3576_dclk_vop_get_clk()
1167 	return DIV_TO_RATE(parent, div);  in rk3576_dclk_vop_get_clk()
1177 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3576_dclk_vop_set_clk()  local
1216 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1220 				     ((div - 1) << div_shift));  in rk3576_dclk_vop_set_clk()
1222 			div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, rate);  in rk3576_dclk_vop_set_clk()
1223 			if (div % 2)  in rk3576_dclk_vop_set_clk()
1224 				div = div + 1;  in rk3576_dclk_vop_set_clk()
1228 				     ((div - 1) << div_shift));  in rk3576_dclk_vop_set_clk()
1230 					      priv->cru, VPLL, div * rate);  in rk3576_dclk_vop_set_clk()
1257 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1258 			if (div > 255)  in rk3576_dclk_vop_set_clk()
1260 			now = pll_rate / div;  in rk3576_dclk_vop_set_clk()
1263 				best_div = div;  in rk3576_dclk_vop_set_clk()
1286 	u32 div, sel, con, parent;  in rk3576_clk_csihost_get_clk()  local
1291 		div = (con & CLK_DSIHOST0_DIV_MASK) >> CLK_DSIHOST0_DIV_SHIFT;  in rk3576_clk_csihost_get_clk()
1311 	return DIV_TO_RATE(parent, div);  in rk3576_clk_csihost_get_clk()
1319 	u32 i, con, div, best_div = 0, best_sel = 0;  in rk3576_clk_csihost_set_clk()  local
1357 		div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_clk_csihost_set_clk()
1358 		if (div > 255)  in rk3576_clk_csihost_set_clk()
1360 		now = pll_rate / div;  in rk3576_clk_csihost_set_clk()
1363 			best_div = div;  in rk3576_clk_csihost_set_clk()
1384 	u32 div, sel, con, parent;  in rk3576_dclk_ebc_get_clk()  local
1390 		div = (con & DCLK_EBC_DIV_MASK) >> DCLK_EBC_DIV_SHIFT;  in rk3576_dclk_ebc_get_clk()
1406 		return DIV_TO_RATE(parent, div);  in rk3576_dclk_ebc_get_clk()
1409 		div = readl(&cru->clksel_con[122]);  in rk3576_dclk_ebc_get_clk()
1422 		n = div & CLK_UART_FRAC_NUMERATOR_MASK;  in rk3576_dclk_ebc_get_clk()
1424 		m = div & CLK_UART_FRAC_DENOMINATOR_MASK;  in rk3576_dclk_ebc_get_clk()
1437 	u32 i, con, sel, div, best_div = 0, best_sel = 0;  in rk3576_dclk_ebc_set_clk()  local
1449 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1452 					     (div - 1) << DCLK_EBC_DIV_SHIFT);  in rk3576_dclk_ebc_set_clk()
1454 				div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ,  in rk3576_dclk_ebc_set_clk()
1456 				if (div % 2)  in rk3576_dclk_ebc_set_clk()
1457 					div = div + 1;  in rk3576_dclk_ebc_set_clk()
1460 					     (div - 1) << DCLK_EBC_DIV_SHIFT);  in rk3576_dclk_ebc_set_clk()
1463 						      VPLL, div * rate);  in rk3576_dclk_ebc_set_clk()
1470 			div = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC) / rate;  in rk3576_dclk_ebc_set_clk()
1473 				     (div - 1) << DCLK_EBC_DIV_SHIFT);  in rk3576_dclk_ebc_set_clk()
1497 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1498 				if (div > 255)  in rk3576_dclk_ebc_set_clk()
1500 				now = pll_rate / div;  in rk3576_dclk_ebc_set_clk()
1503 					best_div = div;  in rk3576_dclk_ebc_set_clk()
1525 		div = 1;  in rk3576_dclk_ebc_set_clk()
1561 	u32 con, div, src, p_rate;  in rk3576_gmac_get_clk()  local
1567 		div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;  in rk3576_gmac_get_clk()
1575 		return DIV_TO_RATE(p_rate, div);  in rk3576_gmac_get_clk()
1579 		div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;  in rk3576_gmac_get_clk()
1587 		return DIV_TO_RATE(p_rate, div);  in rk3576_gmac_get_clk()
1590 		div = (con & CLK_GMAC0_125M_DIV_MASK) >> CLK_GMAC0_125M_DIV_SHIFT;  in rk3576_gmac_get_clk()
1591 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3576_gmac_get_clk()
1594 		div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;  in rk3576_gmac_get_clk()
1595 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3576_gmac_get_clk()
1605 	int div, src;  in rk3576_gmac_set_clk()  local
1607 	div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_gmac_set_clk()
1614 			div = 1;  in rk3576_gmac_set_clk()
1617 			div = priv->gpll_hz / rate;  in rk3576_gmac_set_clk()
1620 			div = priv->cpll_hz / rate;  in rk3576_gmac_set_clk()
1625 			     (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);  in rk3576_gmac_set_clk()
1631 			div = 1;  in rk3576_gmac_set_clk()
1634 			div = priv->gpll_hz / rate;  in rk3576_gmac_set_clk()
1637 			div = priv->cpll_hz / rate;  in rk3576_gmac_set_clk()
1642 			     (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);  in rk3576_gmac_set_clk()
1648 			     (div - 1) << CLK_GMAC0_125M_DIV_SHIFT);  in rk3576_gmac_set_clk()
1653 			     (div - 1) << CLK_GMAC1_125M_DIV_SHIFT);  in rk3576_gmac_set_clk()
1764 	u32 con, div, src, p_rate;  in rk3576_uart_get_rate()  local
1812 		div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT;  in rk3576_uart_get_rate()
1815 		div = (con & CLK_UART_DIV_MASK) >> CLK_UART_DIV_SHIFT;  in rk3576_uart_get_rate()
1832 	return DIV_TO_RATE(p_rate, div);  in rk3576_uart_get_rate()
1839 	u32 reg, clk_src = 0, div = 0;  in rk3576_uart_set_rate()  local
1843 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_uart_set_rate()
1846 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_uart_set_rate()
1849 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0), rate);  in rk3576_uart_set_rate()
1852 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1), rate);  in rk3576_uart_set_rate()
1855 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2), rate);  in rk3576_uart_set_rate()
1858 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_uart_set_rate()
1876 		     ((div - 1) << CLK_UART1_SRC_DIV_SHIFT));  in rk3576_uart_set_rate()
1920 		     ((div - 1) << CLK_UART_DIV_SHIFT));  in rk3576_uart_set_rate()
1929 	u32 reg, con, div, src, p_rate;  in rk3576_ref_clkout_get_clk()  local
1945 	div = (con & REF_CLK0_OUT_PLL_DIV_MASK) >> REF_CLK0_OUT_PLL_DIV_SHIFT;  in rk3576_ref_clkout_get_clk()
1959 	return DIV_TO_RATE(p_rate, div);  in rk3576_ref_clkout_get_clk()
1967 	u32 i, con, div, best_div = 0, best_sel = 0;  in rk3576_ref_clkout_set_clk()  local
2008 		div = DIV_ROUND_UP(p_rate, rate);  in rk3576_ref_clkout_set_clk()
2009 		if (div > 255)  in rk3576_ref_clkout_set_clk()
2011 		now = p_rate / div;  in rk3576_ref_clkout_set_clk()
2014 			best_div = div;  in rk3576_ref_clkout_set_clk()
2039 	u32 src, div;  in rk3576_ufs_ref_get_rate()  local
2042 	div= readl(&cru->pmuclksel_con[1]) & 0xff;  in rk3576_ufs_ref_get_rate()
2046 		return priv->ppll_hz / (div + 1);  in rk3576_ufs_ref_get_rate()