22 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
286 	u32 con, sel, div, rate, prate;  in rk3588_top_get_clk()  local
291 		div = (con & ACLK_TOP_ROOT_DIV_MASK) >>  in rk3588_top_get_clk()
299 		return DIV_TO_RATE(prate, div);  in rk3588_top_get_clk()
302 		div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >>  in rk3588_top_get_clk()
310 		return DIV_TO_RATE(prate, div);  in rk3588_top_get_clk()
656 	u32 div, sel, con, prate;  in rk3588_adc_get_clk()  local
661 		div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;  in rk3588_adc_get_clk()
668 		return DIV_TO_RATE(prate, div);  in rk3588_adc_get_clk()
671 		div = (con & CLK_TSADC_DIV_MASK) >>  in rk3588_adc_get_clk()
679 		return DIV_TO_RATE(prate, div);  in rk3588_adc_get_clk()
747 	u32 sel, con, div, prate;  in rk3588_mmc_get_clk()  local
752 		div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;  in rk3588_mmc_get_clk()
761 		return DIV_TO_RATE(prate, div);  in rk3588_mmc_get_clk()
764 		div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;  in rk3588_mmc_get_clk()
773 		return DIV_TO_RATE(prate, div);  in rk3588_mmc_get_clk()
776 		div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;  in rk3588_mmc_get_clk()
783 		return DIV_TO_RATE(prate, div);  in rk3588_mmc_get_clk()
786 		div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;  in rk3588_mmc_get_clk()
795 		return DIV_TO_RATE(prate, div);  in rk3588_mmc_get_clk()
798 		div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;  in rk3588_mmc_get_clk()
805 		return DIV_TO_RATE(prate, div);  in rk3588_mmc_get_clk()
815 	int src_clk, div;  in rk3588_mmc_set_clk()  local
823 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3588_mmc_set_clk()
826 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_mmc_set_clk()
829 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_mmc_set_clk()
835 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_mmc_set_clk()
838 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_mmc_set_clk()
844 			div = DIV_ROUND_UP(702 * MHz, rate);  in rk3588_mmc_set_clk()
847 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_mmc_set_clk()
860 			     (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);  in rk3588_mmc_set_clk()
867 			     (div - 1) << CCLK_EMMC_DIV_SHIFT);  in rk3588_mmc_set_clk()
874 			     (div - 1) << BCLK_EMMC_DIV_SHIFT);  in rk3588_mmc_set_clk()
881 			     (div - 1) << SCLK_SFC_DIV_SHIFT);  in rk3588_mmc_set_clk()
888 			     (div - 1) << DCLK_DECOM_DIV_SHIFT);  in rk3588_mmc_set_clk()
901 	u32 div, con, parent;  in rk3588_aux16m_get_clk()  local
908 		div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT;  in rk3588_aux16m_get_clk()
909 		return DIV_TO_RATE(parent, div);  in rk3588_aux16m_get_clk()
911 		div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT;  in rk3588_aux16m_get_clk()
912 		return DIV_TO_RATE(parent, div);  in rk3588_aux16m_get_clk()
922 	u32 div;  in rk3588_aux16m_set_clk()  local
929 	div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_aux16m_set_clk()
934 			     (div - 1) << CLK_AUX16MHZ_0_DIV_SHIFT);  in rk3588_aux16m_set_clk()
938 			     (div - 1) << CLK_AUX16MHZ_1_DIV_SHIFT);  in rk3588_aux16m_set_clk()
950 	u32 div, sel, con, parent;  in rk3588_aclk_vop_get_clk()  local
956 		div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;  in rk3588_aclk_vop_get_clk()
968 		return DIV_TO_RATE(parent, div);  in rk3588_aclk_vop_get_clk()
1001 	int src_clk, div;  in rk3588_aclk_vop_set_clk()  local
1008 			div = 1;  in rk3588_aclk_vop_set_clk()
1011 			div = 2;  in rk3588_aclk_vop_set_clk()
1014 			div = 1;  in rk3588_aclk_vop_set_clk()
1017 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_aclk_vop_set_clk()
1020 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_aclk_vop_set_clk()
1026 			     (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);  in rk3588_aclk_vop_set_clk()
1064 	u32 div, sel, con, parent;  in rk3588_dclk_vop_get_clk()  local
1070 		div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;  in rk3588_dclk_vop_get_clk()
1076 		div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT;  in rk3588_dclk_vop_get_clk()
1082 		div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT;  in rk3588_dclk_vop_get_clk()
1087 		div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT;  in rk3588_dclk_vop_get_clk()
1104 	return DIV_TO_RATE(parent, div);  in rk3588_dclk_vop_get_clk()
1114 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3588_dclk_vop_set_clk()  local
1161 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3588_dclk_vop_set_clk()
1165 				     ((div - 1) << div_shift));  in rk3588_dclk_vop_set_clk()
1167 			div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);  in rk3588_dclk_vop_set_clk()
1168 			if (div % 2)  in rk3588_dclk_vop_set_clk()
1169 				div = div + 1;  in rk3588_dclk_vop_set_clk()
1173 				     ((div - 1) << div_shift));  in rk3588_dclk_vop_set_clk()
1175 					      priv->cru, V0PLL, div * rate);  in rk3588_dclk_vop_set_clk()
1197 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3588_dclk_vop_set_clk()
1198 			if (div > 255)  in rk3588_dclk_vop_set_clk()
1200 			now = pll_rate / div;  in rk3588_dclk_vop_set_clk()
1203 				best_div = div;  in rk3588_dclk_vop_set_clk()
1226 	u32 div, sel, con, parent;  in rk3588_clk_csihost_get_clk()  local
1239 	div = (con & CLK_DSIHOST_DIV_MASK) >> CLK_DSIHOST_DIV_SHIFT;  in rk3588_clk_csihost_get_clk()
1251 	return DIV_TO_RATE(parent, div);  in rk3588_clk_csihost_get_clk()
1257 	u32 con, div;  in rk3588_gmac_get_clk()  local
1262 		div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;  in rk3588_gmac_get_clk()
1263 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1266 		div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT;  in rk3588_gmac_get_clk()
1267 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1270 		div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT;  in rk3588_gmac_get_clk()
1271 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1274 		div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT;  in rk3588_gmac_get_clk()
1275 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1285 	int div;  in rk3588_gmac_set_clk()  local
1287 	div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_gmac_set_clk()
1294 			     (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);  in rk3588_gmac_set_clk()
1300 			     (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);  in rk3588_gmac_set_clk()
1307 			     (div - 1) << CLK_GMAC_125M_DIV_SHIFT);  in rk3588_gmac_set_clk()
1313 			     (div - 1) << CLK_GMAC_50M_DIV_SHIFT);  in rk3588_gmac_set_clk()
1325 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3588_uart_get_rate()  local
1362 	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;  in rk3588_uart_get_rate()
1370 		return DIV_TO_RATE(p_rate, div);  in rk3588_uart_get_rate()
1377 		return DIV_TO_RATE(p_rate, div) * n / m;  in rk3588_uart_get_rate()
1387 	u32 reg, clk_src, uart_src, div;  in rk3588_uart_set_rate()  local
1393 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_uart_set_rate()
1397 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3588_uart_set_rate()
1401 		div = 2;  in rk3588_uart_set_rate()
1405 		div = 2;  in rk3588_uart_set_rate()
1406 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3588_uart_set_rate()
1447 		     ((div - 1) << CLK_UART_SRC_DIV_SHIFT));  in rk3588_uart_set_rate()
1462 	u32 con, div, src;  in rk3588_pciephy_get_rate()  local
1469 		div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT;  in rk3588_pciephy_get_rate()
1475 		div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT;  in rk3588_pciephy_get_rate()
1480 		div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT;  in rk3588_pciephy_get_rate()
1487 		return DIV_TO_RATE(priv->ppll_hz, div);  in rk3588_pciephy_get_rate()
1497 	u32 clk_src, div;  in rk3588_pciephy_set_rate()  local
1501 		div = 1;  in rk3588_pciephy_set_rate()
1504 		div = DIV_ROUND_UP(priv->ppll_hz, rate);  in rk3588_pciephy_set_rate()
1514 		     ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT));  in rk3588_pciephy_set_rate()
1522 		     ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT));  in rk3588_pciephy_set_rate()
1529 		     ((div - 1) << CLK_PCIE_PHY2_PLL_DIV_SHIFT));  in rk3588_pciephy_set_rate()
2062 	int ret, div;  in rk3588_clk_init()  local
2064 	div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz);  in rk3588_clk_init()
2068 		     div << ACLK_BUS_ROOT_DIV_SHIFT);  in rk3588_clk_init()
2246 #define CLKDIV_6BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x3fU, shift)  argument
2247 #define CLKDIV_5BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x1fU, shift)  argument
2251 	u32 src, div;  in rk3588_clk_scmi_get_rate()  local
2265 		div = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x0fc0;  in rk3588_clk_scmi_get_rate()
2266 		div = div >> 6;  in rk3588_clk_scmi_get_rate()
2268 			return SPLL_RATE / (div + 1);  in rk3588_clk_scmi_get_rate()
2270 			return OSC_HZ / (div + 1);  in rk3588_clk_scmi_get_rate()
2272 			return GPLL_RATE / (div + 1);  in rk3588_clk_scmi_get_rate()
2275 		div = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x001f;  in rk3588_clk_scmi_get_rate()
2277 			return SPLL_RATE / (div + 1);  in rk3588_clk_scmi_get_rate()
2279 			return GPLL_RATE / (div + 1);  in rk3588_clk_scmi_get_rate()
2356 	u32 src, div;  in rk3588_clk_scmi_set_rate()  local
2382 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3588_clk_scmi_set_rate()
2383 			writel(CLKDIV_6BITS_SHF(div - 1, 6) |  in rk3588_clk_scmi_set_rate()
2387 			div = DIV_ROUND_UP(SPLL_RATE, rate);  in rk3588_clk_scmi_set_rate()
2388 			writel(CLKDIV_6BITS_SHF(div - 1, 6) |  in rk3588_clk_scmi_set_rate()
2392 			div = DIV_ROUND_UP(GPLL_RATE, rate);  in rk3588_clk_scmi_set_rate()
2393 			writel(CLKDIV_6BITS_SHF(div - 1, 6) |  in rk3588_clk_scmi_set_rate()
2400 			div = DIV_ROUND_UP(SPLL_RATE, rate);  in rk3588_clk_scmi_set_rate()
2401 			writel(CLKDIV_5BITS_SHF(div - 1, 0) |  in rk3588_clk_scmi_set_rate()
2405 			div = DIV_ROUND_UP(GPLL_RATE, rate);  in rk3588_clk_scmi_set_rate()
2406 			writel(CLKDIV_5BITS_SHF(div - 1, 0) |  in rk3588_clk_scmi_set_rate()