Lines Matching refs:div
24 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
188 u32 sel, con, div; in rk3506_armclk_get_rate() local
193 div = (con & CLK_CORE_SRC_DIV_MASK) >> CLK_CORE_SRC_DIV_SHIFT; in rk3506_armclk_get_rate()
204 return DIV_TO_RATE(prate, div); in rk3506_armclk_get_rate()
212 u32 con, sel, div, old_div; in rk3506_armclk_set_rate() local
233 div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); in rk3506_armclk_set_rate()
237 div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); in rk3506_armclk_set_rate()
241 div = DIV_ROUND_UP(priv->gpll_hz, new_rate); in rk3506_armclk_set_rate()
244 assert(div - 1 <= 31); in rk3506_armclk_set_rate()
250 (div - 1) << CLK_CORE_SRC_DIV_SHIFT); in rk3506_armclk_set_rate()
257 (div - 1) << CLK_CORE_SRC_DIV_SHIFT); in rk3506_armclk_set_rate()
273 u32 con, div; in rk3506_pll_div_get_rate() local
279 div = (con & CLK_GPLL_DIV_MASK) >> CLK_GPLL_DIV_SHIFT; in rk3506_pll_div_get_rate()
284 div = (con & CLK_GPLL_DIV_100M_MASK) >> CLK_GPLL_DIV_100M_SHIFT; in rk3506_pll_div_get_rate()
289 div = (con & CLK_V0PLL_DIV_MASK) >> CLK_V0PLL_DIV_SHIFT; in rk3506_pll_div_get_rate()
294 div = (con & CLK_V1PLL_DIV_MASK) >> CLK_V1PLL_DIV_SHIFT; in rk3506_pll_div_get_rate()
301 return DIV_TO_RATE(prate, div); in rk3506_pll_div_get_rate()
308 u32 div; in rk3506_pll_div_set_rate() local
312 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_pll_div_set_rate()
313 assert(div - 1 <= 15); in rk3506_pll_div_set_rate()
315 ((div - 1) << CLK_GPLL_DIV_SHIFT)); in rk3506_pll_div_set_rate()
318 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_pll_div_set_rate()
319 assert(div - 1 <= 15); in rk3506_pll_div_set_rate()
321 ((div - 1) << CLK_GPLL_DIV_100M_SHIFT)); in rk3506_pll_div_set_rate()
324 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_pll_div_set_rate()
325 assert(div - 1 <= 15); in rk3506_pll_div_set_rate()
327 ((div - 1) << CLK_V0PLL_DIV_SHIFT)); in rk3506_pll_div_set_rate()
330 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_pll_div_set_rate()
331 assert(div - 1 <= 15); in rk3506_pll_div_set_rate()
333 ((div - 1) << CLK_V1PLL_DIV_SHIFT)); in rk3506_pll_div_set_rate()
345 u32 sel, con, div; in rk3506_bus_get_rate() local
352 div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT; in rk3506_bus_get_rate()
357 div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT; in rk3506_bus_get_rate()
362 div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT; in rk3506_bus_get_rate()
377 return DIV_TO_RATE(prate, div); in rk3506_bus_get_rate()
384 u32 sel, div; in rk3506_bus_set_rate() local
388 div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); in rk3506_bus_set_rate()
391 div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); in rk3506_bus_set_rate()
394 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_bus_set_rate()
396 assert(div - 1 <= 31); in rk3506_bus_set_rate()
403 ((div - 1) << ACLK_BUS_DIV_SHIFT)); in rk3506_bus_set_rate()
409 ((div - 1) << HCLK_BUS_DIV_SHIFT)); in rk3506_bus_set_rate()
415 ((div - 1) << PCLK_BUS_DIV_SHIFT)); in rk3506_bus_set_rate()
427 u32 sel, con, div; in rk3506_peri_get_rate() local
434 div = (con & ACLK_HSPERI_DIV_MASK) >> ACLK_HSPERI_DIV_SHIFT; in rk3506_peri_get_rate()
439 div = (con & HCLK_LSPERI_DIV_MASK) >> HCLK_LSPERI_DIV_SHIFT; in rk3506_peri_get_rate()
454 return DIV_TO_RATE(prate, div); in rk3506_peri_get_rate()
461 u32 sel, div; in rk3506_peri_set_rate() local
465 div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); in rk3506_peri_set_rate()
468 div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); in rk3506_peri_set_rate()
471 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_peri_set_rate()
473 assert(div - 1 <= 31); in rk3506_peri_set_rate()
480 ((div - 1) << ACLK_HSPERI_DIV_SHIFT)); in rk3506_peri_set_rate()
486 ((div - 1) << HCLK_LSPERI_DIV_SHIFT)); in rk3506_peri_set_rate()
498 u32 sel, con, div; in rk3506_sdmmc_get_rate() local
503 div = (con & CCLK_SDMMC_DIV_MASK) >> CCLK_SDMMC_DIV_SHIFT; in rk3506_sdmmc_get_rate()
516 return DIV_TO_RATE(prate, div); in rk3506_sdmmc_get_rate()
523 u32 sel, div; in rk3506_sdmmc_set_rate() local
527 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_sdmmc_set_rate()
530 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_sdmmc_set_rate()
533 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_sdmmc_set_rate()
536 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_sdmmc_set_rate()
538 assert(div - 1 <= 63); in rk3506_sdmmc_set_rate()
543 ((div - 1) << CCLK_SDMMC_DIV_SHIFT)); in rk3506_sdmmc_set_rate()
551 u32 div, con, sel; in rk3506_saradc_get_rate() local
555 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3506_saradc_get_rate()
567 return DIV_TO_RATE(prate, div); in rk3506_saradc_get_rate()
574 u32 div, sel; in rk3506_saradc_set_rate() local
578 div = 1; in rk3506_saradc_set_rate()
581 div = 1; in rk3506_saradc_set_rate()
584 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_saradc_set_rate()
586 assert(div - 1 <= 15); in rk3506_saradc_set_rate()
591 ((div - 1) << CLK_SARADC_DIV_SHIFT)); in rk3506_saradc_set_rate()
599 u32 div, con; in rk3506_tsadc_get_rate() local
604 div = (con & CLK_TSADC_TSEN_DIV_MASK) >> CLK_TSADC_TSEN_DIV_SHIFT; in rk3506_tsadc_get_rate()
607 div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT; in rk3506_tsadc_get_rate()
613 return DIV_TO_RATE(OSC_HZ, div); in rk3506_tsadc_get_rate()
620 u32 div; in rk3506_tsadc_set_rate() local
624 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_tsadc_set_rate()
625 assert(div - 1 <= 7); in rk3506_tsadc_set_rate()
627 (div - 1) << CLK_TSADC_TSEN_DIV_SHIFT); in rk3506_tsadc_set_rate()
630 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_tsadc_set_rate()
631 assert(div - 1 <= 255); in rk3506_tsadc_set_rate()
633 (div - 1) << CLK_TSADC_DIV_SHIFT); in rk3506_tsadc_set_rate()
646 u32 sel, con, div; in rk3506_i2c_get_rate() local
653 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; in rk3506_i2c_get_rate()
657 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; in rk3506_i2c_get_rate()
661 div = (con & CLK_I2C2_DIV_MASK) >> CLK_I2C2_DIV_SHIFT; in rk3506_i2c_get_rate()
676 return DIV_TO_RATE(prate, div); in rk3506_i2c_get_rate()
683 u32 sel, div; in rk3506_i2c_set_rate() local
687 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_i2c_set_rate()
690 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_i2c_set_rate()
693 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_i2c_set_rate()
695 assert(div - 1 <= 15); in rk3506_i2c_set_rate()
702 ((div - 1) << CLK_I2C0_DIV_SHIFT)); in rk3506_i2c_set_rate()
708 ((div - 1) << CLK_I2C1_DIV_SHIFT)); in rk3506_i2c_set_rate()
714 ((div - 1) << CLK_I2C2_DIV_SHIFT)); in rk3506_i2c_set_rate()
727 u32 sel, con, div; in rk3506_pwm_get_rate() local
733 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rk3506_pwm_get_rate()
739 div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; in rk3506_pwm_get_rate()
753 return DIV_TO_RATE(prate, div); in rk3506_pwm_get_rate()
760 u32 sel, div; in rk3506_pwm_set_rate() local
764 div = DIV_ROUND_UP(priv->gpll_div_100mhz, rate); in rk3506_pwm_set_rate()
765 assert(div - 1 <= 15); in rk3506_pwm_set_rate()
767 (div - 1) << CLK_PWM0_DIV_SHIFT); in rk3506_pwm_set_rate()
772 div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); in rk3506_pwm_set_rate()
775 div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); in rk3506_pwm_set_rate()
778 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_pwm_set_rate()
780 assert(div - 1 <= 15); in rk3506_pwm_set_rate()
784 ((div - 1) << CLK_PWM1_DIV_SHIFT)); in rk3506_pwm_set_rate()
796 u32 sel, con, div; in rk3506_spi_get_rate() local
803 div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT; in rk3506_spi_get_rate()
808 div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT; in rk3506_spi_get_rate()
825 return DIV_TO_RATE(prate, div); in rk3506_spi_get_rate()
832 u32 sel, div; in rk3506_spi_set_rate() local
836 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_spi_set_rate()
839 div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); in rk3506_spi_set_rate()
842 div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); in rk3506_spi_set_rate()
845 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_spi_set_rate()
847 assert(div - 1 <= 15); in rk3506_spi_set_rate()
854 ((div - 1) << CLK_SPI0_DIV_SHIFT)); in rk3506_spi_set_rate()
860 ((div - 1) << CLK_SPI1_DIV_SHIFT)); in rk3506_spi_set_rate()
872 u32 div, sel, con, prate; in rk3506_fspi_get_rate() local
875 div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT; in rk3506_fspi_get_rate()
888 return DIV_TO_RATE(prate, div); in rk3506_fspi_get_rate()
894 int div, sel; in rk3506_fspi_set_rate() local
898 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_fspi_set_rate()
901 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_fspi_set_rate()
904 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_fspi_set_rate()
907 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_fspi_set_rate()
909 assert(div - 1 <= 31); in rk3506_fspi_set_rate()
914 (div - 1) << SCLK_FSPI_DIV_SHIFT); in rk3506_fspi_set_rate()
922 u32 div, sel, con, prate; in rk3506_vop_dclk_get_rate() local
925 div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; in rk3506_vop_dclk_get_rate()
939 return DIV_TO_RATE(prate, div); in rk3506_vop_dclk_get_rate()
945 int div, sel; in rk3506_vop_dclk_set_rate() local
949 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3506_vop_dclk_set_rate()
952 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_vop_dclk_set_rate()
955 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_vop_dclk_set_rate()
958 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_vop_dclk_set_rate()
960 assert(div - 1 <= 255); in rk3506_vop_dclk_set_rate()
965 (div - 1) << DCLK_VOP_DIV_SHIFT); in rk3506_vop_dclk_set_rate()
973 u32 div, con; in rk3506_mac_get_rate() local
979 div = (con & CLK_MAC_DIV_MASK) >> CLK_MAC_DIV_SHIFT; in rk3506_mac_get_rate()
983 div = (con & CLK_MAC_OUT_DIV_MASK) >> CLK_MAC_OUT_DIV_SHIFT; in rk3506_mac_get_rate()
989 return DIV_TO_RATE(priv->gpll_hz, div); in rk3506_mac_get_rate()
996 u32 div; in rk3506_mac_set_rate() local
1001 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_mac_set_rate()
1003 ((div - 1) << CLK_MAC_DIV_SHIFT)); in rk3506_mac_set_rate()
1006 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_mac_set_rate()
1008 ((div - 1) << CLK_MAC_OUT_DIV_SHIFT)); in rk3506_mac_set_rate()