20 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
205 	u32 sel, con, div;  in rk3562_bus_get_rate()  local
212 		div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
217 		div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
222 		div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
233 	return DIV_TO_RATE(rate, div);  in rk3562_bus_get_rate()
240 	u32 sel, div;  in rk3562_bus_set_rate()  local
244 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_bus_set_rate()
247 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_bus_set_rate()
255 			     ((div - 1) << ACLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
261 			     ((div - 1) << HCLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
267 			     ((div - 1) << PCLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
279 	u32 sel, con, div;  in rk3562_peri_get_rate()  local
286 		div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
291 		div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
296 		div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
307 	return DIV_TO_RATE(rate, div);  in rk3562_peri_get_rate()
314 	u32 sel, div;  in rk3562_peri_set_rate()  local
318 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_peri_set_rate()
321 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_peri_set_rate()
329 			     ((div - 1) << ACLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
335 			     ((div - 1) << HCLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
341 			     ((div - 1) << PCLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
353 	u32 sel, con, div;  in rk3562_i2c_get_rate()  local
366 		div = (con & CLK_PMU0_I2C0_DIV_MASK) >> CLK_PMU0_I2C0_DIV_SHIFT;  in rk3562_i2c_get_rate()
368 		return DIV_TO_RATE(rate, div);  in rk3562_i2c_get_rate()
397 	u32 sel, div;  in rk3562_i2c_set_rate()  local
403 			div = 1;  in rk3562_i2c_set_rate()
406 			div = 1;  in rk3562_i2c_set_rate()
409 			div = 1;  in rk3562_i2c_set_rate()
412 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_i2c_set_rate()
413 			assert(div - 1 <= 31);  in rk3562_i2c_set_rate()
416 			     (div - 1) << CLK_PMU0_I2C0_DIV_SHIFT);  in rk3562_i2c_set_rate()
447 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3562_uart_get_rate()  local
455 		div = (con & CLK_PMU1_UART0_SRC_DIV_MASK) >>  in rk3562_uart_get_rate()
458 			return DIV_TO_RATE(priv->cpll_hz, div);  in rk3562_uart_get_rate()
465 			return DIV_TO_RATE(priv->cpll_hz, div) * n / m;  in rk3562_uart_get_rate()
501 	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;  in rk3562_uart_get_rate()
508 		return DIV_TO_RATE(p_rate, div);  in rk3562_uart_get_rate()
515 		return DIV_TO_RATE(p_rate, div) * n / m;  in rk3562_uart_get_rate()
525 	u32 reg, clk_src, uart_src, div;  in rk3562_uart_set_rate()  local
532 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_uart_set_rate()
535 			div = 2;  in rk3562_uart_set_rate()
538 			div = 2;  in rk3562_uart_set_rate()
539 			rational_best_approximation(rate, priv->cpll_hz / div,  in rk3562_uart_set_rate()
549 			     ((div - 1) << CLK_PMU1_UART0_SRC_DIV_SHIFT));  in rk3562_uart_set_rate()
590 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_uart_set_rate()
594 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_uart_set_rate()
598 		div = 2;  in rk3562_uart_set_rate()
602 		div = 2;  in rk3562_uart_set_rate()
603 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3562_uart_set_rate()
614 		     ((div - 1) << CLK_UART_SRC_DIV_SHIFT));  in rk3562_uart_set_rate()
626 	u32 sel, con, div, mask, shift;  in rk3562_pwm_get_rate()  local
639 		div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT;  in rk3562_pwm_get_rate()
641 		return DIV_TO_RATE(rate, div);  in rk3562_pwm_get_rate()
674 	u32 sel, div, mask, shift;  in rk3562_pwm_set_rate()  local
680 			div = 1;  in rk3562_pwm_set_rate()
683 			div = 1;  in rk3562_pwm_set_rate()
686 			div = 1;  in rk3562_pwm_set_rate()
689 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_pwm_set_rate()
690 			assert(div - 1 <= 3);  in rk3562_pwm_set_rate()
693 			     (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT);  in rk3562_pwm_set_rate()
728 	u32 sel, con, div, mask, shift;  in rk3562_spi_get_rate()  local
741 		div = (con & CLK_PMU1_SPI0_DIV_MASK) >> CLK_PMU1_SPI0_DIV_SHIFT;  in rk3562_spi_get_rate()
743 		return DIV_TO_RATE(rate, div);  in rk3562_spi_get_rate()
774 	u32 sel, div, mask, shift;  in rk3562_spi_set_rate()  local
780 			div = 1;  in rk3562_spi_set_rate()
783 			div = 1;  in rk3562_spi_set_rate()
786 			div = 1;  in rk3562_spi_set_rate()
789 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_spi_set_rate()
790 			assert(div - 1 <= 3);  in rk3562_spi_set_rate()
793 			     (div - 1) << CLK_PMU1_SPI0_DIV_SHIFT);  in rk3562_spi_set_rate()
826 	u32 div, con;  in rk3562_tsadc_get_rate()  local
831 		div = (con & CLK_TSADC_TSEN_DIV_MASK) >>  in rk3562_tsadc_get_rate()
835 		div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;  in rk3562_tsadc_get_rate()
841 	return DIV_TO_RATE(OSC_HZ, div);  in rk3562_tsadc_get_rate()
848 	u32 div, mask, shift;  in rk3562_tsadc_set_rate()  local
863 	div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_tsadc_set_rate()
864 	rk_clrsetreg(&cru->clksel_con[43], mask, (div - 1) << shift);  in rk3562_tsadc_set_rate()
872 	u32 div, con;  in rk3562_saradc_get_rate()  local
877 		div = (con & CLK_SARADC_VCCIO156_DIV_MASK) >>  in rk3562_saradc_get_rate()
882 		div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;  in rk3562_saradc_get_rate()
888 	return DIV_TO_RATE(OSC_HZ, div);  in rk3562_saradc_get_rate()
895 	u32 div;  in rk3562_saradc_set_rate()  local
899 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_saradc_set_rate()
901 			     (div - 1) << CLK_SARADC_VCCIO156_DIV_SHIFT);  in rk3562_saradc_set_rate()
904 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_saradc_set_rate()
906 			     (div - 1) << CLK_SARADC_DIV_SHIFT);  in rk3562_saradc_set_rate()
918 	u32 div, sel, con, parent;  in rk3562_sfc_get_rate()  local
921 	div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;  in rk3562_sfc_get_rate()
930 	return DIV_TO_RATE(parent, div);  in rk3562_sfc_get_rate()
936 	int div, sel;  in rk3562_sfc_set_rate()  local
939 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_sfc_set_rate()
942 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_sfc_set_rate()
945 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_sfc_set_rate()
949 	assert(div - 1 <= 255);  in rk3562_sfc_set_rate()
953 		     (div - 1) << SCLK_SFC_DIV_SHIFT);  in rk3562_sfc_set_rate()
961 	u32 div, sel, con, parent;  in rk3562_emmc_get_rate()  local
966 		div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;  in rk3562_emmc_get_rate()
979 		div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;  in rk3562_emmc_get_rate()
990 	return DIV_TO_RATE(parent, div);  in rk3562_emmc_get_rate()
997 	int div, sel;  in rk3562_emmc_set_rate()  local
1002 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_emmc_set_rate()
1005 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_emmc_set_rate()
1008 			div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_emmc_set_rate()
1011 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_emmc_set_rate()
1017 			     (div - 1) << CCLK_EMMC_DIV_SHIFT);  in rk3562_emmc_set_rate()
1021 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_emmc_set_rate()
1024 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_emmc_set_rate()
1030 			     (div - 1) << BCLK_EMMC_DIV_SHIFT);  in rk3562_emmc_set_rate()
1042 	u32 div, sel, con;  in rk3562_sdmmc_get_rate()  local
1050 		div = (con & CCLK_SDMMC0_DIV_MASK) >> CCLK_SDMMC0_DIV_SHIFT;  in rk3562_sdmmc_get_rate()
1057 		div = (con & CCLK_SDMMC1_DIV_MASK) >> CCLK_SDMMC1_DIV_SHIFT;  in rk3562_sdmmc_get_rate()
1073 	return DIV_TO_RATE(prate, div);  in rk3562_sdmmc_get_rate()
1080 	u32 div, sel;  in rk3562_sdmmc_set_rate()  local
1083 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_sdmmc_set_rate()
1086 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_sdmmc_set_rate()
1089 		div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_sdmmc_set_rate()
1092 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_sdmmc_set_rate()
1102 			     (div - 1) << CCLK_SDMMC0_DIV_SHIFT);  in rk3562_sdmmc_set_rate()
1109 			     (div - 1) << CCLK_SDMMC1_DIV_SHIFT);  in rk3562_sdmmc_set_rate()
1121 	u32 con, sel, div;  in rk3562_vop_get_rate()  local
1127 		div = (con & ACLK_VOP_DIV_MASK) >> ACLK_VOP_DIV_SHIFT;  in rk3562_vop_get_rate()
1140 		return DIV_TO_RATE(prate, div);  in rk3562_vop_get_rate()
1143 		div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT;  in rk3562_vop_get_rate()
1152 		div = (con & DCLK_VOP1_DIV_MASK) >> DCLK_VOP1_DIV_SHIFT;  in rk3562_vop_get_rate()
1168 	return DIV_TO_RATE(prate, div);  in rk3562_vop_get_rate()
1177 	u32 i, div, sel, best_div = 0, best_sel = 0;  in rk3562_vop_set_rate()  local
1183 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_vop_set_rate()
1186 			div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_vop_set_rate()
1189 			div = DIV_ROUND_UP(priv->vpll_hz, rate);  in rk3562_vop_set_rate()
1192 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_vop_set_rate()
1198 			     ((div - 1) << ACLK_VOP_DIV_SHIFT));  in rk3562_vop_set_rate()
1202 		div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate);  in rk3562_vop_set_rate()
1203 		if (div % 2)  in rk3562_vop_set_rate()
1204 			div = div + 1;  in rk3562_vop_set_rate()
1208 			     ((div - 1) << DCLK_VOP_DIV_SHIFT));  in rk3562_vop_set_rate()
1210 				      VPLL, div * rate);  in rk3562_vop_set_rate()
1229 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3562_vop_set_rate()
1230 			if (div > 255)  in rk3562_vop_set_rate()
1232 			now = pll_rate / div;  in rk3562_vop_set_rate()
1235 				best_div = div;  in rk3562_vop_set_rate()
1261 	u32 con, sel, div;  in rk3562_gmac_get_rate()  local
1289 		div = (con & CLK_GMAC_ETH_OUT2IO_DIV_MASK) >> CLK_GMAC_ETH_OUT2IO_DIV_SHIFT;  in rk3562_gmac_get_rate()
1299 	return DIV_TO_RATE(prate, div);  in rk3562_gmac_get_rate()
1306 	u32 sel, div;  in rk3562_gmac_set_rate()  local
1335 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_gmac_set_rate()
1338 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_gmac_set_rate()
1344 			     (div - 1) << CLK_GMAC_ETH_OUT2IO_DIV_SHIFT);  in rk3562_gmac_set_rate()