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Searched refs:GPLL (Results 1 – 25 of 33) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1103b.c40 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1103B_PLL_CON(24),
812 rate = rockchip_pll_get_rate(&rv1103b_pll_clks[GPLL], priv->cru, in rv1103b_clk_get_rate()
813 GPLL); in rv1103b_clk_get_rate()
898 ret = rockchip_pll_set_rate(&rv1103b_pll_clks[GPLL], priv->cru, in rv1103b_clk_set_rate()
899 GPLL, rate); in rv1103b_clk_set_rate()
990 priv->gpll_hz = rockchip_pll_get_rate(&rv1103b_pll_clks[GPLL], in rv1103b_clk_init()
991 priv->cru, GPLL); in rv1103b_clk_init()
993 ret = rockchip_pll_set_rate(&rv1103b_pll_clks[GPLL], priv->cru, in rv1103b_clk_init()
994 GPLL, GPLL_HZ); in rv1103b_clk_init()
H A Dclk_rk3128.c87 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(12),
605 ret = rockchip_pll_set_rate(&rk3128_pll_clks[GPLL], in rk3128_clk_set_rate()
606 priv->cru, GPLL, rate); in rk3128_clk_set_rate()
814 priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
815 priv->cru, GPLL); in rkclk_init()
818 rockchip_pll_set_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
819 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
H A Dclk_rk3328.c112 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3328_PLL_CON(24),
788 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_get_rate()
789 priv->cru, GPLL); in rk3328_clk_get_rate()
885 ret = rockchip_pll_set_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_set_rate()
886 priv->cru, GPLL, rate); in rk3328_clk_set_rate()
1286 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1287 priv->cru, GPLL); in rkclk_init()
1300 rockchip_pll_set_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1301 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
H A Dclk_rk3368.c315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
596 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_bus_get_clk()
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
670 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_peri_get_clk()
704 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_peri_set_clk()
757 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_vop_get_clk()
806 lcdc_div = rkclk_pll_get_rate(cru, GPLL) / hz; in rk3368_vop_set_clk()
1277 rkclk_set_pll(cru, GPLL, &gpll_init_cfg); in rkclk_init()
1285 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
H A Dclk_rk322x.c88 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(9),
654 ret = rockchip_pll_set_rate(&rk322x_pll_clks[GPLL], in rk322x_clk_set_rate()
655 priv->cru, GPLL, rate); in rk322x_clk_set_rate()
961 priv->gpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
962 priv->cru, GPLL); in rkclk_init()
992 rockchip_pll_set_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
993 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
H A Dclk_rk1808.c86 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK1808_PLL_CON(24),
1015 ret = rockchip_pll_set_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_set_rate()
1016 priv->cru, GPLL, rate); in rk1808_clk_set_rate()
1303 ret = rockchip_pll_set_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()
1304 priv->cru, GPLL, GPLL_HZ); in rk1808_clk_probe()
1310 priv->gpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()
1311 priv->cru, GPLL); in rk1808_clk_probe()
H A Dclk_rv1106.c45 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1106_PLL_CON(24),
1064 rate = rockchip_pll_get_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_get_rate()
1065 GPLL); in rv1106_clk_get_rate()
1165 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_set_rate()
1166 GPLL, rate); in rv1106_clk_set_rate()
1288 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_init()
1289 GPLL, GPLL_HZ); in rv1106_clk_init()
H A Dclk_rk3528.c72 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
1354 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_get_rate()
1355 GPLL); in rk3528_clk_get_rate()
1475 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_set_rate()
1476 GPLL, rate); in rk3528_clk_set_rate()
1477 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], in rk3528_clk_set_rate()
1478 priv->cru, GPLL); in rk3528_clk_set_rate()
1950 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_init()
1951 GPLL, GPLL_HZ); in rk3528_clk_init()
H A Dclk_rv1126b.c44 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126B_PLL_CON(8),
1478 rate = rockchip_pll_get_rate(&rv1126b_pll_clks[GPLL], priv->cru, in rv1126b_clk_get_rate()
1479 GPLL); in rv1126b_clk_get_rate()
1610 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, in rv1126b_clk_set_rate()
1611 GPLL, rate); in rv1126b_clk_set_rate()
1828 priv->gpll_hz = rockchip_pll_get_rate(&rv1126b_pll_clks[GPLL], in rv1126b_clk_init()
1829 priv->cru, GPLL); in rv1126b_clk_init()
1831 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, in rv1126b_clk_init()
1832 GPLL, GPLL_HZ); in rv1126b_clk_init()
H A Dclk_rk3562.c49 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
1371 rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_get_rate()
1372 GPLL); in rk3562_clk_get_rate()
1498 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_set_rate()
1499 GPLL, rate); in rk3562_clk_set_rate()
1500 priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], in rk3562_clk_set_rate()
1501 priv->cru, GPLL); in rk3562_clk_set_rate()
1831 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_init()
1832 GPLL, GPLL_HZ); in rk3562_clk_init()
H A Dclk_rk3588.c62 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
1568 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1569 GPLL); in rk3588_clk_get_rate()
1717 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_set_rate()
1718 GPLL, rate); in rk3588_clk_set_rate()
1719 priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], in rk3588_clk_set_rate()
1720 priv->cru, GPLL); in rk3588_clk_set_rate()
2078 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_init()
2079 GPLL, GPLL_HZ); in rk3588_clk_init()
H A Dclk_rk3576.c77 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
2079 rate = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], priv->cru, in rk3576_clk_get_rate()
2080 GPLL); in rk3576_clk_get_rate()
2243 ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru, in rk3576_clk_set_rate()
2244 GPLL, rate); in rk3576_clk_set_rate()
2245 priv->gpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], in rk3576_clk_set_rate()
2246 priv->cru, GPLL); in rk3576_clk_set_rate()
2527 ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru, in rk3576_clk_init()
2528 GPLL, GPLL_HZ); in rk3576_clk_init()
H A Dclk_rk3568.c74 [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
2538 rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_get_rate()
2539 GPLL); in rk3568_clk_get_rate()
2723 ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_set_rate()
2724 GPLL, rate); in rk3568_clk_set_rate()
2725 priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], in rk3568_clk_set_rate()
2726 priv->cru, GPLL); in rk3568_clk_set_rate()
3274 ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_init()
3275 GPLL, GPLL_HZ); in rk3568_clk_init()
/rk3399_rockchip-uboot/board/rockchip/evb_rv1108/
H A DREADME31 APLL: 400000000 DPLL:798000000 GPLL:384000000
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3128.h66 GPLL, enumerator
H A Dcru_rk3368.h18 GPLL, enumerator
H A Dcru_rk322x.h63 GPLL, enumerator
H A Dcru_rk3328.h61 GPLL, enumerator
H A Dcru_rv1103b.h21 GPLL, enumerator
H A Dcru_rv1106.h29 GPLL, enumerator
H A Dcru_rk3506.h19 GPLL, enumerator
H A Dcru_rk1808.h23 GPLL, enumerator
H A Dcru_rv1126.h52 GPLL, enumerator
H A Dcru_px30.h31 GPLL, enumerator
H A Dcru_rk3528.h24 GPLL, enumerator

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