176f3cd6aSElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 276f3cd6aSElaine Zhang /* 376f3cd6aSElaine Zhang * Copyright (c) 2024 Rockchip Electronics Co. Ltd. 476f3cd6aSElaine Zhang * Author: Elaine Zhang <zhangqing@rock-chips.com> 576f3cd6aSElaine Zhang */ 676f3cd6aSElaine Zhang 776f3cd6aSElaine Zhang #ifndef _ASM_ARCH_CRU_RV1103B_H 876f3cd6aSElaine Zhang #define _ASM_ARCH_CRU_RV1103B_H 976f3cd6aSElaine Zhang 1076f3cd6aSElaine Zhang #include <common.h> 1176f3cd6aSElaine Zhang 1276f3cd6aSElaine Zhang #define MHz 1000000 1376f3cd6aSElaine Zhang #define KHz 1000 1476f3cd6aSElaine Zhang #define OSC_HZ (24 * MHz) 1576f3cd6aSElaine Zhang #define RC_OSC_HZ (125 * MHz) 1676f3cd6aSElaine Zhang 1776f3cd6aSElaine Zhang #define GPLL_HZ (1188 * MHz) 1876f3cd6aSElaine Zhang 1976f3cd6aSElaine Zhang /* RV1103B pll id */ 2076f3cd6aSElaine Zhang enum rv1103b_pll_id { 2176f3cd6aSElaine Zhang GPLL, 2276f3cd6aSElaine Zhang PLL_COUNT, 2376f3cd6aSElaine Zhang }; 2476f3cd6aSElaine Zhang 2576f3cd6aSElaine Zhang struct rv1103b_clk_info { 2676f3cd6aSElaine Zhang unsigned long id; 2776f3cd6aSElaine Zhang char *name; 2876f3cd6aSElaine Zhang bool is_cru; 2976f3cd6aSElaine Zhang }; 3076f3cd6aSElaine Zhang 3176f3cd6aSElaine Zhang struct rv1103b_clk_priv { 3276f3cd6aSElaine Zhang struct rv1103b_cru *cru; 3376f3cd6aSElaine Zhang struct rv1103b_grf *grf; 3476f3cd6aSElaine Zhang ulong gpll_hz; 3576f3cd6aSElaine Zhang ulong armclk_hz; 3676f3cd6aSElaine Zhang ulong armclk_enter_hz; 3776f3cd6aSElaine Zhang ulong armclk_init_hz; 3876f3cd6aSElaine Zhang bool sync_kernel; 3976f3cd6aSElaine Zhang bool set_armclk_rate; 4076f3cd6aSElaine Zhang }; 4176f3cd6aSElaine Zhang 4276f3cd6aSElaine Zhang struct rv1103b_grf_clk_priv { 4376f3cd6aSElaine Zhang struct rv1103b_grf *grf; 4476f3cd6aSElaine Zhang }; 4576f3cd6aSElaine Zhang 4676f3cd6aSElaine Zhang struct rv1103b_pll { 4776f3cd6aSElaine Zhang unsigned int con0; 4876f3cd6aSElaine Zhang unsigned int con1; 4976f3cd6aSElaine Zhang unsigned int con2; 5076f3cd6aSElaine Zhang unsigned int con3; 5176f3cd6aSElaine Zhang unsigned int con4; 5276f3cd6aSElaine Zhang unsigned int reserved0[3]; 5376f3cd6aSElaine Zhang }; 5476f3cd6aSElaine Zhang 5576f3cd6aSElaine Zhang struct rv1103b_cru { 5676f3cd6aSElaine Zhang unsigned int reserved0[192]; 5776f3cd6aSElaine Zhang unsigned int peri_clksel_con[4]; 5876f3cd6aSElaine Zhang unsigned int reserved1[316]; 5976f3cd6aSElaine Zhang unsigned int peri_clkgate_con[12]; 6076f3cd6aSElaine Zhang unsigned int reserved2[116]; 6176f3cd6aSElaine Zhang unsigned int peri_softrst_con[12]; 6276f3cd6aSElaine Zhang unsigned int reserved3[15924]; 6376f3cd6aSElaine Zhang unsigned int vepu_clksel_con[3]; 6476f3cd6aSElaine Zhang unsigned int reserved4[317]; 6576f3cd6aSElaine Zhang unsigned int vepu_clkgate_con[1]; 6676f3cd6aSElaine Zhang unsigned int reserved5[127]; 6776f3cd6aSElaine Zhang unsigned int vepu_softrst_con[1]; 6876f3cd6aSElaine Zhang unsigned int reserved6[15935]; 6976f3cd6aSElaine Zhang unsigned int npu_clksel_con[3]; 7076f3cd6aSElaine Zhang unsigned int reserved7[317]; 7176f3cd6aSElaine Zhang unsigned int npu_clkgate_con[1]; 7276f3cd6aSElaine Zhang unsigned int reserved8[127]; 7376f3cd6aSElaine Zhang unsigned int npu_softrst_con[1]; 7476f3cd6aSElaine Zhang unsigned int reserved9[15935]; 7576f3cd6aSElaine Zhang unsigned int vi_clksel_con[1]; 7676f3cd6aSElaine Zhang unsigned int reserved10[319]; 7776f3cd6aSElaine Zhang unsigned int vi_clkgate_con[3]; 7876f3cd6aSElaine Zhang unsigned int reserved11[125]; 7976f3cd6aSElaine Zhang unsigned int vi_softrst_con[3]; 8076f3cd6aSElaine Zhang unsigned int reserved12[15933]; 8176f3cd6aSElaine Zhang unsigned int core_clksel_con[3]; 8276f3cd6aSElaine Zhang unsigned int reserved13[16381]; 8376f3cd6aSElaine Zhang unsigned int ddr_clksel_con[1]; 8476f3cd6aSElaine Zhang unsigned int reserved14[16207]; 8576f3cd6aSElaine Zhang struct rv1103b_pll pll[2]; 8676f3cd6aSElaine Zhang unsigned int reserved15[128]; 8776f3cd6aSElaine Zhang unsigned int mode; 8876f3cd6aSElaine Zhang unsigned int reserved16[31]; 8976f3cd6aSElaine Zhang unsigned int clksel_con[42]; 9076f3cd6aSElaine Zhang unsigned int reserved17[278]; 9176f3cd6aSElaine Zhang unsigned int clkgate_con[7]; 9276f3cd6aSElaine Zhang unsigned int reserved18[121]; 9376f3cd6aSElaine Zhang unsigned int softrst_con[1]; 9476f3cd6aSElaine Zhang unsigned int reserved19[127]; 9576f3cd6aSElaine Zhang unsigned int glb_cnt_th; 9676f3cd6aSElaine Zhang unsigned int glb_rst_st; 9776f3cd6aSElaine Zhang unsigned int glb_srst_fst; 9876f3cd6aSElaine Zhang unsigned int glb_srst_snd; 9976f3cd6aSElaine Zhang unsigned int glb_rst_con; 10076f3cd6aSElaine Zhang unsigned int reserved20[15803]; 10176f3cd6aSElaine Zhang unsigned int pmu_clksel_con[3]; 10276f3cd6aSElaine Zhang unsigned int reserved21[317]; 10376f3cd6aSElaine Zhang unsigned int pmu_clkgate_con[3]; 10476f3cd6aSElaine Zhang unsigned int reserved22[125]; 10576f3cd6aSElaine Zhang unsigned int pmu_softrst_con[3]; 10676f3cd6aSElaine Zhang unsigned int reserved23[15933]; 10776f3cd6aSElaine Zhang unsigned int pmu1_clksel_con[1]; 10876f3cd6aSElaine Zhang unsigned int reserved24[319]; 10976f3cd6aSElaine Zhang unsigned int pmu1_clkgate_con[2]; 11076f3cd6aSElaine Zhang unsigned int reserved25[126]; 11176f3cd6aSElaine Zhang unsigned int pmu1_softrst_con[2]; 11276f3cd6aSElaine Zhang }; 11376f3cd6aSElaine Zhang check_member(rv1103b_cru, pmu1_softrst_con[1], 0x80a04); 11476f3cd6aSElaine Zhang 11576f3cd6aSElaine Zhang struct pll_rate_table { 11676f3cd6aSElaine Zhang unsigned long rate; 11776f3cd6aSElaine Zhang unsigned int fbdiv; 11876f3cd6aSElaine Zhang unsigned int postdiv1; 11976f3cd6aSElaine Zhang unsigned int refdiv; 12076f3cd6aSElaine Zhang unsigned int postdiv2; 12176f3cd6aSElaine Zhang unsigned int dsmpd; 12276f3cd6aSElaine Zhang unsigned int frac; 12376f3cd6aSElaine Zhang }; 12476f3cd6aSElaine Zhang 12576f3cd6aSElaine Zhang #define RV1103B_TOPCRU_BASE 0x60000 12676f3cd6aSElaine Zhang #define RV1103B_PERICRU_BASE 0x0 12776f3cd6aSElaine Zhang #define RV1103B_VICRU_BASE 0x30000 12876f3cd6aSElaine Zhang #define RV1103B_NPUCRU_BASE 0x20000 12976f3cd6aSElaine Zhang #define RV1103B_CORECRU_BASE 0x40000 13076f3cd6aSElaine Zhang #define RV1103B_VEPUCRU_BASE 0x10000 13176f3cd6aSElaine Zhang #define RV1103B_DDRCRU_BASE 0x50000 13276f3cd6aSElaine Zhang #define RV1103B_SUBDDRCRU_BASE 0x58000 13376f3cd6aSElaine Zhang #define RV1103B_PMUCRU_BASE 0x70000 13476f3cd6aSElaine Zhang #define RV1103B_PMU1CRU_BASE 0x80000 13576f3cd6aSElaine Zhang 13676f3cd6aSElaine Zhang #define RV1103B_CRU_BASE 0x20000000 13776f3cd6aSElaine Zhang 13876f3cd6aSElaine Zhang #define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE) 13976f3cd6aSElaine Zhang #define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE) 14076f3cd6aSElaine Zhang #define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE) 14176f3cd6aSElaine Zhang #define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE) 14276f3cd6aSElaine Zhang 14376f3cd6aSElaine Zhang enum { 14476f3cd6aSElaine Zhang /* CORECRU_CLK_SEL0_CON */ 14576f3cd6aSElaine Zhang CLK_CORE_SRC_SEL_SHIFT = 1, 14676f3cd6aSElaine Zhang CLK_CORE_SRC_SEL_MASK = 0x1 << CLK_CORE_SRC_SEL_SHIFT, 14776f3cd6aSElaine Zhang CLK_CORE_SRC_SEL_GPLL = 0, 14876f3cd6aSElaine Zhang CLK_CORE_SRC_SEL_PVTPLL, 14976f3cd6aSElaine Zhang 15076f3cd6aSElaine Zhang /* CRU_PERI_CLK_SEL0_CON */ 15176f3cd6aSElaine Zhang CLK_TSADC_TSEN_DIV_SHIFT = 10, 15276f3cd6aSElaine Zhang CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT, 15376f3cd6aSElaine Zhang CLK_TSADC_DIV_SHIFT = 4, 15476f3cd6aSElaine Zhang CLK_TSADC_DIV_MASK = 0x1f << CLK_TSADC_DIV_SHIFT, 15576f3cd6aSElaine Zhang PCLK_PERI_DIV_SHIFT = 0, 15676f3cd6aSElaine Zhang PCLK_PERI_DIV_MASK = 0x3 << PCLK_PERI_DIV_SHIFT, 15776f3cd6aSElaine Zhang 15876f3cd6aSElaine Zhang /* CRU_PERI_CLK_SEL1_CON */ 15976f3cd6aSElaine Zhang CLK_SARADC_DIV_SHIFT = 0, 16076f3cd6aSElaine Zhang CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 16176f3cd6aSElaine Zhang 16276f3cd6aSElaine Zhang /* CRU_CLK_SEL5_CON */ 16376f3cd6aSElaine Zhang CLK_UART2_SRC_DIV_SHIFT = 10, 16476f3cd6aSElaine Zhang CLK_UART2_SRC_DIV_MASK = 0x1f << CLK_UART2_SRC_DIV_SHIFT, 16576f3cd6aSElaine Zhang CLK_UART1_SRC_DIV_SHIFT = 5, 16676f3cd6aSElaine Zhang CLK_UART1_SRC_DIV_MASK = 0x1f << CLK_UART1_SRC_DIV_SHIFT, 16776f3cd6aSElaine Zhang CLK_UART0_SRC_DIV_SHIFT = 0, 16876f3cd6aSElaine Zhang CLK_UART0_SRC_DIV_MASK = 0x1f << CLK_UART0_SRC_DIV_SHIFT, 16976f3cd6aSElaine Zhang 17076f3cd6aSElaine Zhang /* CRU_CLK_SEL10_CON */ 17176f3cd6aSElaine Zhang CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 17276f3cd6aSElaine Zhang CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 17376f3cd6aSElaine Zhang CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 17476f3cd6aSElaine Zhang CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 17576f3cd6aSElaine Zhang 17676f3cd6aSElaine Zhang /* CRU_CLK_SEL31_CON */ 17776f3cd6aSElaine Zhang CLK_EMMC_SEL_SHIFT = 15, 17876f3cd6aSElaine Zhang CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT, 17976f3cd6aSElaine Zhang ACLK_PERI_SEL_SHIFT = 10, 18076f3cd6aSElaine Zhang ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT, 18176f3cd6aSElaine Zhang ACLK_PERI_SEL_600M = 0, 18276f3cd6aSElaine Zhang ACLK_PERI_SEL_480M, 18376f3cd6aSElaine Zhang ACLK_PERI_SEL_400M, 18476f3cd6aSElaine Zhang LSCLK_PERI_SEL_SHIFT = 9, 18576f3cd6aSElaine Zhang LSCLK_PERI_SEL_MASK = 0x1 << LSCLK_PERI_SEL_SHIFT, 18676f3cd6aSElaine Zhang LSCLK_PERI_SEL_300M = 0, 18776f3cd6aSElaine Zhang LSCLK_PERI_SEL_200M, 18876f3cd6aSElaine Zhang CLK_EMMC_DIV_SHIFT = 0, 18976f3cd6aSElaine Zhang CLK_EMMC_DIV_MASK = 0xff << CLK_EMMC_DIV_SHIFT, 19076f3cd6aSElaine Zhang 19176f3cd6aSElaine Zhang /* CRU_CLK_SEL32_CON */ 19276f3cd6aSElaine Zhang CLK_SDMMC_SEL_SHIFT = 15, 19376f3cd6aSElaine Zhang CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT, 19476f3cd6aSElaine Zhang CLK_MMC_SEL_GPLL = 0, 19576f3cd6aSElaine Zhang CLK_MMC_SEL_OSC, 19676f3cd6aSElaine Zhang CLK_UART2_SEL_SHIFT = 12, 19776f3cd6aSElaine Zhang CLK_UART2_SEL_MASK = 3 << CLK_UART2_SEL_SHIFT, 19876f3cd6aSElaine Zhang CLK_UART1_SEL_SHIFT = 10, 19976f3cd6aSElaine Zhang CLK_UART1_SEL_MASK = 3 << CLK_UART1_SEL_SHIFT, 20076f3cd6aSElaine Zhang CLK_UART0_SEL_SHIFT = 8, 20176f3cd6aSElaine Zhang CLK_UART0_SEL_MASK = 3 << CLK_UART0_SEL_SHIFT, 20276f3cd6aSElaine Zhang CLK_UART_SEL_SRC = 0, 20376f3cd6aSElaine Zhang CLK_UART_SEL_FRAC, 20476f3cd6aSElaine Zhang CLK_UART_SEL_OSC, 20576f3cd6aSElaine Zhang CLK_SDMMC_DIV_SHIFT = 0, 20676f3cd6aSElaine Zhang CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT, 20776f3cd6aSElaine Zhang 208*0d477f41SXuhui Lin /* CRU_CLK_SEL33_CON */ 209*0d477f41SXuhui Lin CLK_SFC_SEL_SHIFT = 15, 210*0d477f41SXuhui Lin CLK_SFC_SEL_MASK = 0x1 << CLK_SFC_SEL_SHIFT, 211*0d477f41SXuhui Lin CLK_SFC_DIV_SHIFT = 0, 212*0d477f41SXuhui Lin CLK_SFC_DIV_MASK = 0xff << CLK_SFC_DIV_SHIFT, 213*0d477f41SXuhui Lin 21476f3cd6aSElaine Zhang /* CRU_CLK_SEL34_CON */ 21576f3cd6aSElaine Zhang CLK_PWM2_SEL_SHIFT = 14, 21676f3cd6aSElaine Zhang CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 21776f3cd6aSElaine Zhang CLK_PWM1_SEL_SHIFT = 13, 21876f3cd6aSElaine Zhang CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 21976f3cd6aSElaine Zhang CLK_PWM0_SEL_SHIFT = 12, 22076f3cd6aSElaine Zhang CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 22176f3cd6aSElaine Zhang CLK_PWM_SEL_100M = 0, 22276f3cd6aSElaine Zhang CLK_PWM_SEL_24M, 22376f3cd6aSElaine Zhang CLK_SPI0_SEL_SHIFT = 2, 22476f3cd6aSElaine Zhang CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 22576f3cd6aSElaine Zhang CLK_SPI0_SEL_200M = 0, 22676f3cd6aSElaine Zhang CLK_SPI0_SEL_100M, 22776f3cd6aSElaine Zhang CLK_SPI0_SEL_50M, 22876f3cd6aSElaine Zhang CLK_SPI0_SEL_24M, 22976f3cd6aSElaine Zhang CLK_I2C1_SEL_SHIFT = 1, 23076f3cd6aSElaine Zhang CLK_I2C1_SEL_MASK = 0x1 << CLK_I2C1_SEL_SHIFT, 23176f3cd6aSElaine Zhang CLK_I2C0_SEL_SHIFT = 0, 23276f3cd6aSElaine Zhang CLK_I2C0_SEL_MASK = 0x1 << CLK_I2C0_SEL_SHIFT, 23376f3cd6aSElaine Zhang CLK_I2C_SEL_100M = 0, 23476f3cd6aSElaine Zhang CLK_I2C_SEL_24M, 23576f3cd6aSElaine Zhang 23676f3cd6aSElaine Zhang /* CRU_CLK_SEL35_CON */ 23776f3cd6aSElaine Zhang CLK_PKA_CRYPTO_SEL_SHIFT = 4, 23876f3cd6aSElaine Zhang CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 23976f3cd6aSElaine Zhang CLK_CORE_CRYPTO_SEL_SHIFT = 2, 24076f3cd6aSElaine Zhang CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 24176f3cd6aSElaine Zhang CLK_CORE_CRYPTO_SEL_300M = 0, 24276f3cd6aSElaine Zhang CLK_CORE_CRYPTO_SEL_200M, 24376f3cd6aSElaine Zhang CLK_CORE_CRYPTO_SEL_100M, 24476f3cd6aSElaine Zhang DCLK_DECOM_SEL_SHIFT = 0, 24576f3cd6aSElaine Zhang DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT, 24676f3cd6aSElaine Zhang DCLK_DECOM_SEL_480M = 0, 24776f3cd6aSElaine Zhang DCLK_DECOM_SEL_400M, 24876f3cd6aSElaine Zhang DCLK_DECOM_SEL_300M, 24976f3cd6aSElaine Zhang 25076f3cd6aSElaine Zhang /* CRU_CLK_SEL37_CON */ 25176f3cd6aSElaine Zhang CLK_CORE_GPLL_DIV_SHIFT = 13, 25276f3cd6aSElaine Zhang CLK_CORE_GPLL_DIV_MASK = 0x7 << CLK_CORE_GPLL_DIV_SHIFT, 25376f3cd6aSElaine Zhang CLK_CORE_GPLL_SEL_SHIFT = 12, 25476f3cd6aSElaine Zhang CLK_CORE_GPLL_SEL_MASK = 0x1 << CLK_CORE_GPLL_SEL_SHIFT, 25576f3cd6aSElaine Zhang CLK_CORE_GPLL_SEL_GPLL = 0, 25676f3cd6aSElaine Zhang CLK_CORE_GPLL_SEL_OSC, 25776f3cd6aSElaine Zhang 25876f3cd6aSElaine Zhang /* CRU_PMU_CLK_SEL2_CON */ 25976f3cd6aSElaine Zhang LSCLK_PMU_SEL_SHIFT = 4, 26076f3cd6aSElaine Zhang LSCLK_PMU_SEL_MASK = 0x1 << LSCLK_PMU_SEL_SHIFT, 26176f3cd6aSElaine Zhang LSCLK_PMU_SEL_24M = 0, 26276f3cd6aSElaine Zhang LSCLK_PMU_SEL_RC_OSC, 26376f3cd6aSElaine Zhang LSCLK_PMU_DIV_SHIFT = 0, 26476f3cd6aSElaine Zhang LSCLK_PMU_DIV_MASK = 0x3 << LSCLK_PMU_DIV_SHIFT, 26576f3cd6aSElaine Zhang 26676f3cd6aSElaine Zhang }; 26776f3cd6aSElaine Zhang #endif 268