| /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 20 #define DPLL 9 macro
|
| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
186 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
187 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
275 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
276 priv->cru, DPLL); in rk3308_mac_set_clk()
943 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_rate()
944 priv->cru, DPLL); in rk3308_clk_get_rate()
1026 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru, in rk3308_clk_set_rate()
1027 DPLL, rate); in rk3308_clk_set_rate()
1028 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_set_rate()
[all …]
|
| H A D | clk_rk322x.c | 84 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(3),
674 ret = rockchip_pll_set_rate(&rk322x_pll_clks[DPLL], in rk322x_clk_set_rate()
675 priv->cru, DPLL, rate); in rk322x_clk_set_rate()
|
| H A D | clk_rv1106.c | 41 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1106_PLL_CON(16),
1056 rate = rockchip_pll_get_rate(&rv1106_pll_clks[DPLL], priv->cru, in rv1106_clk_get_rate()
1057 DPLL); in rv1106_clk_get_rate()
|
| H A D | clk_rk3528.c | 78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
1363 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, in rk3528_clk_get_rate()
1364 DPLL); in rk3528_clk_get_rate()
|
| H A D | clk_rk3562.c | 57 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3562_SUBDDR_PLL_CON(0),
1388 rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru, in rk3562_clk_get_rate()
1389 DPLL); in rk3562_clk_get_rate()
|
| H A D | clk_rk3368.c | 441 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
1283 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
|
| H A D | clk_rv1126.c | 62 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8),
1637 rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, in rv1126_clk_get_rate()
1638 DPLL); in rv1126_clk_get_rate()
|
| H A D | clk_rk3128.c | 83 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(4),
|
| H A D | clk_rk3568.c | 70 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
2550 rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru, in rk3568_clk_get_rate()
2551 DPLL); in rk3568_clk_get_rate()
|
| /rk3399_rockchip-uboot/board/rockchip/evb_rv1108/ |
| H A D | README | 31 APLL: 400000000 DPLL:798000000 GPLL:384000000
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3128.h | 64 DPLL, enumerator
|
| H A D | cru_rk3368.h | 16 DPLL, enumerator
|
| H A D | cru_rk322x.h | 61 DPLL, enumerator
|
| H A D | cru_rk3328.h | 59 DPLL, enumerator
|
| H A D | cru_rv1106.h | 27 DPLL, enumerator
|
| H A D | cru_rk1808.h | 21 DPLL, enumerator
|
| H A D | cru_rv1126.h | 49 DPLL, enumerator
|
| H A D | cru_px30.h | 28 DPLL, enumerator
|
| H A D | cru_rk3528.h | 26 DPLL, enumerator
|
| H A D | cru_rk3562.h | 29 DPLL, enumerator
|
| H A D | cru_rk3568.h | 22 DPLL, enumerator
|
| H A D | cru_rk3576.h | 25 DPLL, enumerator
|
| H A D | cru_rk3308.h | 36 DPLL, enumerator
|
| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 202 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
270 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
333 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
|