1417bebc4SElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 2417bebc4SElaine Zhang /* 3417bebc4SElaine Zhang * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4417bebc4SElaine Zhang * Author: Elaine Zhang <zhangqing@rock-chips.com> 5417bebc4SElaine Zhang */ 6417bebc4SElaine Zhang 7417bebc4SElaine Zhang #ifndef _ASM_ARCH_CRU_RK3568_H 8417bebc4SElaine Zhang #define _ASM_ARCH_CRU_RK3568_H 9417bebc4SElaine Zhang 10417bebc4SElaine Zhang #define MHz 1000000 11417bebc4SElaine Zhang #define KHz 1000 12417bebc4SElaine Zhang #define OSC_HZ (24 * MHz) 13417bebc4SElaine Zhang 143a5404afSJason Zhu #define APLL_HZ (816 * MHz) 15417bebc4SElaine Zhang #define GPLL_HZ (1188 * MHz) 16417bebc4SElaine Zhang #define CPLL_HZ (1000 * MHz) 1702155da2SElaine Zhang #define PPLL_HZ (200 * MHz) 18417bebc4SElaine Zhang 19417bebc4SElaine Zhang /* RK3568 pll id */ 20417bebc4SElaine Zhang enum rk3568_pll_id { 21417bebc4SElaine Zhang APLL, 22417bebc4SElaine Zhang DPLL, 23417bebc4SElaine Zhang CPLL, 24417bebc4SElaine Zhang GPLL, 25417bebc4SElaine Zhang NPLL, 26417bebc4SElaine Zhang VPLL, 27417bebc4SElaine Zhang PPLL, 28417bebc4SElaine Zhang HPLL, 29417bebc4SElaine Zhang PLL_COUNT, 30417bebc4SElaine Zhang }; 31417bebc4SElaine Zhang 32417bebc4SElaine Zhang struct rk3568_clk_info { 33417bebc4SElaine Zhang unsigned long id; 34417bebc4SElaine Zhang char *name; 35417bebc4SElaine Zhang bool is_cru; 36417bebc4SElaine Zhang }; 37417bebc4SElaine Zhang 38417bebc4SElaine Zhang /* Private data for the clock driver - used by rockchip_get_cru() */ 39417bebc4SElaine Zhang struct rk3568_pmuclk_priv { 40417bebc4SElaine Zhang struct rk3568_pmucru *pmucru; 41417bebc4SElaine Zhang ulong ppll_hz; 42417bebc4SElaine Zhang ulong hpll_hz; 43417bebc4SElaine Zhang }; 44417bebc4SElaine Zhang 45417bebc4SElaine Zhang struct rk3568_clk_priv { 46417bebc4SElaine Zhang struct rk3568_cru *cru; 47417bebc4SElaine Zhang struct rk3568_grf *grf; 48417bebc4SElaine Zhang ulong ppll_hz; 49417bebc4SElaine Zhang ulong hpll_hz; 50417bebc4SElaine Zhang ulong gpll_hz; 51417bebc4SElaine Zhang ulong cpll_hz; 52417bebc4SElaine Zhang ulong npll_hz; 53417bebc4SElaine Zhang ulong vpll_hz; 54417bebc4SElaine Zhang ulong armclk_hz; 55417bebc4SElaine Zhang ulong armclk_enter_hz; 56417bebc4SElaine Zhang ulong armclk_init_hz; 57417bebc4SElaine Zhang bool sync_kernel; 58417bebc4SElaine Zhang bool set_armclk_rate; 59417bebc4SElaine Zhang }; 60417bebc4SElaine Zhang 61417bebc4SElaine Zhang struct rk3568_pll { 62417bebc4SElaine Zhang unsigned int con0; 63417bebc4SElaine Zhang unsigned int con1; 64417bebc4SElaine Zhang unsigned int con2; 65417bebc4SElaine Zhang unsigned int con3; 66417bebc4SElaine Zhang unsigned int con4; 67417bebc4SElaine Zhang unsigned int reserved0[3]; 68417bebc4SElaine Zhang }; 69417bebc4SElaine Zhang 70417bebc4SElaine Zhang struct rk3568_pmucru { 71417bebc4SElaine Zhang struct rk3568_pll pll[2];/* Address Offset: 0x0000 */ 72417bebc4SElaine Zhang unsigned int reserved0[16];/* Address Offset: 0x0040 */ 73417bebc4SElaine Zhang unsigned int mode_con00;/* Address Offset: 0x0080 */ 74417bebc4SElaine Zhang unsigned int reserved1[31];/* Address Offset: 0x0084 */ 75417bebc4SElaine Zhang unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */ 76417bebc4SElaine Zhang unsigned int reserved2[22];/* Address Offset: 0x0128 */ 77417bebc4SElaine Zhang unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */ 78417bebc4SElaine Zhang unsigned int reserved3[29];/* Address Offset: 0x018C */ 79417bebc4SElaine Zhang unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */ 80417bebc4SElaine Zhang }; 81417bebc4SElaine Zhang 82417bebc4SElaine Zhang check_member(rk3568_pmucru, mode_con00, 0x80); 83417bebc4SElaine Zhang check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200); 84417bebc4SElaine Zhang 85417bebc4SElaine Zhang struct rk3568_cru { 86417bebc4SElaine Zhang struct rk3568_pll pll[6]; 87417bebc4SElaine Zhang unsigned int mode_con00;/* Address Offset: 0x00C0 */ 88417bebc4SElaine Zhang unsigned int misc_con[3];/* Address Offset: 0x00C4 */ 89417bebc4SElaine Zhang unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */ 90417bebc4SElaine Zhang unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */ 91417bebc4SElaine Zhang unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */ 92417bebc4SElaine Zhang unsigned int glb_rst_con;/* Address Offset: 0x00DC */ 93417bebc4SElaine Zhang unsigned int glb_rst_st;/* Address Offset: 0x00E0 */ 94417bebc4SElaine Zhang unsigned int reserved0[7];/* Address Offset: 0x00E4 */ 95417bebc4SElaine Zhang unsigned int clksel_con[85]; /* Address Offset: 0x0100 */ 96417bebc4SElaine Zhang unsigned int reserved1[43];/* Address Offset: 0x0254 */ 97417bebc4SElaine Zhang unsigned int clkgate_con[36];/* Address Offset: 0x0300 */ 98417bebc4SElaine Zhang unsigned int reserved2[28]; /* Address Offset: 0x0390 */ 99417bebc4SElaine Zhang unsigned int softrst_con[30];/* Address Offset: 0x0400 */ 100417bebc4SElaine Zhang unsigned int reserved3[2];/* Address Offset: 0x0478 */ 101417bebc4SElaine Zhang unsigned int ssgtbl[32];/* Address Offset: 0x0480 */ 102417bebc4SElaine Zhang unsigned int reserved4[32];/* Address Offset: 0x0500 */ 103417bebc4SElaine Zhang unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */ 104417bebc4SElaine Zhang unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */ 105417bebc4SElaine Zhang unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */ 106417bebc4SElaine Zhang unsigned int emmc_con[2];/* Address Offset: 0x0598 */ 107417bebc4SElaine Zhang }; 108417bebc4SElaine Zhang 109417bebc4SElaine Zhang check_member(rk3568_cru, mode_con00, 0xc0); 110417bebc4SElaine Zhang check_member(rk3568_cru, softrst_con[0], 0x400); 111417bebc4SElaine Zhang 112417bebc4SElaine Zhang struct pll_rate_table { 113417bebc4SElaine Zhang unsigned long rate; 114417bebc4SElaine Zhang unsigned int fbdiv; 115417bebc4SElaine Zhang unsigned int postdiv1; 116417bebc4SElaine Zhang unsigned int refdiv; 117417bebc4SElaine Zhang unsigned int postdiv2; 118417bebc4SElaine Zhang unsigned int dsmpd; 119417bebc4SElaine Zhang unsigned int frac; 120417bebc4SElaine Zhang }; 121417bebc4SElaine Zhang 122417bebc4SElaine Zhang #define RK3568_PMU_MODE 0x80 123417bebc4SElaine Zhang #define RK3568_PMU_PLL_CON(x) ((x) * 0x4) 124417bebc4SElaine Zhang #define RK3568_PLL_CON(x) ((x) * 0x4) 125417bebc4SElaine Zhang #define RK3568_MODE_CON 0xc0 126417bebc4SElaine Zhang 127417bebc4SElaine Zhang enum { 128417bebc4SElaine Zhang /* CRU_PMU_CLK_SEL0_CON */ 129417bebc4SElaine Zhang RTC32K_SEL_SHIFT = 6, 130417bebc4SElaine Zhang RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 131417bebc4SElaine Zhang RTC32K_SEL_PMUPVTM = 0, 132417bebc4SElaine Zhang RTC32K_SEL_OSC1_32K, 133417bebc4SElaine Zhang RTC32K_SEL_OSC0_DIV32K, 134417bebc4SElaine Zhang 135417bebc4SElaine Zhang /* CRU_PMU_CLK_SEL1_CON */ 136417bebc4SElaine Zhang RTC32K_FRAC_NUMERATOR_SHIFT = 16, 137417bebc4SElaine Zhang RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 138417bebc4SElaine Zhang RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 139417bebc4SElaine Zhang RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 140417bebc4SElaine Zhang 141417bebc4SElaine Zhang /* CRU_PMU_CLK_SEL2_CON */ 142417bebc4SElaine Zhang PCLK_PDPMU_SEL_SHIFT = 15, 143417bebc4SElaine Zhang PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT, 144417bebc4SElaine Zhang PCLK_PDPMU_SEL_PPLL = 0, 145417bebc4SElaine Zhang PCLK_PDPMU_SEL_GPLL, 146417bebc4SElaine Zhang PCLK_PDPMU_DIV_SHIFT = 0, 147417bebc4SElaine Zhang PCLK_PDPMU_DIV_MASK = 0x1f, 148417bebc4SElaine Zhang 149417bebc4SElaine Zhang /* CRU_PMU_CLK_SEL3_CON */ 150417bebc4SElaine Zhang CLK_I2C0_DIV_SHIFT = 0, 151417bebc4SElaine Zhang CLK_I2C0_DIV_MASK = 0x7f, 152417bebc4SElaine Zhang 153417bebc4SElaine Zhang /* CRU_PMU_CLK_SEL6_CON */ 154417bebc4SElaine Zhang CLK_PWM0_SEL_SHIFT = 7, 155417bebc4SElaine Zhang CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 156417bebc4SElaine Zhang CLK_PWM0_SEL_XIN24M = 0, 157417bebc4SElaine Zhang CLK_PWM0_SEL_PPLL, 158417bebc4SElaine Zhang CLK_PWM0_DIV_SHIFT = 0, 159417bebc4SElaine Zhang CLK_PWM0_DIV_MASK = 0x7f, 160417bebc4SElaine Zhang 161417bebc4SElaine Zhang /* CRU_CLK_SEL0_CON */ 162417bebc4SElaine Zhang CLK_CORE_PRE_SEL_SHIFT = 7, 163417bebc4SElaine Zhang CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT, 164417bebc4SElaine Zhang CLK_CORE_PRE_SEL_SRC = 0, 165417bebc4SElaine Zhang CLK_CORE_PRE_SEL_APLL, 166417bebc4SElaine Zhang 167417bebc4SElaine Zhang /* CRU_CLK_SEL2_CON */ 168417bebc4SElaine Zhang SCLK_CORE_PRE_SEL_SHIFT = 15, 169417bebc4SElaine Zhang SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT, 170417bebc4SElaine Zhang SCLK_CORE_PRE_SEL_SRC = 0, 171417bebc4SElaine Zhang SCLK_CORE_PRE_SEL_NPLL, 172417bebc4SElaine Zhang SCLK_CORE_SRC_SEL_SHIFT = 8, 173417bebc4SElaine Zhang SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT, 174417bebc4SElaine Zhang SCLK_CORE_SRC_SEL_APLL = 0, 175417bebc4SElaine Zhang SCLK_CORE_SRC_SEL_GPLL, 176417bebc4SElaine Zhang SCLK_CORE_SRC_SEL_NPLL, 177417bebc4SElaine Zhang SCLK_CORE_SRC_DIV_SHIFT = 0, 178417bebc4SElaine Zhang SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT, 179417bebc4SElaine Zhang 180417bebc4SElaine Zhang /* CRU_CLK_SEL3_CON */ 181417bebc4SElaine Zhang GICCLK_CORE_DIV_SHIFT = 8, 182417bebc4SElaine Zhang GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT, 183417bebc4SElaine Zhang ATCLK_CORE_DIV_SHIFT = 0, 184417bebc4SElaine Zhang ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT, 185417bebc4SElaine Zhang 186417bebc4SElaine Zhang /* CRU_CLK_SEL4_CON */ 187417bebc4SElaine Zhang PERIPHCLK_CORE_PRE_DIV_SHIFT = 8, 188417bebc4SElaine Zhang PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT, 189417bebc4SElaine Zhang PCLK_CORE_PRE_DIV_SHIFT = 0, 190417bebc4SElaine Zhang PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT, 191417bebc4SElaine Zhang 192417bebc4SElaine Zhang /* CRU_CLK_SEL5_CON */ 193417bebc4SElaine Zhang ACLK_CORE_NIU2BUS_SEL_SHIFT = 14, 194417bebc4SElaine Zhang ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT, 195417bebc4SElaine Zhang ACLK_CORE_NDFT_DIV_SHIFT = 8, 196417bebc4SElaine Zhang ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT, 197417bebc4SElaine Zhang 198417bebc4SElaine Zhang /* CRU_CLK_SEL10_CON */ 199417bebc4SElaine Zhang HCLK_PERIMID_SEL_SHIFT = 6, 200417bebc4SElaine Zhang HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT, 201417bebc4SElaine Zhang HCLK_PERIMID_SEL_150M = 0, 202417bebc4SElaine Zhang HCLK_PERIMID_SEL_100M, 203417bebc4SElaine Zhang HCLK_PERIMID_SEL_75M, 204417bebc4SElaine Zhang HCLK_PERIMID_SEL_24M, 205417bebc4SElaine Zhang ACLK_PERIMID_SEL_SHIFT = 4, 206417bebc4SElaine Zhang ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT, 207417bebc4SElaine Zhang ACLK_PERIMID_SEL_300M = 0, 208417bebc4SElaine Zhang ACLK_PERIMID_SEL_200M, 209417bebc4SElaine Zhang ACLK_PERIMID_SEL_100M, 210417bebc4SElaine Zhang ACLK_PERIMID_SEL_24M, 211417bebc4SElaine Zhang 21226663c2dSElaine Zhang /* CRU_CLK_SEL21_CON */ 21326663c2dSElaine Zhang I2S3_MCLKOUT_TX_SEL_SHIFT = 15, 21426663c2dSElaine Zhang I2S3_MCLKOUT_TX_SEL_MASK = 1 << I2S3_MCLKOUT_TX_SEL_SHIFT, 21526663c2dSElaine Zhang I2S3_MCLKOUT_TX_SEL_MCLK = 0, 21626663c2dSElaine Zhang I2S3_MCLKOUT_TX_SEL_12M, 21726663c2dSElaine Zhang CLK_I2S3_SEL_SHIFT = 10, 21826663c2dSElaine Zhang CLK_I2S3_SEL_MASK = 0x3 << CLK_I2S3_SEL_SHIFT, 21926663c2dSElaine Zhang CLK_I2S3_SEL_SRC = 0, 22026663c2dSElaine Zhang CLK_I2S3_SEL_FRAC, 22126663c2dSElaine Zhang CLK_I2S3_SEL_CLKIN, 22226663c2dSElaine Zhang CLK_I2S3_SEL_XIN12M, 22326663c2dSElaine Zhang CLK_I2S3_SRC_SEL_SHIFT = 8, 22426663c2dSElaine Zhang CLK_I2S3_SRC_SEL_MASK = 0x3 << CLK_I2S3_SRC_SEL_SHIFT, 22526663c2dSElaine Zhang CLK_I2S3_SRC_SEL_GPLL = 0, 22626663c2dSElaine Zhang CLK_I2S3_SRC_SEL_CPLL, 22726663c2dSElaine Zhang CLK_I2S3_SRC_SEL_NPLL, 22826663c2dSElaine Zhang CLK_I2S3_SRC_DIV_SHIFT = 0, 22926663c2dSElaine Zhang CLK_I2S3_SRC_DIV_MASK = 0x7f << CLK_I2S3_SRC_DIV_SHIFT, 23026663c2dSElaine Zhang 23126663c2dSElaine Zhang /* CRU_CLK_SEL22_CON */ 23226663c2dSElaine Zhang CLK_I2S3_FRAC_NUMERATOR_SHIFT = 16, 23326663c2dSElaine Zhang CLK_I2S3_FRAC_NUMERATOR_MASK = 0xffff << 16, 23426663c2dSElaine Zhang CLK_I2S3_FRAC_DENOMINATOR_SHIFT = 0, 23526663c2dSElaine Zhang CLK_I2S3_FRAC_DENOMINATOR_MASK = 0xffff, 23626663c2dSElaine Zhang 237417bebc4SElaine Zhang /* CRU_CLK_SEL27_CON */ 238417bebc4SElaine Zhang CLK_CRYPTO_PKA_SEL_SHIFT = 6, 239417bebc4SElaine Zhang CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT, 240417bebc4SElaine Zhang CLK_CRYPTO_PKA_SEL_300M = 0, 241417bebc4SElaine Zhang CLK_CRYPTO_PKA_SEL_200M, 242417bebc4SElaine Zhang CLK_CRYPTO_PKA_SEL_100M, 243417bebc4SElaine Zhang CLK_CRYPTO_CORE_SEL_SHIFT = 4, 244417bebc4SElaine Zhang CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT, 245417bebc4SElaine Zhang CLK_CRYPTO_CORE_SEL_200M = 0, 246417bebc4SElaine Zhang CLK_CRYPTO_CORE_SEL_150M, 247417bebc4SElaine Zhang CLK_CRYPTO_CORE_SEL_100M, 248417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_SHIFT = 2, 249417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT, 250417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_150M = 0, 251417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_100M, 252417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_75M, 253417bebc4SElaine Zhang HCLK_SECURE_FLASH_SEL_24M, 254417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_SHIFT = 0, 255417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT, 256417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_200M = 0, 257417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_150M, 258417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_100M, 259417bebc4SElaine Zhang ACLK_SECURE_FLASH_SEL_24M, 260417bebc4SElaine Zhang 261417bebc4SElaine Zhang /* CRU_CLK_SEL28_CON */ 262417bebc4SElaine Zhang CCLK_EMMC_SEL_SHIFT = 12, 263417bebc4SElaine Zhang CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT, 264417bebc4SElaine Zhang CCLK_EMMC_SEL_24M = 0, 265417bebc4SElaine Zhang CCLK_EMMC_SEL_200M, 266417bebc4SElaine Zhang CCLK_EMMC_SEL_150M, 267417bebc4SElaine Zhang CCLK_EMMC_SEL_100M, 268417bebc4SElaine Zhang CCLK_EMMC_SEL_50M, 269417bebc4SElaine Zhang CCLK_EMMC_SEL_375K, 270417bebc4SElaine Zhang BCLK_EMMC_SEL_SHIFT = 8, 271417bebc4SElaine Zhang BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, 272417bebc4SElaine Zhang BCLK_EMMC_SEL_200M = 0, 273417bebc4SElaine Zhang BCLK_EMMC_SEL_150M, 274417bebc4SElaine Zhang BCLK_EMMC_SEL_125M, 275417bebc4SElaine Zhang SCLK_SFC_SEL_SHIFT = 4, 276417bebc4SElaine Zhang SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT, 277417bebc4SElaine Zhang SCLK_SFC_SEL_24M = 0, 278417bebc4SElaine Zhang SCLK_SFC_SEL_50M, 279417bebc4SElaine Zhang SCLK_SFC_SEL_75M, 280417bebc4SElaine Zhang SCLK_SFC_SEL_100M, 281417bebc4SElaine Zhang SCLK_SFC_SEL_125M, 282417bebc4SElaine Zhang SCLK_SFC_SEL_150M, 283417bebc4SElaine Zhang NCLK_NANDC_SEL_SHIFT = 0, 284417bebc4SElaine Zhang NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT, 285417bebc4SElaine Zhang NCLK_NANDC_SEL_200M = 0, 286417bebc4SElaine Zhang NCLK_NANDC_SEL_150M, 287417bebc4SElaine Zhang NCLK_NANDC_SEL_100M, 288417bebc4SElaine Zhang NCLK_NANDC_SEL_24M, 289417bebc4SElaine Zhang 290417bebc4SElaine Zhang /* CRU_CLK_SEL30_CON */ 291417bebc4SElaine Zhang CLK_SDMMC1_SEL_SHIFT = 12, 292417bebc4SElaine Zhang CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT, 293417bebc4SElaine Zhang CLK_SDMMC0_SEL_SHIFT = 8, 294417bebc4SElaine Zhang CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT, 295417bebc4SElaine Zhang CLK_SDMMC_SEL_24M = 0, 296417bebc4SElaine Zhang CLK_SDMMC_SEL_400M, 297417bebc4SElaine Zhang CLK_SDMMC_SEL_300M, 298417bebc4SElaine Zhang CLK_SDMMC_SEL_100M, 299417bebc4SElaine Zhang CLK_SDMMC_SEL_50M, 300417bebc4SElaine Zhang CLK_SDMMC_SEL_750K, 301417bebc4SElaine Zhang 302417bebc4SElaine Zhang /* CRU_CLK_SEL31_CON */ 303417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_SHIFT = 14, 304417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT, 305417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_125M = 0, 306417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_50M, 307417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_25M, 308417bebc4SElaine Zhang CLK_MAC0_OUT_SEL_24M, 309417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_SHIFT = 12, 310417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT, 311417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_62_5M = 0, 312417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_100M, 313417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_50M, 314417bebc4SElaine Zhang CLK_GMAC0_PTP_REF_SEL_24M, 315417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_SHIFT = 8, 316417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT, 317417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_125M = 0, 318417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_50M, 319417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_25M, 320417bebc4SElaine Zhang CLK_MAC0_2TOP_SEL_PPLL, 321417bebc4SElaine Zhang RGMII0_CLK_SEL_SHIFT = 4, 322417bebc4SElaine Zhang RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT, 323417bebc4SElaine Zhang RGMII0_CLK_SEL_125M = 0, 324417bebc4SElaine Zhang RGMII0_CLK_SEL_125M_1, 325417bebc4SElaine Zhang RGMII0_CLK_SEL_2_5M, 326417bebc4SElaine Zhang RGMII0_CLK_SEL_25M, 327417bebc4SElaine Zhang RMII0_CLK_SEL_SHIFT = 3, 328417bebc4SElaine Zhang RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT, 329417bebc4SElaine Zhang RMII0_CLK_SEL_2_5M = 0, 330417bebc4SElaine Zhang RMII0_CLK_SEL_25M, 331417bebc4SElaine Zhang RMII0_EXTCLK_SEL_SHIFT = 2, 332417bebc4SElaine Zhang RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT, 333417bebc4SElaine Zhang RMII0_EXTCLK_SEL_MAC0_TOP = 0, 334417bebc4SElaine Zhang RMII0_EXTCLK_SEL_IO, 335417bebc4SElaine Zhang RMII0_MODE_SHIFT = 0, 336417bebc4SElaine Zhang RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT, 337417bebc4SElaine Zhang RMII0_MODE_SEL_RGMII = 0, 338417bebc4SElaine Zhang RMII0_MODE_SEL_RMII, 339417bebc4SElaine Zhang RMII0_MODE_SEL_GMII, 340417bebc4SElaine Zhang 341417bebc4SElaine Zhang /* CRU_CLK_SEL32_CON */ 342417bebc4SElaine Zhang CLK_SDMMC2_SEL_SHIFT = 8, 343417bebc4SElaine Zhang CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT, 344417bebc4SElaine Zhang 345417bebc4SElaine Zhang /* CRU_CLK_SEL38_CON */ 346417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_SHIFT = 6, 347417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT, 348417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_CPLL = 0, 349417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_GPLL, 350417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_HPLL, 351417bebc4SElaine Zhang ACLK_VOP_PRE_SEL_VPLL, 352417bebc4SElaine Zhang ACLK_VOP_PRE_DIV_SHIFT = 0, 353417bebc4SElaine Zhang ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT, 354417bebc4SElaine Zhang 355417bebc4SElaine Zhang /* CRU_CLK_SEL39_CON */ 356417bebc4SElaine Zhang DCLK0_VOP_SEL_SHIFT = 10, 357417bebc4SElaine Zhang DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT, 358417bebc4SElaine Zhang DCLK_VOP_SEL_HPLL = 0, 359417bebc4SElaine Zhang DCLK_VOP_SEL_VPLL, 360417bebc4SElaine Zhang DCLK_VOP_SEL_GPLL, 361417bebc4SElaine Zhang DCLK_VOP_SEL_CPLL, 362417bebc4SElaine Zhang DCLK0_VOP_DIV_SHIFT = 0, 363417bebc4SElaine Zhang DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT, 364417bebc4SElaine Zhang 365417bebc4SElaine Zhang /* CRU_CLK_SEL40_CON */ 366417bebc4SElaine Zhang DCLK1_VOP_SEL_SHIFT = 10, 367417bebc4SElaine Zhang DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT, 368417bebc4SElaine Zhang DCLK1_VOP_DIV_SHIFT = 0, 369417bebc4SElaine Zhang DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT, 370417bebc4SElaine Zhang 371417bebc4SElaine Zhang /* CRU_CLK_SEL41_CON */ 372417bebc4SElaine Zhang DCLK2_VOP_SEL_SHIFT = 10, 373417bebc4SElaine Zhang DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT, 374417bebc4SElaine Zhang DCLK2_VOP_DIV_SHIFT = 0, 375417bebc4SElaine Zhang DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT, 376417bebc4SElaine Zhang 377fdd74c32SElaine Zhang /* CRU_CLK_SEL43_CON */ 378fdd74c32SElaine Zhang DCLK_EBC_SEL_SHIFT = 6, 379fdd74c32SElaine Zhang DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT, 380fdd74c32SElaine Zhang DCLK_EBC_SEL_GPLL_400M = 0, 381fdd74c32SElaine Zhang DCLK_EBC_SEL_CPLL_333M, 382fdd74c32SElaine Zhang DCLK_EBC_SEL_GPLL_200M, 383fdd74c32SElaine Zhang 3840a04fb50SElaine Zhang /* CRU_CLK_SEL47_CON */ 3850a04fb50SElaine Zhang ACLK_RKVDEC_SEL_SHIFT = 7, 3860a04fb50SElaine Zhang ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT, 3870a04fb50SElaine Zhang ACLK_RKVDEC_SEL_GPLL = 0, 3880a04fb50SElaine Zhang ACLK_RKVDEC_SEL_CPLL, 3890a04fb50SElaine Zhang ACLK_RKVDEC_DIV_SHIFT = 0, 3900a04fb50SElaine Zhang ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT, 3910a04fb50SElaine Zhang 3920a04fb50SElaine Zhang /* CRU_CLK_SEL49_CON */ 3930a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_SHIFT = 14, 3940a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT, 3950a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_GPLL = 0, 3960a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_CPLL, 3970a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_NPLL, 3980a04fb50SElaine Zhang CLK_RKVDEC_CORE_SEL_VPLL, 3990a04fb50SElaine Zhang CLK_RKVDEC_CORE_DIV_SHIFT = 8, 4000a04fb50SElaine Zhang CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT, 4010a04fb50SElaine Zhang 402417bebc4SElaine Zhang /* CRU_CLK_SEL50_CON */ 403417bebc4SElaine Zhang PCLK_BUS_SEL_SHIFT = 4, 404417bebc4SElaine Zhang PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT, 405417bebc4SElaine Zhang PCLK_BUS_SEL_100M = 0, 406417bebc4SElaine Zhang PCLK_BUS_SEL_75M, 407417bebc4SElaine Zhang PCLK_BUS_SEL_50M, 408417bebc4SElaine Zhang PCLK_BUS_SEL_24M, 409417bebc4SElaine Zhang ACLK_BUS_SEL_SHIFT = 0, 410417bebc4SElaine Zhang ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT, 411417bebc4SElaine Zhang ACLK_BUS_SEL_200M = 0, 412417bebc4SElaine Zhang ACLK_BUS_SEL_150M, 413417bebc4SElaine Zhang ACLK_BUS_SEL_100M, 414417bebc4SElaine Zhang ACLK_BUS_SEL_24M, 415417bebc4SElaine Zhang 416417bebc4SElaine Zhang /* CRU_CLK_SEL51_CON */ 417417bebc4SElaine Zhang CLK_TSADC_DIV_SHIFT = 8, 418417bebc4SElaine Zhang CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT, 419417bebc4SElaine Zhang CLK_TSADC_TSEN_SEL_SHIFT = 4, 420417bebc4SElaine Zhang CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT, 421417bebc4SElaine Zhang CLK_TSADC_TSEN_SEL_24M = 0, 422417bebc4SElaine Zhang CLK_TSADC_TSEN_SEL_100M, 423417bebc4SElaine Zhang CLK_TSADC_TSEN_SEL_CPLL_100M, 424417bebc4SElaine Zhang CLK_TSADC_TSEN_DIV_SHIFT = 0, 425417bebc4SElaine Zhang CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT, 426417bebc4SElaine Zhang 427563d12f2SElaine Zhang /* CRU_CLK_SEL52_CON */ 428563d12f2SElaine Zhang CLK_UART_SEL_SHIFT = 12, 429563d12f2SElaine Zhang CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 430563d12f2SElaine Zhang CLK_UART_SEL_SRC = 0, 431563d12f2SElaine Zhang CLK_UART_SEL_FRAC, 432563d12f2SElaine Zhang CLK_UART_SEL_XIN24M, 433563d12f2SElaine Zhang CLK_UART_SRC_SEL_SHIFT = 8, 434563d12f2SElaine Zhang CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, 435563d12f2SElaine Zhang CLK_UART_SRC_SEL_GPLL = 0, 436563d12f2SElaine Zhang CLK_UART_SRC_SEL_CPLL, 437563d12f2SElaine Zhang CLK_UART_SRC_SEL_480M, 438563d12f2SElaine Zhang CLK_UART_SRC_DIV_SHIFT = 0, 439563d12f2SElaine Zhang CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT, 440563d12f2SElaine Zhang 441563d12f2SElaine Zhang /* CRU_CLK_SEL53_CON */ 442563d12f2SElaine Zhang CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 443563d12f2SElaine Zhang CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 444563d12f2SElaine Zhang CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 445563d12f2SElaine Zhang CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 446563d12f2SElaine Zhang 447417bebc4SElaine Zhang /* CRU_CLK_SEL71_CON */ 448417bebc4SElaine Zhang CLK_I2C_SEL_SHIFT = 8, 449417bebc4SElaine Zhang CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT, 450417bebc4SElaine Zhang CLK_I2C_SEL_200M = 0, 451417bebc4SElaine Zhang CLK_I2C_SEL_100M, 452417bebc4SElaine Zhang CLK_I2C_SEL_24M, 453417bebc4SElaine Zhang CLK_I2C_SEL_CPLL_100M, 454417bebc4SElaine Zhang 455417bebc4SElaine Zhang /* CRU_CLK_SEL72_CON */ 456417bebc4SElaine Zhang CLK_PWM3_SEL_SHIFT = 12, 457417bebc4SElaine Zhang CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, 458417bebc4SElaine Zhang CLK_PWM2_SEL_SHIFT = 10, 459417bebc4SElaine Zhang CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 460417bebc4SElaine Zhang CLK_PWM1_SEL_SHIFT = 8, 461417bebc4SElaine Zhang CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 462417bebc4SElaine Zhang CLK_PWM_SEL_100M = 0, 463417bebc4SElaine Zhang CLK_PWM_SEL_24M, 464417bebc4SElaine Zhang CLK_PWM_SEL_CPLL_100M, 465417bebc4SElaine Zhang CLK_SPI3_SEL_SHIFT = 6, 466417bebc4SElaine Zhang CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 467417bebc4SElaine Zhang CLK_SPI2_SEL_SHIFT = 4, 468417bebc4SElaine Zhang CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 469417bebc4SElaine Zhang CLK_SPI1_SEL_SHIFT = 2, 470417bebc4SElaine Zhang CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 471417bebc4SElaine Zhang CLK_SPI0_SEL_SHIFT = 0, 472417bebc4SElaine Zhang CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 473417bebc4SElaine Zhang CLK_SPI_SEL_200M = 0, 474417bebc4SElaine Zhang CLK_SPI_SEL_24M, 475417bebc4SElaine Zhang CLK_SPI_SEL_CPLL_100M, 476417bebc4SElaine Zhang 477417bebc4SElaine Zhang /* CRU_CLK_SEL73_CON */ 478417bebc4SElaine Zhang PCLK_TOP_SEL_SHIFT = 12, 479417bebc4SElaine Zhang PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, 480417bebc4SElaine Zhang PCLK_TOP_SEL_100M = 0, 481417bebc4SElaine Zhang PCLK_TOP_SEL_75M, 482417bebc4SElaine Zhang PCLK_TOP_SEL_50M, 483417bebc4SElaine Zhang PCLK_TOP_SEL_24M, 484417bebc4SElaine Zhang HCLK_TOP_SEL_SHIFT = 8, 485417bebc4SElaine Zhang HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, 486417bebc4SElaine Zhang HCLK_TOP_SEL_150M = 0, 487417bebc4SElaine Zhang HCLK_TOP_SEL_100M, 488417bebc4SElaine Zhang HCLK_TOP_SEL_75M, 489417bebc4SElaine Zhang HCLK_TOP_SEL_24M, 490417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_SHIFT = 4, 491417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT, 492417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_400M = 0, 493417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_300M, 494417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_200M, 495417bebc4SElaine Zhang ACLK_TOP_LOW_SEL_24M, 496417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_SHIFT = 0, 497417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT, 498417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_500M = 0, 499417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_400M, 500417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_300M, 501417bebc4SElaine Zhang ACLK_TOP_HIGH_SEL_24M, 502fdd74c32SElaine Zhang 503f6d27794Szhangqing /* CRU_CLK_SEL78_CON */ 504f6d27794Szhangqing CPLL_500M_DIV_SHIFT = 8, 505f6d27794Szhangqing CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT, 506f6d27794Szhangqing 507fdd74c32SElaine Zhang /* CRU_CLK_SEL79_CON */ 508f6d27794Szhangqing CPLL_250M_DIV_SHIFT = 8, 509f6d27794Szhangqing CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT, 510fdd74c32SElaine Zhang CPLL_333M_DIV_SHIFT = 0, 511fdd74c32SElaine Zhang CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT, 512f6d27794Szhangqing 513f6d27794Szhangqing /* CRU_CLK_SEL80_CON */ 514f6d27794Szhangqing CPLL_62P5M_DIV_SHIFT = 8, 515f6d27794Szhangqing CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT, 516f6d27794Szhangqing CPLL_125M_DIV_SHIFT = 0, 517f6d27794Szhangqing CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT, 518f6d27794Szhangqing 519f6d27794Szhangqing /* CRU_CLK_SEL81_CON */ 520f6d27794Szhangqing CPLL_25M_DIV_SHIFT = 8, 521*0de0139eSJonas Karlman CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT, 522f6d27794Szhangqing CPLL_50M_DIV_SHIFT = 0, 523f6d27794Szhangqing CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, 524f6d27794Szhangqing 525f6d27794Szhangqing /* CRU_CLK_SEL82_CON */ 526f6d27794Szhangqing CPLL_100M_DIV_SHIFT = 0, 527f6d27794Szhangqing CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT, 52826663c2dSElaine Zhang 52926663c2dSElaine Zhang /* GRF_SOC_CON2 */ 53026663c2dSElaine Zhang I2S3_MCLKOUT_SEL_SHIFT = 15, 53126663c2dSElaine Zhang I2S3_MCLKOUT_SEL_MASK = 0x1 << I2S3_MCLKOUT_SEL_SHIFT, 53226663c2dSElaine Zhang I2S3_MCLKOUT_SEL_RX = 0, 53326663c2dSElaine Zhang I2S3_MCLKOUT_SEL_TX, 53426663c2dSElaine Zhang I2S3_MCLK_IOE_SEL_SHIFT = 3, 53526663c2dSElaine Zhang I2S3_MCLK_IOE_SEL_MASK = 0x1 << I2S3_MCLK_IOE_SEL_SHIFT, 53626663c2dSElaine Zhang I2S3_MCLK_IOE_SEL_CLKIN = 0, 53726663c2dSElaine Zhang I2S3_MCLK_IOE_SEL_CLKOUT, 53826663c2dSElaine Zhang 539417bebc4SElaine Zhang }; 540417bebc4SElaine Zhang #endif 541