| #
0de0139e |
| 04-Aug-2023 |
Jonas Karlman <jonas@kwiboo.se> |
UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Change-Id: Icc9fda366d0428b2b425a74c7ea2c5a5c1489d2f
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
02155da2 |
| 26-Sep-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: modify the PPLL init freq to 200M
Keep the frequency consistent with the kernel.
Change-Id: I129f2b428d51e344338f92e1d492082afaa0b029
Signed-off-by: Elaine Zhang <zhangqing@r
clk: rockchip: rk3568: modify the PPLL init freq to 200M
Keep the frequency consistent with the kernel.
Change-Id: I129f2b428d51e344338f92e1d492082afaa0b029
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
26663c2d |
| 23-Jul-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: add i2s3 clk
Change-Id: If20fe16260d2b584d4216d1dbabffcb25478fb1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
563d12f2 |
| 09-Apr-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: add uart clk
Change-Id: I92a097e216e9cbb254c5bae5a25bc52f0c53cd38
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
3a5404af |
| 24-Dec-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk3568: set the APLL_HZ to 816MHz
Set the APLL_HZ to lower frequency in spl when the pmic is not
available.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id540ff174e
clk: rockchip: rk3568: set the APLL_HZ to 816MHz
Set the APLL_HZ to lower frequency in spl when the pmic is not
available.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id540ff174ef93c3d9ea22bb37dc26ca7b587a5b7
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| #
0a04fb50 |
| 09-Dec-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support rkvdec clk setting
Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
f6d27794 |
| 01-Dec-2020 |
zhangqing <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support more clk setting
support cpll_xxx settings.
Change-Id: I2735f6abe0fb02828b7ace76b58a60757199cab8
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
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| #
fdd74c32 |
| 12-Nov-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support ebc clk setting/getting rate
Change-Id: Iecac8e56b2b5615b54c8969767053b6282fe6fb8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
417bebc4 |
| 14-Sep-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: Add clock driver
Add basic clock for rk3568 which including cpu, bus, mmc,
i2c, pwm, gmac ...clocks init.
Change-Id: I4119f10897d06befa4a39198b3724dc515d416e3
Signed-off-by:
clk: rockchip: rk3568: Add clock driver
Add basic clock for rk3568 which including cpu, bus, mmc,
i2c, pwm, gmac ...clocks init.
Change-Id: I4119f10897d06befa4a39198b3724dc515d416e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|