clk: rockchip: rk3576: fix cci\big\litcore init

If core select pvtpll in ddr,not need init in spl.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I653ad0836eb6c05591c2105705c2ee3

clk: rockchip: rk3576: fix cci\big\litcore init

If core select pvtpll in ddr,not need init in spl.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I653ad0836eb6c05591c2105705c2ee3038feeefb

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clk: rockchip: rk3576: add ref_clkout_pll

Change-Id: Id120fafec101568fab94929934667e7bef8c1a09
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3576: add decom clk setting

Change-Id: I3e0e288938d672b86d80dc91e1b782691695c5fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3576: Change cpu rm from 4 to 3 for performance

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3e6d153a35e2615b612d08525c09d117979d9cd1

clk: rockchip: Add rk3576 clock driver

Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.

- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk set

clk: rockchip: Add rk3576 clock driver

Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.

- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk setting rule
- relase bigcore biu\cru\grf in spl
- add ufs ref clk setting
- Remove PCIe relevant
- fix hdmi phy name
- add dsihost and ebc clk setting
- add dsihot getting
- fix dclk getting freq error

Change-Id: I2658bf3f77f6386a6f124f624a0658d61cf90fc2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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