| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3188.h | 14 #define CPLL_HZ (384 * 1000000) macro
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| H A D | cru_rk3066.h | 14 #define CPLL_HZ (384 * 1000000) macro
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| H A D | cru_rk3399.h | 83 #define CPLL_HZ (384*MHz) macro
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| H A D | cru_rk3128.h | 17 #define CPLL_HZ (400 * MHz) macro
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| H A D | cru_rk322x.h | 15 #define CPLL_HZ (500 * MHz) macro
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| H A D | cru_rk3328.h | 76 #define CPLL_HZ (1200 * MHz) macro
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| H A D | cru_rk3288.h | 16 #define CPLL_HZ (384 * 1000000) macro
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| H A D | cru_rv1106.h | 22 #define CPLL_HZ (1000 * MHz) macro
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| H A D | cru_rv1126.h | 22 #define CPLL_HZ (500 * MHz) macro
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| H A D | cru_rk3528.h | 17 #define CPLL_HZ (996 * MHz) macro
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| H A D | cru_rk3562.h | 19 #define CPLL_HZ (1000 * MHz) macro
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| H A D | cru_rv1126b.h | 19 #define CPLL_HZ (1000 * MHz) macro
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| H A D | cru_rk3588.h | 17 #define CPLL_HZ (1500 * MHz) macro
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| H A D | cru_rk3568.h | 16 #define CPLL_HZ (1000 * MHz) macro
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| H A D | cru_rk3576.h | 17 #define CPLL_HZ (1000 * MHz) macro
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 59 #define CPLL_HZ (400 * 1000 * 1000) macro
117 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
346 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
469 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
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| H A D | clk_rv1106.c | 1280 if (priv->cpll_hz != CPLL_HZ) { in rv1106_clk_init()
1282 CPLL, CPLL_HZ); in rv1106_clk_init()
1284 priv->cpll_hz = CPLL_HZ; in rv1106_clk_init()
1312 priv->cpll_hz = CPLL_HZ; in rv1106_clk_probe()
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| H A D | clk_rk3328.c | 291 pll_rate = CPLL_HZ; in rk3328_gmac2phy_src_set_clk()
1305 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
1306 priv->cpll_hz = CPLL_HZ; in rkclk_init()
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| H A D | clk_rk322x.c | 997 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
998 priv->cpll_hz = CPLL_HZ; in rkclk_init()
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| H A D | clk_rv1126.c | 675 if (CPLL_HZ % rate) { in rv1126_pdbus_set_clk()
2146 if (priv->cpll_hz != CPLL_HZ) { in rv1126_clk_init()
2148 CPLL, CPLL_HZ); in rv1126_clk_init()
2150 priv->cpll_hz = CPLL_HZ; in rv1126_clk_init()
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| H A D | clk_rk3528.c | 1942 if (priv->cpll_hz != CPLL_HZ) { in rk3528_clk_init()
1944 CPLL, CPLL_HZ); in rk3528_clk_init()
1946 priv->cpll_hz = CPLL_HZ; in rk3528_clk_init()
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| H A D | clk_rv1126b.c | 1846 if (priv->cpll_hz != CPLL_HZ) { in rv1126b_clk_init()
1848 CPLL, CPLL_HZ); in rv1126b_clk_init()
1850 priv->cpll_hz = CPLL_HZ; in rv1126b_clk_init()
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| H A D | clk_rk3066.c | 104 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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| H A D | clk_rk3562.c | 1823 if (priv->cpll_hz != CPLL_HZ) { in rk3562_clk_init()
1825 CPLL, CPLL_HZ); in rk3562_clk_init()
1827 priv->cpll_hz = CPLL_HZ; in rk3562_clk_init()
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| H A D | clk_rk3188.c | 102 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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