clk: rockchip: rk3399: print arm enter and init rate

Change-Id: Ib5e3e0f9a3e1a5b535ec852e7c58966dc0db77cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: support clk dump

add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zh

clk: rockchip: rk3399: support clk dump

add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-

clk: rockchip: rk3399: Improve the aclk_perilp0 frequency

Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@ro

clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cr

clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0_DIV>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&vopl {
status = "okay";
assigned-clocks = <&cru DCLK_VOP1_DIV>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

Change-Id: I07ab4e2837cf7fc0860e8b4d14adb8936f5cb27a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

clk: rockchip: rk3399: refactor configure cpu clock function

some board request enable cpu big core clock in uboot,
refactor rk3399_configure_cpu() function, so that the little
core and big core can

clk: rockchip: rk3399: refactor configure cpu clock function

some board request enable cpu big core clock in uboot,
refactor rk3399_configure_cpu() function, so that the little
core and big core can reuse this function to set clock.

Change-Id: I0390d22179faf91307b22348f6f9329a58f00143
Signed-off-by: Lin Huang <hl@rock-chips.com>

show more ...

clk: rockchip: rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ

This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock

clk: rockchip: rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ

This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock to always run at
the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our
previous tests and validation with this bug, we should probably increase
the value of the constant (that had not actually been used) to the value
that we had been incorrectly using instead.

Change-Id: I8e1725f71ea0dbacd01929b8e8a80b91dc4f17cc
Signed-off-by: Lin Huang <hl@rock-chips.com>

show more ...

rockchip: clk: rk3399: remove unused fields from priv-structures

This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from

rockchip: clk: rk3399: remove unused fields from priv-structures

This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it bo

Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).

show more ...

rockchip: clk: rk3399: update driver for spl

Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: S

rockchip: clk: rk3399: update driver for spl

Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning:
Signed-off-by: Simon Glass <sjg@chromium.org>

show more ...

Merge git://git.denx.de/u-boot-rockchip

rockchip: rk3399: Move rockchip_get_cru() out of the driver

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be m

rockchip: rk3399: Move rockchip_get_cru() out of the driver

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

show more ...

Merge git://git.denx.de/u-boot-rockchip

rockchip: rk3399: update PPLL and pmu_pclk frequency

Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think

rockchip: rk3399: update PPLL and pmu_pclk frequency

Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

show more ...

Merge git://git.denx.de/u-boot-rockchip

rk3399: add basic soc driver

This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver

Signed-off-by: Kever Yang <kever.yang@rock-ch

rk3399: add basic soc driver

This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

show more ...