xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/cru_rk3288.h (revision 5561190119af2afc614623105648ea752a441418)
199c15650SSimon Glass /*
299c15650SSimon Glass  * (C) Copyright 2015 Google, Inc
399c15650SSimon Glass  *
499c15650SSimon Glass  * (C) Copyright 2008-2014 Rockchip Electronics
599c15650SSimon Glass  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
699c15650SSimon Glass  *
799c15650SSimon Glass  * SPDX-License-Identifier:     GPL-2.0+
899c15650SSimon Glass  */
999c15650SSimon Glass #ifndef _ASM_ARCH_CRU_RK3288_H
1099c15650SSimon Glass #define _ASM_ARCH_CRU_RK3288_H
1199c15650SSimon Glass 
1299c15650SSimon Glass #define OSC_HZ		(24 * 1000 * 1000)
1399c15650SSimon Glass 
1499c15650SSimon Glass #define APLL_HZ		(1800 * 1000000)
1599c15650SSimon Glass #define GPLL_HZ		(594 * 1000000)
1699c15650SSimon Glass #define CPLL_HZ		(384 * 1000000)
1799c15650SSimon Glass #define NPLL_HZ		(384 * 1000000)
1899c15650SSimon Glass 
1999c15650SSimon Glass /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
2099c15650SSimon Glass #define PD_BUS_ACLK_HZ	297000000
2199c15650SSimon Glass #define PD_BUS_HCLK_HZ	148500000
2299c15650SSimon Glass #define PD_BUS_PCLK_HZ	74250000
2399c15650SSimon Glass 
2499c15650SSimon Glass #define PERI_ACLK_HZ	148500000
2599c15650SSimon Glass #define PERI_HCLK_HZ	148500000
2699c15650SSimon Glass #define PERI_PCLK_HZ	74250000
2799c15650SSimon Glass 
28*55611901SElaine Zhang #define HCLK_VIO_HZ	100000000
29*55611901SElaine Zhang 
305564ed5dSSimon Glass /* Private data for the clock driver - used by rockchip_get_cru() */
315564ed5dSSimon Glass struct rk3288_clk_priv {
325564ed5dSSimon Glass 	struct rk3288_grf *grf;
335564ed5dSSimon Glass 	struct rk3288_cru *cru;
345564ed5dSSimon Glass 	ulong rate;
35ec0307efSElaine Zhang 	ulong armclk_hz;
36ec0307efSElaine Zhang 	ulong armclk_enter_hz;
37ec0307efSElaine Zhang 	ulong armclk_init_hz;
38ec0307efSElaine Zhang 	bool sync_kernel;
39ec0307efSElaine Zhang 	bool set_armclk_rate;
405564ed5dSSimon Glass };
415564ed5dSSimon Glass 
4299c15650SSimon Glass struct rk3288_cru {
4399c15650SSimon Glass 	struct rk3288_pll {
4499c15650SSimon Glass 		u32 con0;
4599c15650SSimon Glass 		u32 con1;
4699c15650SSimon Glass 		u32 con2;
4799c15650SSimon Glass 		u32 con3;
4899c15650SSimon Glass 	} pll[5];
4999c15650SSimon Glass 	u32 cru_mode_con;
5099c15650SSimon Glass 	u32 reserved0[3];
5199c15650SSimon Glass 	u32 cru_clksel_con[43];
5299c15650SSimon Glass 	u32 reserved1[21];
5399c15650SSimon Glass 	u32 cru_clkgate_con[19];
5499c15650SSimon Glass 	u32 reserved2;
5599c15650SSimon Glass 	u32 cru_glb_srst_fst_value;
5699c15650SSimon Glass 	u32 cru_glb_srst_snd_value;
5799c15650SSimon Glass 	u32 cru_softrst_con[12];
5899c15650SSimon Glass 	u32 cru_misc_con;
5999c15650SSimon Glass 	u32 cru_glb_cnt_th;
6099c15650SSimon Glass 	u32 cru_glb_rst_con;
6199c15650SSimon Glass 	u32 reserved3;
6299c15650SSimon Glass 	u32 cru_glb_rst_st;
6399c15650SSimon Glass 	u32 reserved4;
6499c15650SSimon Glass 	u32 cru_sdmmc_con[2];
6599c15650SSimon Glass 	u32 cru_sdio0_con[2];
6699c15650SSimon Glass 	u32 cru_sdio1_con[2];
6799c15650SSimon Glass 	u32 cru_emmc_con[2];
6899c15650SSimon Glass };
6999c15650SSimon Glass check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
7099c15650SSimon Glass 
71ec0307efSElaine Zhang struct rk3288_clk_info {
72ec0307efSElaine Zhang 	unsigned long id;
73ec0307efSElaine Zhang 	char *name;
74ec0307efSElaine Zhang 	bool is_cru;
75ec0307efSElaine Zhang };
76ec0307efSElaine Zhang 
7799c15650SSimon Glass /* CRU_CLKSEL11_CON */
7899c15650SSimon Glass enum {
7999c15650SSimon Glass 	HSICPHY_DIV_SHIFT	= 8,
80b223c1aeSSimon Glass 	HSICPHY_DIV_MASK	= 0x3f << HSICPHY_DIV_SHIFT,
8199c15650SSimon Glass 
8299c15650SSimon Glass 	MMC0_PLL_SHIFT		= 6,
83b223c1aeSSimon Glass 	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
8499c15650SSimon Glass 	MMC0_PLL_SELECT_CODEC	= 0,
8599c15650SSimon Glass 	MMC0_PLL_SELECT_GENERAL,
8699c15650SSimon Glass 	MMC0_PLL_SELECT_24MHZ,
8799c15650SSimon Glass 
8899c15650SSimon Glass 	MMC0_DIV_SHIFT		= 0,
89b223c1aeSSimon Glass 	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
9099c15650SSimon Glass };
9199c15650SSimon Glass 
9299c15650SSimon Glass /* CRU_CLKSEL12_CON */
9399c15650SSimon Glass enum {
9499c15650SSimon Glass 	EMMC_PLL_SHIFT		= 0xe,
95b223c1aeSSimon Glass 	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
9699c15650SSimon Glass 	EMMC_PLL_SELECT_CODEC	= 0,
9799c15650SSimon Glass 	EMMC_PLL_SELECT_GENERAL,
9899c15650SSimon Glass 	EMMC_PLL_SELECT_24MHZ,
9999c15650SSimon Glass 
10099c15650SSimon Glass 	EMMC_DIV_SHIFT		= 8,
101bf82e200SKever Yang 	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
10299c15650SSimon Glass 
10399c15650SSimon Glass 	SDIO0_PLL_SHIFT		= 6,
104b223c1aeSSimon Glass 	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,
10599c15650SSimon Glass 	SDIO0_PLL_SELECT_CODEC	= 0,
10699c15650SSimon Glass 	SDIO0_PLL_SELECT_GENERAL,
10799c15650SSimon Glass 	SDIO0_PLL_SELECT_24MHZ,
10899c15650SSimon Glass 
10999c15650SSimon Glass 	SDIO0_DIV_SHIFT		= 0,
110b223c1aeSSimon Glass 	SDIO0_DIV_MASK		= 0x3f << SDIO0_DIV_SHIFT,
11199c15650SSimon Glass };
11299c15650SSimon Glass 
1130aefc0b0SSjoerd Simons /* CRU_CLKSEL21_CON */
1140aefc0b0SSjoerd Simons enum {
1150aefc0b0SSjoerd Simons 	MAC_DIV_CON_SHIFT	= 0xf,
116b223c1aeSSimon Glass 	MAC_DIV_CON_MASK	= 0x1f << MAC_DIV_CON_SHIFT,
1170aefc0b0SSjoerd Simons 
1180aefc0b0SSjoerd Simons 	RMII_EXTCLK_SHIFT	= 4,
119b223c1aeSSimon Glass 	RMII_EXTCLK_MASK	= 1 << RMII_EXTCLK_SHIFT,
1200aefc0b0SSjoerd Simons 	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
1210aefc0b0SSjoerd Simons 	RMII_EXTCLK_SELECT_EXT_CLK = 1,
1220aefc0b0SSjoerd Simons 
1230aefc0b0SSjoerd Simons 	EMAC_PLL_SHIFT		= 0,
124b223c1aeSSimon Glass 	EMAC_PLL_MASK		= 0x3 << EMAC_PLL_SHIFT,
1250aefc0b0SSjoerd Simons 	EMAC_PLL_SELECT_NEW	= 0x0,
1260aefc0b0SSjoerd Simons 	EMAC_PLL_SELECT_CODEC	= 0x1,
1270aefc0b0SSjoerd Simons 	EMAC_PLL_SELECT_GENERAL	= 0x2,
1280aefc0b0SSjoerd Simons };
1290aefc0b0SSjoerd Simons 
13099c15650SSimon Glass /* CRU_CLKSEL25_CON */
13199c15650SSimon Glass enum {
13299c15650SSimon Glass 	SPI1_PLL_SHIFT		= 0xf,
133b223c1aeSSimon Glass 	SPI1_PLL_MASK		= 1 << SPI1_PLL_SHIFT,
13499c15650SSimon Glass 	SPI1_PLL_SELECT_CODEC	= 0,
13599c15650SSimon Glass 	SPI1_PLL_SELECT_GENERAL,
13699c15650SSimon Glass 
13799c15650SSimon Glass 	SPI1_DIV_SHIFT		= 8,
138b223c1aeSSimon Glass 	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
13999c15650SSimon Glass 
14099c15650SSimon Glass 	SPI0_PLL_SHIFT		= 7,
141b223c1aeSSimon Glass 	SPI0_PLL_MASK		= 1 << SPI0_PLL_SHIFT,
14299c15650SSimon Glass 	SPI0_PLL_SELECT_CODEC	= 0,
14399c15650SSimon Glass 	SPI0_PLL_SELECT_GENERAL,
14499c15650SSimon Glass 
14599c15650SSimon Glass 	SPI0_DIV_SHIFT		= 0,
146b223c1aeSSimon Glass 	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
14799c15650SSimon Glass };
14899c15650SSimon Glass 
149b328c914SElaine Zhang /* CRU_CLKSEL27_CON */
150b328c914SElaine Zhang enum {
151b328c914SElaine Zhang 	DCLK_VOP0_DIV_SHIFT	= 8,
152b328c914SElaine Zhang 	DCLK_VOP0_DIV_MASK	= 0xff << DCLK_VOP0_DIV_SHIFT,
153b328c914SElaine Zhang 	DCLK_VOP0_PLL_SHIFT	= 0,
154b328c914SElaine Zhang 	DCLK_VOP0_PLL_MASK	= 3 << DCLK_VOP0_PLL_SHIFT,
155b328c914SElaine Zhang 	DCLK_VOP0_SELECT_CPLL	= 0,
156b328c914SElaine Zhang 	DCLK_VOP0_SELECT_GPLL	= 1,
157b328c914SElaine Zhang 	DCLK_VOP0_SELECT_NPLL	= 2,
158b328c914SElaine Zhang };
159b328c914SElaine Zhang 
160*55611901SElaine Zhang /* CRU_CLKSEL28_CON */
161*55611901SElaine Zhang enum {
162*55611901SElaine Zhang 	HCLK_VIO_DIV_SHIFT	= 8,
163*55611901SElaine Zhang 	HCLK_VIO_DIV_MASK	= 0x1f << HCLK_VIO_DIV_SHIFT,
164*55611901SElaine Zhang };
165*55611901SElaine Zhang 
166b328c914SElaine Zhang /* CRU_CLKSEL29_CON */
167b328c914SElaine Zhang enum {
168b328c914SElaine Zhang 	DCLK_VOP1_DIV_SHIFT	= 8,
169b328c914SElaine Zhang 	DCLK_VOP1_DIV_MASK	= 0xff << DCLK_VOP1_DIV_SHIFT,
170b328c914SElaine Zhang 	DCLK_VOP1_PLL_SHIFT	= 6,
171b328c914SElaine Zhang 	DCLK_VOP1_PLL_MASK	= 3 << DCLK_VOP1_PLL_SHIFT,
172b328c914SElaine Zhang 	DCLK_VOP1_SELECT_CPLL	= 0,
173b328c914SElaine Zhang 	DCLK_VOP1_SELECT_GPLL	= 1,
174b328c914SElaine Zhang 	DCLK_VOP1_SELECT_NPLL	= 2,
175b328c914SElaine Zhang };
176b328c914SElaine Zhang 
1775a616fcfSElaine Zhang /* CRU_CLKSEL31_CON */
1785a616fcfSElaine Zhang enum {
179*55611901SElaine Zhang 	ACLK_VIO_SELECT_CPLL	= 0,
180*55611901SElaine Zhang 	ACLK_VIO_SELECT_GPLL	= 1,
181*55611901SElaine Zhang 	ACLK_VIO_SELECT_USB480	= 2,
182*55611901SElaine Zhang 	ACLK_VIO1_PLL_SHIFT	= 14,
183*55611901SElaine Zhang 	ACLK_VIO1_PLL_MASK	= 3 << ACLK_VIO1_PLL_SHIFT,
184*55611901SElaine Zhang 	ACLK_VIO1_DIV_SHIFT	= 8,
185*55611901SElaine Zhang 	ACLK_VIO1_DIV_MASK	= 0x1f << ACLK_VIO1_DIV_SHIFT,
186*55611901SElaine Zhang 	ACLK_VIO0_PLL_SHIFT	= 6,
187*55611901SElaine Zhang 	ACLK_VIO0_PLL_MASK	= 3 << ACLK_VIO0_PLL_SHIFT,
188*55611901SElaine Zhang 	ACLK_VIO0_DIV_SHIFT	= 0,
189*55611901SElaine Zhang 	ACLK_VIO0_DIV_MASK	= 0x1f << ACLK_VIO0_DIV_SHIFT,
1905a616fcfSElaine Zhang };
1915a616fcfSElaine Zhang 
192dae594f2SSimon Glass /* CRU_CLKSEL37_CON */
193dae594f2SSimon Glass enum {
194dae594f2SSimon Glass 	PCLK_CORE_DBG_DIV_SHIFT	= 9,
195b223c1aeSSimon Glass 	PCLK_CORE_DBG_DIV_MASK	= 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
196dae594f2SSimon Glass 
197dae594f2SSimon Glass 	ATCLK_CORE_DIV_CON_SHIFT = 4,
198b223c1aeSSimon Glass 	ATCLK_CORE_DIV_CON_MASK	= 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
199dae594f2SSimon Glass 
200dae594f2SSimon Glass 	CLK_L2RAM_DIV_SHIFT	= 0,
201b223c1aeSSimon Glass 	CLK_L2RAM_DIV_MASK	= 7 << CLK_L2RAM_DIV_SHIFT,
202dae594f2SSimon Glass };
203dae594f2SSimon Glass 
20499c15650SSimon Glass /* CRU_CLKSEL39_CON */
20599c15650SSimon Glass enum {
20699c15650SSimon Glass 	ACLK_HEVC_PLL_SHIFT	= 0xe,
207b223c1aeSSimon Glass 	ACLK_HEVC_PLL_MASK	= 3 << ACLK_HEVC_PLL_SHIFT,
20899c15650SSimon Glass 	ACLK_HEVC_PLL_SELECT_CODEC = 0,
20999c15650SSimon Glass 	ACLK_HEVC_PLL_SELECT_GENERAL,
21099c15650SSimon Glass 	ACLK_HEVC_PLL_SELECT_NEW,
21199c15650SSimon Glass 
21299c15650SSimon Glass 	ACLK_HEVC_DIV_SHIFT	= 8,
213b223c1aeSSimon Glass 	ACLK_HEVC_DIV_MASK	= 0x1f << ACLK_HEVC_DIV_SHIFT,
21499c15650SSimon Glass 
21599c15650SSimon Glass 	SPI2_PLL_SHIFT		= 7,
216b223c1aeSSimon Glass 	SPI2_PLL_MASK		= 1 << SPI2_PLL_SHIFT,
21799c15650SSimon Glass 	SPI2_PLL_SELECT_CODEC	= 0,
21899c15650SSimon Glass 	SPI2_PLL_SELECT_GENERAL,
21999c15650SSimon Glass 
22099c15650SSimon Glass 	SPI2_DIV_SHIFT		= 0,
221b223c1aeSSimon Glass 	SPI2_DIV_MASK		= 0x7f << SPI2_DIV_SHIFT,
22299c15650SSimon Glass };
22399c15650SSimon Glass 
22499c15650SSimon Glass /* CRU_MODE_CON */
22599c15650SSimon Glass enum {
226b223c1aeSSimon Glass 	CRU_MODE_MASK		= 3,
227b223c1aeSSimon Glass 
228009741fbSSimon Glass 	NPLL_MODE_SHIFT		= 0xe,
229b223c1aeSSimon Glass 	NPLL_MODE_MASK		= CRU_MODE_MASK << NPLL_MODE_SHIFT,
230009741fbSSimon Glass 	NPLL_MODE_SLOW		= 0,
231009741fbSSimon Glass 	NPLL_MODE_NORMAL,
232009741fbSSimon Glass 	NPLL_MODE_DEEP,
23399c15650SSimon Glass 
234009741fbSSimon Glass 	GPLL_MODE_SHIFT		= 0xc,
235b223c1aeSSimon Glass 	GPLL_MODE_MASK		= CRU_MODE_MASK << GPLL_MODE_SHIFT,
236009741fbSSimon Glass 	GPLL_MODE_SLOW		= 0,
237009741fbSSimon Glass 	GPLL_MODE_NORMAL,
238009741fbSSimon Glass 	GPLL_MODE_DEEP,
23999c15650SSimon Glass 
240009741fbSSimon Glass 	CPLL_MODE_SHIFT		= 8,
241b223c1aeSSimon Glass 	CPLL_MODE_MASK		= CRU_MODE_MASK << CPLL_MODE_SHIFT,
242009741fbSSimon Glass 	CPLL_MODE_SLOW		= 0,
243009741fbSSimon Glass 	CPLL_MODE_NORMAL,
244009741fbSSimon Glass 	CPLL_MODE_DEEP,
24599c15650SSimon Glass 
246009741fbSSimon Glass 	DPLL_MODE_SHIFT		= 4,
247b223c1aeSSimon Glass 	DPLL_MODE_MASK		= CRU_MODE_MASK << DPLL_MODE_SHIFT,
248009741fbSSimon Glass 	DPLL_MODE_SLOW		= 0,
249009741fbSSimon Glass 	DPLL_MODE_NORMAL,
250009741fbSSimon Glass 	DPLL_MODE_DEEP,
25199c15650SSimon Glass 
252009741fbSSimon Glass 	APLL_MODE_SHIFT		= 0,
253b223c1aeSSimon Glass 	APLL_MODE_MASK		= CRU_MODE_MASK << APLL_MODE_SHIFT,
254009741fbSSimon Glass 	APLL_MODE_SLOW		= 0,
255009741fbSSimon Glass 	APLL_MODE_NORMAL,
256009741fbSSimon Glass 	APLL_MODE_DEEP,
25799c15650SSimon Glass };
25899c15650SSimon Glass 
25999c15650SSimon Glass /* CRU_APLL_CON0 */
26099c15650SSimon Glass enum {
26199c15650SSimon Glass 	CLKR_SHIFT		= 8,
262b223c1aeSSimon Glass 	CLKR_MASK		= 0x3f << CLKR_SHIFT,
26399c15650SSimon Glass 
26499c15650SSimon Glass 	CLKOD_SHIFT		= 0,
265b223c1aeSSimon Glass 	CLKOD_MASK		= 0xf << CLKOD_SHIFT,
26699c15650SSimon Glass };
26799c15650SSimon Glass 
26899c15650SSimon Glass /* CRU_APLL_CON1 */
26999c15650SSimon Glass enum {
27099c15650SSimon Glass 	LOCK_SHIFT		= 0x1f,
271b223c1aeSSimon Glass 	LOCK_MASK		= 1 << LOCK_SHIFT,
27299c15650SSimon Glass 	LOCK_UNLOCK		= 0,
27399c15650SSimon Glass 	LOCK_LOCK,
27499c15650SSimon Glass 
27599c15650SSimon Glass 	CLKF_SHIFT		= 0,
276b223c1aeSSimon Glass 	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
27799c15650SSimon Glass };
27899c15650SSimon Glass 
27940d4f79bSWadim Egorov /* CRU_GLB_RST_ST */
28040d4f79bSWadim Egorov enum {
28140d4f79bSWadim Egorov 	GLB_POR_RST,
28240d4f79bSWadim Egorov 	FST_GLB_RST_ST		= BIT(0),
28340d4f79bSWadim Egorov 	SND_GLB_RST_ST		= BIT(1),
28440d4f79bSWadim Egorov 	FST_GLB_TSADC_RST_ST	= BIT(2),
28540d4f79bSWadim Egorov 	SND_GLB_TSADC_RST_ST	= BIT(3),
28640d4f79bSWadim Egorov 	FST_GLB_WDT_RST_ST	= BIT(4),
28740d4f79bSWadim Egorov 	SND_GLB_WDT_RST_ST	= BIT(5),
28840d4f79bSWadim Egorov 	GLB_RST_ST_MASK		= GENMASK(5, 0),
28940d4f79bSWadim Egorov };
29040d4f79bSWadim Egorov 
29199c15650SSimon Glass #endif
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