| #
0265e00c |
| 24-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add rk3576 clock driver
Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.
- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk set
clk: rockchip: Add rk3576 clock driver
Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.
- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk setting rule
- relase bigcore biu\cru\grf in spl
- add ufs ref clk setting
- Remove PCIe relevant
- fix hdmi phy name
- add dsihost and ebc clk setting
- add dsihot getting
- fix dclk getting freq error
Change-Id: I2658bf3f77f6386a6f124f624a0658d61cf90fc2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
show more ...
|
| #
6f22b15e |
| 17-Jun-2022 |
Jianqun Xu <jay.xu@rock-chips.com> |
rockchip: rk3588: fix aclk_vop_root_sel to 3bit width
Reference to trm the aclk_vop_root_sel has 3bit width.
Change-Id: I2f87e427446f59d408dcf89ed175ddb95ae0a8fb
Signed-off-by: Jianqun Xu <jay.xu@r
rockchip: rk3588: fix aclk_vop_root_sel to 3bit width
Reference to trm the aclk_vop_root_sel has 3bit width.
Change-Id: I2f87e427446f59d408dcf89ed175ddb95ae0a8fb
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
show more ...
|
| #
056cae5c |
| 13-Apr-2022 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3588: change cpul clock source to pvtpll
Change-Id: I4ab6d15c05b4cb805b60125cb5bb7e7d2e65d6e5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
| #
3a7297c2 |
| 21-Apr-2022 |
Kever Yang <kever.yang@rock-chips.com> |
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442
show more ...
|
| #
b6d6b016 |
| 24-Feb-2022 |
Zhang Yubing <yubing.zhang@rock-chips.com> |
clk: rockchip: rk3588: support setting dp aux channel clk
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I65954d0805ce51c042dd5ca469781fb55ab1bccc
|
| #
da48e024 |
| 22-Jan-2022 |
Algea Cao <algea.cao@rock-chips.com> |
clk: rockchip: rk3588: Support hdmiphy pll
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4fa787ed2b6057579985ab8469adef888eee1ee7
|
| #
6fe01683 |
| 24-Dec-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: add clk for clk_pmu1pwm
Change-Id: I40d2f22bf5ed6c586cf087beccbbf9e7e05abde6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
6ee1fad0 |
| 20-Nov-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk3588: modify LPP_HZ from 816M to 1200M
Change-Id: Ief08613007e8506cc1ffa4d25f4121f5c59a5cf5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
921abd27 |
| 19-Nov-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: add clk_pciephy
Change-Id: I29075c82c684f02e33caa1b70bdd4e633ee15fcb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
|
| #
d2b507bb |
| 11-Nov-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: add clk for dclk_decom
Change-Id: Iedeb11e0367d89aaa0d77338cd36c30e34df6f71
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
28d0997c |
| 19-May-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Add clock driver
Add basic clock for rk3588 which including top, peri, mmc,
i2c, pwm, gmac ...clocks init.
Change-Id: I0fb1695db483fc676c4ebc956aec66c143cc73e5
Signed-off-by:
clk: rockchip: rk3588: Add clock driver
Add basic clock for rk3588 which including top, peri, mmc,
i2c, pwm, gmac ...clocks init.
Change-Id: I0fb1695db483fc676c4ebc956aec66c143cc73e5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|