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Searched refs:SCLK_SPI2 (Results 1 – 25 of 33) sorted by relevance

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/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dexynos7-clk.h111 #define SCLK_SPI2 19 macro
H A Drk3288-cru.h22 #define SCLK_SPI2 67 macro
H A Drk3308-cru.h33 #define SCLK_SPI2 29 macro
H A Drk3368-cru.h23 #define SCLK_SPI2 67 macro
H A Drk1808-cru.h76 #define SCLK_SPI2 75 macro
H A Drk3399-cru.h33 #define SCLK_SPI2 73 macro
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dexynos7420-clk.h114 #define SCLK_SPI2 19 macro
H A Drk3308-cru.h42 #define SCLK_SPI2 29 macro
H A Drk3368-cru.h32 #define SCLK_SPI2 67 macro
H A Drk3288-cru.h20 #define SCLK_SPI2 67 macro
H A Drk1808-cru.h76 #define SCLK_SPI2 75 macro
H A Drk3399-cru.h32 #define SCLK_SPI2 73 macro
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-vop-clk-set.dtsi86 <&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3288.c816 case SCLK_SPI2: in rockchip_spi_get_clk()
850 case SCLK_SPI2: in rockchip_spi_set_clk()
1100 case SCLK_SPI2: in rk3288_clk_get_rate()
1179 case SCLK_SPI2: in rk3288_clk_set_rate()
H A Dclk_rk1808.c423 case SCLK_SPI2: in rk1808_spi_get_clk()
457 case SCLK_SPI2: in rk1808_spi_set_clk()
960 case SCLK_SPI2: in rk1808_clk_get_rate()
1064 case SCLK_SPI2: in rk1808_clk_set_rate()
H A Dclk_rk3368.c520 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_spi_get_clk()
545 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_spi_set_clk()
949 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_clk_get_rate()
1026 case SCLK_SPI0 ... SCLK_SPI2: in rk3368_clk_set_rate()
H A Dclk_rk3308.c449 case SCLK_SPI2: in rk3308_spi_get_clk()
479 case SCLK_SPI2: in rk3308_spi_set_clk()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos7.c788 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3368.c560 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
H A Dclk-rk3288.c535 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
H A Dclk-rk3308.c413 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
H A Dclk-rk1808.c930 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0,
H A Dclk-rk3399.c1425 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3308.dtsi259 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
H A Drk3368.dtsi322 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;

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