1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_EXYNOS7_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPC */ 11*4882a593Smuzhiyun #define DOUT_ACLK_PERIS 1 12*4882a593Smuzhiyun #define DOUT_SCLK_BUS0_PLL 2 13*4882a593Smuzhiyun #define DOUT_SCLK_BUS1_PLL 3 14*4882a593Smuzhiyun #define DOUT_SCLK_CC_PLL 4 15*4882a593Smuzhiyun #define DOUT_SCLK_MFC_PLL 5 16*4882a593Smuzhiyun #define DOUT_ACLK_CCORE_133 6 17*4882a593Smuzhiyun #define DOUT_ACLK_MSCL_532 7 18*4882a593Smuzhiyun #define ACLK_MSCL_532 8 19*4882a593Smuzhiyun #define DOUT_SCLK_AUD_PLL 9 20*4882a593Smuzhiyun #define FOUT_AUD_PLL 10 21*4882a593Smuzhiyun #define SCLK_AUD_PLL 11 22*4882a593Smuzhiyun #define SCLK_MFC_PLL_B 12 23*4882a593Smuzhiyun #define SCLK_MFC_PLL_A 13 24*4882a593Smuzhiyun #define SCLK_BUS1_PLL_B 14 25*4882a593Smuzhiyun #define SCLK_BUS1_PLL_A 15 26*4882a593Smuzhiyun #define SCLK_BUS0_PLL_B 16 27*4882a593Smuzhiyun #define SCLK_BUS0_PLL_A 17 28*4882a593Smuzhiyun #define SCLK_CC_PLL_B 18 29*4882a593Smuzhiyun #define SCLK_CC_PLL_A 19 30*4882a593Smuzhiyun #define ACLK_CCORE_133 20 31*4882a593Smuzhiyun #define ACLK_PERIS_66 21 32*4882a593Smuzhiyun #define TOPC_NR_CLK 22 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* TOP0 */ 35*4882a593Smuzhiyun #define DOUT_ACLK_PERIC1 1 36*4882a593Smuzhiyun #define DOUT_ACLK_PERIC0 2 37*4882a593Smuzhiyun #define CLK_SCLK_UART0 3 38*4882a593Smuzhiyun #define CLK_SCLK_UART1 4 39*4882a593Smuzhiyun #define CLK_SCLK_UART2 5 40*4882a593Smuzhiyun #define CLK_SCLK_UART3 6 41*4882a593Smuzhiyun #define CLK_SCLK_SPI0 7 42*4882a593Smuzhiyun #define CLK_SCLK_SPI1 8 43*4882a593Smuzhiyun #define CLK_SCLK_SPI2 9 44*4882a593Smuzhiyun #define CLK_SCLK_SPI3 10 45*4882a593Smuzhiyun #define CLK_SCLK_SPI4 11 46*4882a593Smuzhiyun #define CLK_SCLK_SPDIF 12 47*4882a593Smuzhiyun #define CLK_SCLK_PCM1 13 48*4882a593Smuzhiyun #define CLK_SCLK_I2S1 14 49*4882a593Smuzhiyun #define CLK_ACLK_PERIC0_66 15 50*4882a593Smuzhiyun #define CLK_ACLK_PERIC1_66 16 51*4882a593Smuzhiyun #define TOP0_NR_CLK 17 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* TOP1 */ 54*4882a593Smuzhiyun #define DOUT_ACLK_FSYS1_200 1 55*4882a593Smuzhiyun #define DOUT_ACLK_FSYS0_200 2 56*4882a593Smuzhiyun #define DOUT_SCLK_MMC2 3 57*4882a593Smuzhiyun #define DOUT_SCLK_MMC1 4 58*4882a593Smuzhiyun #define DOUT_SCLK_MMC0 5 59*4882a593Smuzhiyun #define CLK_SCLK_MMC2 6 60*4882a593Smuzhiyun #define CLK_SCLK_MMC1 7 61*4882a593Smuzhiyun #define CLK_SCLK_MMC0 8 62*4882a593Smuzhiyun #define CLK_ACLK_FSYS0_200 9 63*4882a593Smuzhiyun #define CLK_ACLK_FSYS1_200 10 64*4882a593Smuzhiyun #define CLK_SCLK_PHY_FSYS1 11 65*4882a593Smuzhiyun #define CLK_SCLK_PHY_FSYS1_26M 12 66*4882a593Smuzhiyun #define MOUT_SCLK_UFSUNIPRO20 13 67*4882a593Smuzhiyun #define DOUT_SCLK_UFSUNIPRO20 14 68*4882a593Smuzhiyun #define CLK_SCLK_UFSUNIPRO20 15 69*4882a593Smuzhiyun #define DOUT_SCLK_PHY_FSYS1 16 70*4882a593Smuzhiyun #define DOUT_SCLK_PHY_FSYS1_26M 17 71*4882a593Smuzhiyun #define TOP1_NR_CLK 18 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* CCORE */ 74*4882a593Smuzhiyun #define PCLK_RTC 1 75*4882a593Smuzhiyun #define CCORE_NR_CLK 2 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* PERIC0 */ 78*4882a593Smuzhiyun #define PCLK_UART0 1 79*4882a593Smuzhiyun #define SCLK_UART0 2 80*4882a593Smuzhiyun #define PCLK_HSI2C0 3 81*4882a593Smuzhiyun #define PCLK_HSI2C1 4 82*4882a593Smuzhiyun #define PCLK_HSI2C4 5 83*4882a593Smuzhiyun #define PCLK_HSI2C5 6 84*4882a593Smuzhiyun #define PCLK_HSI2C9 7 85*4882a593Smuzhiyun #define PCLK_HSI2C10 8 86*4882a593Smuzhiyun #define PCLK_HSI2C11 9 87*4882a593Smuzhiyun #define PCLK_PWM 10 88*4882a593Smuzhiyun #define SCLK_PWM 11 89*4882a593Smuzhiyun #define PCLK_ADCIF 12 90*4882a593Smuzhiyun #define PERIC0_NR_CLK 13 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* PERIC1 */ 93*4882a593Smuzhiyun #define PCLK_UART1 1 94*4882a593Smuzhiyun #define PCLK_UART2 2 95*4882a593Smuzhiyun #define PCLK_UART3 3 96*4882a593Smuzhiyun #define SCLK_UART1 4 97*4882a593Smuzhiyun #define SCLK_UART2 5 98*4882a593Smuzhiyun #define SCLK_UART3 6 99*4882a593Smuzhiyun #define PCLK_HSI2C2 7 100*4882a593Smuzhiyun #define PCLK_HSI2C3 8 101*4882a593Smuzhiyun #define PCLK_HSI2C6 9 102*4882a593Smuzhiyun #define PCLK_HSI2C7 10 103*4882a593Smuzhiyun #define PCLK_HSI2C8 11 104*4882a593Smuzhiyun #define PCLK_SPI0 12 105*4882a593Smuzhiyun #define PCLK_SPI1 13 106*4882a593Smuzhiyun #define PCLK_SPI2 14 107*4882a593Smuzhiyun #define PCLK_SPI3 15 108*4882a593Smuzhiyun #define PCLK_SPI4 16 109*4882a593Smuzhiyun #define SCLK_SPI0 17 110*4882a593Smuzhiyun #define SCLK_SPI1 18 111*4882a593Smuzhiyun #define SCLK_SPI2 19 112*4882a593Smuzhiyun #define SCLK_SPI3 20 113*4882a593Smuzhiyun #define SCLK_SPI4 21 114*4882a593Smuzhiyun #define PCLK_I2S1 22 115*4882a593Smuzhiyun #define PCLK_PCM1 23 116*4882a593Smuzhiyun #define PCLK_SPDIF 24 117*4882a593Smuzhiyun #define SCLK_I2S1 25 118*4882a593Smuzhiyun #define SCLK_PCM1 26 119*4882a593Smuzhiyun #define SCLK_SPDIF 27 120*4882a593Smuzhiyun #define PERIC1_NR_CLK 28 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* PERIS */ 123*4882a593Smuzhiyun #define PCLK_CHIPID 1 124*4882a593Smuzhiyun #define SCLK_CHIPID 2 125*4882a593Smuzhiyun #define PCLK_WDT 3 126*4882a593Smuzhiyun #define PCLK_TMU 4 127*4882a593Smuzhiyun #define SCLK_TMU 5 128*4882a593Smuzhiyun #define PERIS_NR_CLK 6 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* FSYS0 */ 131*4882a593Smuzhiyun #define ACLK_MMC2 1 132*4882a593Smuzhiyun #define ACLK_AXIUS_USBDRD30X_FSYS0X 2 133*4882a593Smuzhiyun #define ACLK_USBDRD300 3 134*4882a593Smuzhiyun #define SCLK_USBDRD300_SUSPENDCLK 4 135*4882a593Smuzhiyun #define SCLK_USBDRD300_REFCLK 5 136*4882a593Smuzhiyun #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 137*4882a593Smuzhiyun #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 138*4882a593Smuzhiyun #define OSCCLK_PHY_CLKOUT_USB30_PHY 8 139*4882a593Smuzhiyun #define ACLK_PDMA0 9 140*4882a593Smuzhiyun #define ACLK_PDMA1 10 141*4882a593Smuzhiyun #define FSYS0_NR_CLK 11 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* FSYS1 */ 144*4882a593Smuzhiyun #define ACLK_MMC1 1 145*4882a593Smuzhiyun #define ACLK_MMC0 2 146*4882a593Smuzhiyun #define PHYCLK_UFS20_TX0_SYMBOL 3 147*4882a593Smuzhiyun #define PHYCLK_UFS20_RX0_SYMBOL 4 148*4882a593Smuzhiyun #define PHYCLK_UFS20_RX1_SYMBOL 5 149*4882a593Smuzhiyun #define ACLK_UFS20_LINK 6 150*4882a593Smuzhiyun #define SCLK_UFSUNIPRO20_USER 7 151*4882a593Smuzhiyun #define PHYCLK_UFS20_RX1_SYMBOL_USER 8 152*4882a593Smuzhiyun #define PHYCLK_UFS20_RX0_SYMBOL_USER 9 153*4882a593Smuzhiyun #define PHYCLK_UFS20_TX0_SYMBOL_USER 10 154*4882a593Smuzhiyun #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 155*4882a593Smuzhiyun #define SCLK_COMBO_PHY_EMBEDDED_26M 12 156*4882a593Smuzhiyun #define DOUT_PCLK_FSYS1 13 157*4882a593Smuzhiyun #define PCLK_GPIO_FSYS1 14 158*4882a593Smuzhiyun #define MOUT_FSYS1_PHYCLK_SEL1 15 159*4882a593Smuzhiyun #define FSYS1_NR_CLK 16 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* MSCL */ 162*4882a593Smuzhiyun #define USERMUX_ACLK_MSCL_532 1 163*4882a593Smuzhiyun #define DOUT_PCLK_MSCL 2 164*4882a593Smuzhiyun #define ACLK_MSCL_0 3 165*4882a593Smuzhiyun #define ACLK_MSCL_1 4 166*4882a593Smuzhiyun #define ACLK_JPEG 5 167*4882a593Smuzhiyun #define ACLK_G2D 6 168*4882a593Smuzhiyun #define ACLK_LH_ASYNC_SI_MSCL_0 7 169*4882a593Smuzhiyun #define ACLK_LH_ASYNC_SI_MSCL_1 8 170*4882a593Smuzhiyun #define ACLK_AXI2ACEL_BRIDGE 9 171*4882a593Smuzhiyun #define ACLK_XIU_MSCLX_0 10 172*4882a593Smuzhiyun #define ACLK_XIU_MSCLX_1 11 173*4882a593Smuzhiyun #define ACLK_QE_MSCL_0 12 174*4882a593Smuzhiyun #define ACLK_QE_MSCL_1 13 175*4882a593Smuzhiyun #define ACLK_QE_JPEG 14 176*4882a593Smuzhiyun #define ACLK_QE_G2D 15 177*4882a593Smuzhiyun #define ACLK_PPMU_MSCL_0 16 178*4882a593Smuzhiyun #define ACLK_PPMU_MSCL_1 17 179*4882a593Smuzhiyun #define ACLK_MSCLNP_133 18 180*4882a593Smuzhiyun #define ACLK_AHB2APB_MSCL0P 19 181*4882a593Smuzhiyun #define ACLK_AHB2APB_MSCL1P 20 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define PCLK_MSCL_0 21 184*4882a593Smuzhiyun #define PCLK_MSCL_1 22 185*4882a593Smuzhiyun #define PCLK_JPEG 23 186*4882a593Smuzhiyun #define PCLK_G2D 24 187*4882a593Smuzhiyun #define PCLK_QE_MSCL_0 25 188*4882a593Smuzhiyun #define PCLK_QE_MSCL_1 26 189*4882a593Smuzhiyun #define PCLK_QE_JPEG 27 190*4882a593Smuzhiyun #define PCLK_QE_G2D 28 191*4882a593Smuzhiyun #define PCLK_PPMU_MSCL_0 29 192*4882a593Smuzhiyun #define PCLK_PPMU_MSCL_1 30 193*4882a593Smuzhiyun #define PCLK_AXI2ACEL_BRIDGE 31 194*4882a593Smuzhiyun #define PCLK_PMU_MSCL 32 195*4882a593Smuzhiyun #define MSCL_NR_CLK 33 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* AUD */ 198*4882a593Smuzhiyun #define SCLK_I2S 1 199*4882a593Smuzhiyun #define SCLK_PCM 2 200*4882a593Smuzhiyun #define PCLK_I2S 3 201*4882a593Smuzhiyun #define PCLK_PCM 4 202*4882a593Smuzhiyun #define ACLK_ADMA 5 203*4882a593Smuzhiyun #define AUD_NR_CLK 6 204*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 205