1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define PLL_NPLL 5 16 #define ARMCLK 6 17 18 /* sclk gates (special clocks) */ 19 #define SCLK_GPU 64 20 #define SCLK_SPI0 65 21 #define SCLK_SPI1 66 22 #define SCLK_SPI2 67 23 #define SCLK_SDMMC 68 24 #define SCLK_SDIO0 69 25 #define SCLK_SDIO1 70 26 #define SCLK_EMMC 71 27 #define SCLK_TSADC 72 28 #define SCLK_SARADC 73 29 #define SCLK_PS2C 74 30 #define SCLK_NANDC0 75 31 #define SCLK_NANDC1 76 32 #define SCLK_UART0 77 33 #define SCLK_UART1 78 34 #define SCLK_UART2 79 35 #define SCLK_UART3 80 36 #define SCLK_UART4 81 37 #define SCLK_I2S0 82 38 #define SCLK_SPDIF 83 39 #define SCLK_SPDIF8CH 84 40 #define SCLK_TIMER0 85 41 #define SCLK_TIMER1 86 42 #define SCLK_TIMER2 87 43 #define SCLK_TIMER3 88 44 #define SCLK_TIMER4 89 45 #define SCLK_TIMER5 90 46 #define SCLK_TIMER6 91 47 #define SCLK_HSADC 92 48 #define SCLK_OTGPHY0 93 49 #define SCLK_OTGPHY1 94 50 #define SCLK_OTGPHY2 95 51 #define SCLK_OTG_ADP 96 52 #define SCLK_HSICPHY480M 97 53 #define SCLK_HSICPHY12M 98 54 #define SCLK_MACREF 99 55 #define SCLK_LCDC_PWM0 100 56 #define SCLK_LCDC_PWM1 101 57 #define SCLK_MAC_RX 102 58 #define SCLK_MAC_TX 103 59 #define SCLK_EDP_24M 104 60 #define SCLK_EDP 105 61 #define SCLK_RGA 106 62 #define SCLK_ISP 107 63 #define SCLK_ISP_JPE 108 64 #define SCLK_HDMI_HDCP 109 65 #define SCLK_HDMI_CEC 110 66 #define SCLK_HEVC_CABAC 111 67 #define SCLK_HEVC_CORE 112 68 #define SCLK_I2S0_OUT 113 69 #define SCLK_SDMMC_DRV 114 70 #define SCLK_SDIO0_DRV 115 71 #define SCLK_SDIO1_DRV 116 72 #define SCLK_EMMC_DRV 117 73 #define SCLK_SDMMC_SAMPLE 118 74 #define SCLK_SDIO0_SAMPLE 119 75 #define SCLK_SDIO1_SAMPLE 120 76 #define SCLK_EMMC_SAMPLE 121 77 #define SCLK_USBPHY480M_SRC 122 78 #define SCLK_PVTM_CORE 123 79 #define SCLK_PVTM_GPU 124 80 #define SCLK_CRYPTO 125 81 #define SCLK_MIPIDSI_24M 126 82 #define SCLK_VIP_OUT 127 83 #define SCLK_DDRCLK 128 84 #define SCLK_I2S_SRC 129 85 #define SCLK_TSPOUT 130 86 #define SCLK_TSP 131 87 #define SCLK_HSADC0_TSP 132 88 #define SCLK_HSADC1_TSP 133 89 #define SCLK_27M_TSP 134 90 91 #define SCLK_MAC_PLL 150 92 #define SCLK_MAC 151 93 #define SCLK_MACREF_OUT 152 94 #define SCLK_TESTOUT_SRC 153 95 #define SCLK_TESTOUT 154 96 97 #define DCLK_VOP0 190 98 #define DCLK_VOP1 191 99 100 /* aclk gates */ 101 #define ACLK_GPU 192 102 #define ACLK_DMAC1 193 103 #define ACLK_DMAC2 194 104 #define ACLK_MMU 195 105 #define ACLK_GMAC 196 106 #define ACLK_VOP0 197 107 #define ACLK_VOP1 198 108 #define ACLK_CRYPTO 199 109 #define ACLK_RGA 200 110 #define ACLK_RGA_NIU 201 111 #define ACLK_IEP 202 112 #define ACLK_VIO0_NIU 203 113 #define ACLK_VIP 204 114 #define ACLK_ISP 205 115 #define ACLK_VIO1_NIU 206 116 #define ACLK_HEVC 207 117 #define ACLK_VCODEC 208 118 #define ACLK_CPU 209 119 #define ACLK_PERI 210 120 #define ACLK_VIO0 211 121 #define ACLK_VIO1 212 122 123 /* pclk gates */ 124 #define PCLK_GPIO0 320 125 #define PCLK_GPIO1 321 126 #define PCLK_GPIO2 322 127 #define PCLK_GPIO3 323 128 #define PCLK_GPIO4 324 129 #define PCLK_GPIO5 325 130 #define PCLK_GPIO6 326 131 #define PCLK_GPIO7 327 132 #define PCLK_GPIO8 328 133 #define PCLK_GRF 329 134 #define PCLK_SGRF 330 135 #define PCLK_PMU 331 136 #define PCLK_I2C0 332 137 #define PCLK_I2C1 333 138 #define PCLK_I2C2 334 139 #define PCLK_I2C3 335 140 #define PCLK_I2C4 336 141 #define PCLK_I2C5 337 142 #define PCLK_SPI0 338 143 #define PCLK_SPI1 339 144 #define PCLK_SPI2 340 145 #define PCLK_UART0 341 146 #define PCLK_UART1 342 147 #define PCLK_UART2 343 148 #define PCLK_UART3 344 149 #define PCLK_UART4 345 150 #define PCLK_TSADC 346 151 #define PCLK_SARADC 347 152 #define PCLK_SIM 348 153 #define PCLK_GMAC 349 154 #define PCLK_PWM 350 155 #define PCLK_RKPWM 351 156 #define PCLK_PS2C 352 157 #define PCLK_TIMER 353 158 #define PCLK_TZPC 354 159 #define PCLK_EDP_CTRL 355 160 #define PCLK_MIPI_DSI0 356 161 #define PCLK_MIPI_DSI1 357 162 #define PCLK_MIPI_CSI 358 163 #define PCLK_LVDS_PHY 359 164 #define PCLK_HDMI_CTRL 360 165 #define PCLK_VIO2_H2P 361 166 #define PCLK_CPU 362 167 #define PCLK_PERI 363 168 #define PCLK_DDRUPCTL0 364 169 #define PCLK_PUBL0 365 170 #define PCLK_DDRUPCTL1 366 171 #define PCLK_PUBL1 367 172 #define PCLK_WDT 368 173 #define PCLK_EFUSE256 369 174 #define PCLK_EFUSE1024 370 175 #define PCLK_ISP_IN 371 176 #define PCLK_VIP 372 177 #define PCLK_VIP_IN 373 178 #define PCLK_PD_ALIVE 374 179 #define PCLK_PD_PMU 375 180 181 /* hclk gates */ 182 #define HCLK_GPS 448 183 #define HCLK_OTG0 449 184 #define HCLK_USBHOST0 450 185 #define HCLK_USBHOST1 451 186 #define HCLK_HSIC 452 187 #define HCLK_NANDC0 453 188 #define HCLK_NANDC1 454 189 #define HCLK_TSP 455 190 #define HCLK_SDMMC 456 191 #define HCLK_SDIO0 457 192 #define HCLK_SDIO1 458 193 #define HCLK_EMMC 459 194 #define HCLK_HSADC 460 195 #define HCLK_CRYPTO 461 196 #define HCLK_I2S0 462 197 #define HCLK_SPDIF 463 198 #define HCLK_SPDIF8CH 464 199 #define HCLK_VOP0 465 200 #define HCLK_VOP1 466 201 #define HCLK_ROM 467 202 #define HCLK_IEP 468 203 #define HCLK_ISP 469 204 #define HCLK_RGA 470 205 #define HCLK_VIO_AHB_ARBI 471 206 #define HCLK_VIO_NIU 472 207 #define HCLK_VIP 473 208 #define HCLK_VIO2_H2P 474 209 #define HCLK_HEVC 475 210 #define HCLK_VCODEC 476 211 #define HCLK_CPU 477 212 #define HCLK_PERI 478 213 #define HCLK_USB_PERI 479 214 #define HCLK_VIO 480 215 216 #define CLK_NR_CLKS (HCLK_VIO + 1) 217 218 /* soft-reset indices */ 219 #define SRST_CORE0 0 220 #define SRST_CORE1 1 221 #define SRST_CORE2 2 222 #define SRST_CORE3 3 223 #define SRST_CORE0_PO 4 224 #define SRST_CORE1_PO 5 225 #define SRST_CORE2_PO 6 226 #define SRST_CORE3_PO 7 227 #define SRST_PDCORE_STRSYS 8 228 #define SRST_PDBUS_STRSYS 9 229 #define SRST_L2C 10 230 #define SRST_TOPDBG 11 231 #define SRST_CORE0_DBG 12 232 #define SRST_CORE1_DBG 13 233 #define SRST_CORE2_DBG 14 234 #define SRST_CORE3_DBG 15 235 236 #define SRST_PDBUG_AHB_ARBITOR 16 237 #define SRST_EFUSE256 17 238 #define SRST_DMAC1 18 239 #define SRST_INTMEM 19 240 #define SRST_ROM 20 241 #define SRST_SPDIF8CH 21 242 #define SRST_TIMER 22 243 #define SRST_I2S0 23 244 #define SRST_SPDIF 24 245 #define SRST_TIMER0 25 246 #define SRST_TIMER1 26 247 #define SRST_TIMER2 27 248 #define SRST_TIMER3 28 249 #define SRST_TIMER4 29 250 #define SRST_TIMER5 30 251 #define SRST_EFUSE 31 252 253 #define SRST_GPIO0 32 254 #define SRST_GPIO1 33 255 #define SRST_GPIO2 34 256 #define SRST_GPIO3 35 257 #define SRST_GPIO4 36 258 #define SRST_GPIO5 37 259 #define SRST_GPIO6 38 260 #define SRST_GPIO7 39 261 #define SRST_GPIO8 40 262 #define SRST_I2C0 42 263 #define SRST_I2C1 43 264 #define SRST_I2C2 44 265 #define SRST_I2C3 45 266 #define SRST_I2C4 46 267 #define SRST_I2C5 47 268 269 #define SRST_DWPWM 48 270 #define SRST_MMC_PERI 49 271 #define SRST_PERIPH_MMU 50 272 #define SRST_DAP 51 273 #define SRST_DAP_SYS 52 274 #define SRST_TPIU 53 275 #define SRST_PMU_APB 54 276 #define SRST_GRF 55 277 #define SRST_PMU 56 278 #define SRST_PERIPH_AXI 57 279 #define SRST_PERIPH_AHB 58 280 #define SRST_PERIPH_APB 59 281 #define SRST_PERIPH_NIU 60 282 #define SRST_PDPERI_AHB_ARBI 61 283 #define SRST_EMEM 62 284 #define SRST_USB_PERI 63 285 286 #define SRST_DMAC2 64 287 #define SRST_MAC 66 288 #define SRST_GPS 67 289 #define SRST_RKPWM 69 290 #define SRST_CCP 71 291 #define SRST_USBHOST0 72 292 #define SRST_HSIC 73 293 #define SRST_HSIC_AUX 74 294 #define SRST_HSIC_PHY 75 295 #define SRST_HSADC 76 296 #define SRST_NANDC0 77 297 #define SRST_NANDC1 78 298 299 #define SRST_TZPC 80 300 #define SRST_SPI0 83 301 #define SRST_SPI1 84 302 #define SRST_SPI2 85 303 #define SRST_SARADC 87 304 #define SRST_PDALIVE_NIU 88 305 #define SRST_PDPMU_INTMEM 89 306 #define SRST_PDPMU_NIU 90 307 #define SRST_SGRF 91 308 309 #define SRST_VIO_ARBI 96 310 #define SRST_RGA_NIU 97 311 #define SRST_VIO0_NIU_AXI 98 312 #define SRST_VIO_NIU_AHB 99 313 #define SRST_LCDC0_AXI 100 314 #define SRST_LCDC0_AHB 101 315 #define SRST_LCDC0_DCLK 102 316 #define SRST_VIO1_NIU_AXI 103 317 #define SRST_VIP 104 318 #define SRST_RGA_CORE 105 319 #define SRST_IEP_AXI 106 320 #define SRST_IEP_AHB 107 321 #define SRST_RGA_AXI 108 322 #define SRST_RGA_AHB 109 323 #define SRST_ISP 110 324 #define SRST_EDP 111 325 326 #define SRST_VCODEC_AXI 112 327 #define SRST_VCODEC_AHB 113 328 #define SRST_VIO_H2P 114 329 #define SRST_MIPIDSI0 115 330 #define SRST_MIPIDSI1 116 331 #define SRST_MIPICSI 117 332 #define SRST_LVDS_PHY 118 333 #define SRST_LVDS_CON 119 334 #define SRST_GPU 120 335 #define SRST_HDMI 121 336 #define SRST_CORE_PVTM 124 337 #define SRST_GPU_PVTM 125 338 339 #define SRST_MMC0 128 340 #define SRST_SDIO0 129 341 #define SRST_SDIO1 130 342 #define SRST_EMMC 131 343 #define SRST_USBOTG_AHB 132 344 #define SRST_USBOTG_PHY 133 345 #define SRST_USBOTG_CON 134 346 #define SRST_USBHOST0_AHB 135 347 #define SRST_USBHOST0_PHY 136 348 #define SRST_USBHOST0_CON 137 349 #define SRST_USBHOST1_AHB 138 350 #define SRST_USBHOST1_PHY 139 351 #define SRST_USBHOST1_CON 140 352 #define SRST_USB_ADP 141 353 #define SRST_ACC_EFUSE 142 354 355 #define SRST_CORESIGHT 144 356 #define SRST_PD_CORE_AHB_NOC 145 357 #define SRST_PD_CORE_APB_NOC 146 358 #define SRST_PD_CORE_MP_AXI 147 359 #define SRST_GIC 148 360 #define SRST_LCDC_PWM0 149 361 #define SRST_LCDC_PWM1 150 362 #define SRST_VIO0_H2P_BRG 151 363 #define SRST_VIO1_H2P_BRG 152 364 #define SRST_RGA_H2P_BRG 153 365 #define SRST_HEVC 154 366 #define SRST_TSADC 159 367 368 #define SRST_DDRPHY0 160 369 #define SRST_DDRPHY0_APB 161 370 #define SRST_DDRCTRL0 162 371 #define SRST_DDRCTRL0_APB 163 372 #define SRST_DDRPHY0_CTRL 164 373 #define SRST_DDRPHY1 165 374 #define SRST_DDRPHY1_APB 166 375 #define SRST_DDRCTRL1 167 376 #define SRST_DDRCTRL1_APB 168 377 #define SRST_DDRPHY1_CTRL 169 378 #define SRST_DDRMSCH0 170 379 #define SRST_DDRMSCH1 171 380 #define SRST_CRYPTO 174 381 #define SRST_C2C_HOST 175 382 383 #define SRST_LCDC1_AXI 176 384 #define SRST_LCDC1_AHB 177 385 #define SRST_LCDC1_DCLK 178 386 #define SRST_UART0 179 387 #define SRST_UART1 180 388 #define SRST_UART2 181 389 #define SRST_UART3 182 390 #define SRST_UART4 183 391 #define SRST_SIMC 186 392 #define SRST_PS2C 187 393 #define SRST_TSP 188 394 #define SRST_TSP_CLKIN0 189 395 #define SRST_TSP_CLKIN1 190 396 #define SRST_TSP_27M 191 397 398 #endif 399