1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* core clocks */ 10*4882a593Smuzhiyun #define PLL_APLLB 1 11*4882a593Smuzhiyun #define PLL_APLLL 2 12*4882a593Smuzhiyun #define PLL_DPLL 3 13*4882a593Smuzhiyun #define PLL_CPLL 4 14*4882a593Smuzhiyun #define PLL_GPLL 5 15*4882a593Smuzhiyun #define PLL_NPLL 6 16*4882a593Smuzhiyun #define ARMCLKB 7 17*4882a593Smuzhiyun #define ARMCLKL 8 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* sclk gates (special clocks) */ 20*4882a593Smuzhiyun #define SCLK_GPU_CORE 64 21*4882a593Smuzhiyun #define SCLK_SPI0 65 22*4882a593Smuzhiyun #define SCLK_SPI1 66 23*4882a593Smuzhiyun #define SCLK_SPI2 67 24*4882a593Smuzhiyun #define SCLK_SDMMC 68 25*4882a593Smuzhiyun #define SCLK_SDIO0 69 26*4882a593Smuzhiyun #define SCLK_EMMC 71 27*4882a593Smuzhiyun #define SCLK_TSADC 72 28*4882a593Smuzhiyun #define SCLK_SARADC 73 29*4882a593Smuzhiyun #define SCLK_NANDC0 75 30*4882a593Smuzhiyun #define SCLK_UART0 77 31*4882a593Smuzhiyun #define SCLK_UART1 78 32*4882a593Smuzhiyun #define SCLK_UART2 79 33*4882a593Smuzhiyun #define SCLK_UART3 80 34*4882a593Smuzhiyun #define SCLK_UART4 81 35*4882a593Smuzhiyun #define SCLK_I2S_8CH 82 36*4882a593Smuzhiyun #define SCLK_SPDIF_8CH 83 37*4882a593Smuzhiyun #define SCLK_I2S_2CH 84 38*4882a593Smuzhiyun #define SCLK_TIMER00 85 39*4882a593Smuzhiyun #define SCLK_TIMER01 86 40*4882a593Smuzhiyun #define SCLK_TIMER02 87 41*4882a593Smuzhiyun #define SCLK_TIMER03 88 42*4882a593Smuzhiyun #define SCLK_TIMER04 89 43*4882a593Smuzhiyun #define SCLK_TIMER05 90 44*4882a593Smuzhiyun #define SCLK_OTGPHY0 93 45*4882a593Smuzhiyun #define SCLK_OTG_ADP 96 46*4882a593Smuzhiyun #define SCLK_HSICPHY480M 97 47*4882a593Smuzhiyun #define SCLK_HSICPHY12M 98 48*4882a593Smuzhiyun #define SCLK_MACREF 99 49*4882a593Smuzhiyun #define SCLK_VOP0_PWM 100 50*4882a593Smuzhiyun #define SCLK_MAC_RX 102 51*4882a593Smuzhiyun #define SCLK_MAC_TX 103 52*4882a593Smuzhiyun #define SCLK_EDP_24M 104 53*4882a593Smuzhiyun #define SCLK_EDP 105 54*4882a593Smuzhiyun #define SCLK_RGA 106 55*4882a593Smuzhiyun #define SCLK_ISP 107 56*4882a593Smuzhiyun #define SCLK_HDCP 108 57*4882a593Smuzhiyun #define SCLK_HDMI_HDCP 109 58*4882a593Smuzhiyun #define SCLK_HDMI_CEC 110 59*4882a593Smuzhiyun #define SCLK_HEVC_CABAC 111 60*4882a593Smuzhiyun #define SCLK_HEVC_CORE 112 61*4882a593Smuzhiyun #define SCLK_I2S_8CH_OUT 113 62*4882a593Smuzhiyun #define SCLK_SDMMC_DRV 114 63*4882a593Smuzhiyun #define SCLK_SDIO0_DRV 115 64*4882a593Smuzhiyun #define SCLK_EMMC_DRV 117 65*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE 118 66*4882a593Smuzhiyun #define SCLK_SDIO0_SAMPLE 119 67*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE 121 68*4882a593Smuzhiyun #define SCLK_USBPHY480M 122 69*4882a593Smuzhiyun #define SCLK_PVTM_CORE 123 70*4882a593Smuzhiyun #define SCLK_PVTM_GPU 124 71*4882a593Smuzhiyun #define SCLK_PVTM_PMU 125 72*4882a593Smuzhiyun #define SCLK_SFC 126 73*4882a593Smuzhiyun #define SCLK_MAC 127 74*4882a593Smuzhiyun #define SCLK_MACREF_OUT 128 75*4882a593Smuzhiyun #define SCLK_TIMER10 133 76*4882a593Smuzhiyun #define SCLK_TIMER11 134 77*4882a593Smuzhiyun #define SCLK_TIMER12 135 78*4882a593Smuzhiyun #define SCLK_TIMER13 136 79*4882a593Smuzhiyun #define SCLK_TIMER14 137 80*4882a593Smuzhiyun #define SCLK_TIMER15 138 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define DCLK_VOP 190 83*4882a593Smuzhiyun #define MCLK_CRYPTO 191 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* aclk gates */ 86*4882a593Smuzhiyun #define ACLK_GPU_MEM 192 87*4882a593Smuzhiyun #define ACLK_GPU_CFG 193 88*4882a593Smuzhiyun #define ACLK_DMAC_BUS 194 89*4882a593Smuzhiyun #define ACLK_DMAC_PERI 195 90*4882a593Smuzhiyun #define ACLK_PERI_MMU 196 91*4882a593Smuzhiyun #define ACLK_GMAC 197 92*4882a593Smuzhiyun #define ACLK_VOP 198 93*4882a593Smuzhiyun #define ACLK_VOP_IEP 199 94*4882a593Smuzhiyun #define ACLK_RGA 200 95*4882a593Smuzhiyun #define ACLK_HDCP 201 96*4882a593Smuzhiyun #define ACLK_IEP 202 97*4882a593Smuzhiyun #define ACLK_VIO0_NOC 203 98*4882a593Smuzhiyun #define ACLK_VIP 204 99*4882a593Smuzhiyun #define ACLK_ISP 205 100*4882a593Smuzhiyun #define ACLK_VIO1_NOC 206 101*4882a593Smuzhiyun #define ACLK_VIDEO 208 102*4882a593Smuzhiyun #define ACLK_BUS 209 103*4882a593Smuzhiyun #define ACLK_PERI 210 104*4882a593Smuzhiyun #define ACLK_CCI_PRE 211 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* pclk gates */ 107*4882a593Smuzhiyun #define PCLK_GPIO0 320 108*4882a593Smuzhiyun #define PCLK_GPIO1 321 109*4882a593Smuzhiyun #define PCLK_GPIO2 322 110*4882a593Smuzhiyun #define PCLK_GPIO3 323 111*4882a593Smuzhiyun #define PCLK_PMUGRF 324 112*4882a593Smuzhiyun #define PCLK_MAILBOX 325 113*4882a593Smuzhiyun #define PCLK_GRF 329 114*4882a593Smuzhiyun #define PCLK_SGRF 330 115*4882a593Smuzhiyun #define PCLK_PMU 331 116*4882a593Smuzhiyun #define PCLK_I2C0 332 117*4882a593Smuzhiyun #define PCLK_I2C1 333 118*4882a593Smuzhiyun #define PCLK_I2C2 334 119*4882a593Smuzhiyun #define PCLK_I2C3 335 120*4882a593Smuzhiyun #define PCLK_I2C4 336 121*4882a593Smuzhiyun #define PCLK_I2C5 337 122*4882a593Smuzhiyun #define PCLK_SPI0 338 123*4882a593Smuzhiyun #define PCLK_SPI1 339 124*4882a593Smuzhiyun #define PCLK_SPI2 340 125*4882a593Smuzhiyun #define PCLK_UART0 341 126*4882a593Smuzhiyun #define PCLK_UART1 342 127*4882a593Smuzhiyun #define PCLK_UART2 343 128*4882a593Smuzhiyun #define PCLK_UART3 344 129*4882a593Smuzhiyun #define PCLK_UART4 345 130*4882a593Smuzhiyun #define PCLK_TSADC 346 131*4882a593Smuzhiyun #define PCLK_SARADC 347 132*4882a593Smuzhiyun #define PCLK_SIM 348 133*4882a593Smuzhiyun #define PCLK_GMAC 349 134*4882a593Smuzhiyun #define PCLK_PWM0 350 135*4882a593Smuzhiyun #define PCLK_PWM1 351 136*4882a593Smuzhiyun #define PCLK_TIMER0 353 137*4882a593Smuzhiyun #define PCLK_TIMER1 354 138*4882a593Smuzhiyun #define PCLK_EDP_CTRL 355 139*4882a593Smuzhiyun #define PCLK_MIPI_DSI0 356 140*4882a593Smuzhiyun #define PCLK_MIPI_CSI 358 141*4882a593Smuzhiyun #define PCLK_HDCP 359 142*4882a593Smuzhiyun #define PCLK_HDMI_CTRL 360 143*4882a593Smuzhiyun #define PCLK_VIO_H2P 361 144*4882a593Smuzhiyun #define PCLK_BUS 362 145*4882a593Smuzhiyun #define PCLK_PERI 363 146*4882a593Smuzhiyun #define PCLK_DDRUPCTL 364 147*4882a593Smuzhiyun #define PCLK_DDRPHY 365 148*4882a593Smuzhiyun #define PCLK_ISP 366 149*4882a593Smuzhiyun #define PCLK_VIP 367 150*4882a593Smuzhiyun #define PCLK_WDT 368 151*4882a593Smuzhiyun #define PCLK_EFUSE256 369 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* hclk gates */ 154*4882a593Smuzhiyun #define HCLK_SFC 448 155*4882a593Smuzhiyun #define HCLK_OTG0 449 156*4882a593Smuzhiyun #define HCLK_HOST0 450 157*4882a593Smuzhiyun #define HCLK_HOST1 451 158*4882a593Smuzhiyun #define HCLK_HSIC 452 159*4882a593Smuzhiyun #define HCLK_NANDC0 453 160*4882a593Smuzhiyun #define HCLK_TSP 455 161*4882a593Smuzhiyun #define HCLK_SDMMC 456 162*4882a593Smuzhiyun #define HCLK_SDIO0 457 163*4882a593Smuzhiyun #define HCLK_EMMC 459 164*4882a593Smuzhiyun #define HCLK_HSADC 460 165*4882a593Smuzhiyun #define HCLK_CRYPTO 461 166*4882a593Smuzhiyun #define HCLK_I2S_2CH 462 167*4882a593Smuzhiyun #define HCLK_I2S_8CH 463 168*4882a593Smuzhiyun #define HCLK_SPDIF 464 169*4882a593Smuzhiyun #define HCLK_VOP 465 170*4882a593Smuzhiyun #define HCLK_ROM 467 171*4882a593Smuzhiyun #define HCLK_IEP 468 172*4882a593Smuzhiyun #define HCLK_ISP 469 173*4882a593Smuzhiyun #define HCLK_RGA 470 174*4882a593Smuzhiyun #define HCLK_VIO_AHB_ARBI 471 175*4882a593Smuzhiyun #define HCLK_VIO_NOC 472 176*4882a593Smuzhiyun #define HCLK_VIP 473 177*4882a593Smuzhiyun #define HCLK_VIO_H2P 474 178*4882a593Smuzhiyun #define HCLK_VIO_HDCPMMU 475 179*4882a593Smuzhiyun #define HCLK_VIDEO 476 180*4882a593Smuzhiyun #define HCLK_BUS 477 181*4882a593Smuzhiyun #define HCLK_PERI 478 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define CLK_NR_CLKS (HCLK_PERI + 1) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* soft-reset indices */ 186*4882a593Smuzhiyun #define SRST_CORE_B0 0 187*4882a593Smuzhiyun #define SRST_CORE_B1 1 188*4882a593Smuzhiyun #define SRST_CORE_B2 2 189*4882a593Smuzhiyun #define SRST_CORE_B3 3 190*4882a593Smuzhiyun #define SRST_CORE_B0_PO 4 191*4882a593Smuzhiyun #define SRST_CORE_B1_PO 5 192*4882a593Smuzhiyun #define SRST_CORE_B2_PO 6 193*4882a593Smuzhiyun #define SRST_CORE_B3_PO 7 194*4882a593Smuzhiyun #define SRST_L2_B 8 195*4882a593Smuzhiyun #define SRST_ADB_B 9 196*4882a593Smuzhiyun #define SRST_PD_CORE_B_NIU 10 197*4882a593Smuzhiyun #define SRST_PDBUS_STRSYS 11 198*4882a593Smuzhiyun #define SRST_SOCDBG_B 14 199*4882a593Smuzhiyun #define SRST_CORE_B_DBG 15 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define SRST_DMAC1 18 202*4882a593Smuzhiyun #define SRST_INTMEM 19 203*4882a593Smuzhiyun #define SRST_ROM 20 204*4882a593Smuzhiyun #define SRST_SPDIF8CH 21 205*4882a593Smuzhiyun #define SRST_I2S8CH 23 206*4882a593Smuzhiyun #define SRST_MAILBOX 24 207*4882a593Smuzhiyun #define SRST_I2S2CH 25 208*4882a593Smuzhiyun #define SRST_EFUSE_256 26 209*4882a593Smuzhiyun #define SRST_MCU_SYS 28 210*4882a593Smuzhiyun #define SRST_MCU_PO 29 211*4882a593Smuzhiyun #define SRST_MCU_NOC 30 212*4882a593Smuzhiyun #define SRST_EFUSE 31 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define SRST_GPIO0 32 215*4882a593Smuzhiyun #define SRST_GPIO1 33 216*4882a593Smuzhiyun #define SRST_GPIO2 34 217*4882a593Smuzhiyun #define SRST_GPIO3 35 218*4882a593Smuzhiyun #define SRST_GPIO4 36 219*4882a593Smuzhiyun #define SRST_PMUGRF 41 220*4882a593Smuzhiyun #define SRST_I2C0 42 221*4882a593Smuzhiyun #define SRST_I2C1 43 222*4882a593Smuzhiyun #define SRST_I2C2 44 223*4882a593Smuzhiyun #define SRST_I2C3 45 224*4882a593Smuzhiyun #define SRST_I2C4 46 225*4882a593Smuzhiyun #define SRST_I2C5 47 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define SRST_DWPWM 48 228*4882a593Smuzhiyun #define SRST_MMC_PERI 49 229*4882a593Smuzhiyun #define SRST_PERIPH_MMU 50 230*4882a593Smuzhiyun #define SRST_GRF 55 231*4882a593Smuzhiyun #define SRST_PMU 56 232*4882a593Smuzhiyun #define SRST_PERIPH_AXI 57 233*4882a593Smuzhiyun #define SRST_PERIPH_AHB 58 234*4882a593Smuzhiyun #define SRST_PERIPH_APB 59 235*4882a593Smuzhiyun #define SRST_PERIPH_NIU 60 236*4882a593Smuzhiyun #define SRST_PDPERI_AHB_ARBI 61 237*4882a593Smuzhiyun #define SRST_EMEM 62 238*4882a593Smuzhiyun #define SRST_USB_PERI 63 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define SRST_DMAC2 64 241*4882a593Smuzhiyun #define SRST_MAC 66 242*4882a593Smuzhiyun #define SRST_GPS 67 243*4882a593Smuzhiyun #define SRST_RKPWM 69 244*4882a593Smuzhiyun #define SRST_USBHOST0 72 245*4882a593Smuzhiyun #define SRST_HSIC 73 246*4882a593Smuzhiyun #define SRST_HSIC_AUX 74 247*4882a593Smuzhiyun #define SRST_HSIC_PHY 75 248*4882a593Smuzhiyun #define SRST_HSADC 76 249*4882a593Smuzhiyun #define SRST_NANDC0 77 250*4882a593Smuzhiyun #define SRST_SFC 79 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define SRST_SPI0 83 253*4882a593Smuzhiyun #define SRST_SPI1 84 254*4882a593Smuzhiyun #define SRST_SPI2 85 255*4882a593Smuzhiyun #define SRST_SARADC 87 256*4882a593Smuzhiyun #define SRST_PDALIVE_NIU 88 257*4882a593Smuzhiyun #define SRST_PDPMU_INTMEM 89 258*4882a593Smuzhiyun #define SRST_PDPMU_NIU 90 259*4882a593Smuzhiyun #define SRST_SGRF 91 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define SRST_VIO_ARBI 96 262*4882a593Smuzhiyun #define SRST_RGA_NIU 97 263*4882a593Smuzhiyun #define SRST_VIO0_NIU_AXI 98 264*4882a593Smuzhiyun #define SRST_VIO_NIU_AHB 99 265*4882a593Smuzhiyun #define SRST_LCDC0_AXI 100 266*4882a593Smuzhiyun #define SRST_LCDC0_AHB 101 267*4882a593Smuzhiyun #define SRST_LCDC0_DCLK 102 268*4882a593Smuzhiyun #define SRST_VIP 104 269*4882a593Smuzhiyun #define SRST_RGA_CORE 105 270*4882a593Smuzhiyun #define SRST_IEP_AXI 106 271*4882a593Smuzhiyun #define SRST_IEP_AHB 107 272*4882a593Smuzhiyun #define SRST_RGA_AXI 108 273*4882a593Smuzhiyun #define SRST_RGA_AHB 109 274*4882a593Smuzhiyun #define SRST_ISP 110 275*4882a593Smuzhiyun #define SRST_EDP_24M 111 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define SRST_VIDEO_AXI 112 278*4882a593Smuzhiyun #define SRST_VIDEO_AHB 113 279*4882a593Smuzhiyun #define SRST_MIPIDPHYTX 114 280*4882a593Smuzhiyun #define SRST_MIPIDSI0 115 281*4882a593Smuzhiyun #define SRST_MIPIDPHYRX 116 282*4882a593Smuzhiyun #define SRST_MIPICSI 117 283*4882a593Smuzhiyun #define SRST_GPU 120 284*4882a593Smuzhiyun #define SRST_HDMI 121 285*4882a593Smuzhiyun #define SRST_EDP 122 286*4882a593Smuzhiyun #define SRST_PMU_PVTM 123 287*4882a593Smuzhiyun #define SRST_CORE_PVTM 124 288*4882a593Smuzhiyun #define SRST_GPU_PVTM 125 289*4882a593Smuzhiyun #define SRST_GPU_SYS 126 290*4882a593Smuzhiyun #define SRST_GPU_MEM_NIU 127 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #define SRST_MMC0 128 293*4882a593Smuzhiyun #define SRST_SDIO0 129 294*4882a593Smuzhiyun #define SRST_EMMC 131 295*4882a593Smuzhiyun #define SRST_USBOTG_AHB 132 296*4882a593Smuzhiyun #define SRST_USBOTG_PHY 133 297*4882a593Smuzhiyun #define SRST_USBOTG_CON 134 298*4882a593Smuzhiyun #define SRST_USBHOST0_AHB 135 299*4882a593Smuzhiyun #define SRST_USBHOST0_PHY 136 300*4882a593Smuzhiyun #define SRST_USBHOST0_CON 137 301*4882a593Smuzhiyun #define SRST_USBOTG_UTMI 138 302*4882a593Smuzhiyun #define SRST_USBHOST1_UTMI 139 303*4882a593Smuzhiyun #define SRST_USB_ADP 141 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #define SRST_CORESIGHT 144 306*4882a593Smuzhiyun #define SRST_PD_CORE_AHB_NOC 145 307*4882a593Smuzhiyun #define SRST_PD_CORE_APB_NOC 146 308*4882a593Smuzhiyun #define SRST_GIC 148 309*4882a593Smuzhiyun #define SRST_LCDC_PWM0 149 310*4882a593Smuzhiyun #define SRST_RGA_H2P_BRG 153 311*4882a593Smuzhiyun #define SRST_VIDEO 154 312*4882a593Smuzhiyun #define SRST_GPU_CFG_NIU 157 313*4882a593Smuzhiyun #define SRST_TSADC 159 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define SRST_DDRPHY0 160 316*4882a593Smuzhiyun #define SRST_DDRPHY0_APB 161 317*4882a593Smuzhiyun #define SRST_DDRCTRL0 162 318*4882a593Smuzhiyun #define SRST_DDRCTRL0_APB 163 319*4882a593Smuzhiyun #define SRST_VIDEO_NIU 165 320*4882a593Smuzhiyun #define SRST_VIDEO_NIU_AHB 167 321*4882a593Smuzhiyun #define SRST_DDRMSCH0 170 322*4882a593Smuzhiyun #define SRST_PDBUS_AHB 173 323*4882a593Smuzhiyun #define SRST_CRYPTO 174 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define SRST_UART0 179 326*4882a593Smuzhiyun #define SRST_UART1 180 327*4882a593Smuzhiyun #define SRST_UART2 181 328*4882a593Smuzhiyun #define SRST_UART3 182 329*4882a593Smuzhiyun #define SRST_UART4 183 330*4882a593Smuzhiyun #define SRST_SIMC 186 331*4882a593Smuzhiyun #define SRST_TSP 188 332*4882a593Smuzhiyun #define SRST_TSP_CLKIN0 189 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun #define SRST_CORE_L0 192 335*4882a593Smuzhiyun #define SRST_CORE_L1 193 336*4882a593Smuzhiyun #define SRST_CORE_L2 194 337*4882a593Smuzhiyun #define SRST_CORE_L3 195 338*4882a593Smuzhiyun #define SRST_CORE_L0_PO 195 339*4882a593Smuzhiyun #define SRST_CORE_L1_PO 197 340*4882a593Smuzhiyun #define SRST_CORE_L2_PO 198 341*4882a593Smuzhiyun #define SRST_CORE_L3_PO 199 342*4882a593Smuzhiyun #define SRST_L2_L 200 343*4882a593Smuzhiyun #define SRST_ADB_L 201 344*4882a593Smuzhiyun #define SRST_PD_CORE_L_NIU 202 345*4882a593Smuzhiyun #define SRST_CCI_SYS 203 346*4882a593Smuzhiyun #define SRST_CCI_DDR 204 347*4882a593Smuzhiyun #define SRST_CCI 205 348*4882a593Smuzhiyun #define SRST_SOCDBG_L 206 349*4882a593Smuzhiyun #define SRST_CORE_L_DBG 207 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun #define SRST_CORE_B0_NC 208 352*4882a593Smuzhiyun #define SRST_CORE_B0_PO_NC 209 353*4882a593Smuzhiyun #define SRST_L2_B_NC 210 354*4882a593Smuzhiyun #define SRST_ADB_B_NC 211 355*4882a593Smuzhiyun #define SRST_PD_CORE_B_NIU_NC 212 356*4882a593Smuzhiyun #define SRST_PDBUS_STRSYS_NC 213 357*4882a593Smuzhiyun #define SRST_CORE_L0_NC 214 358*4882a593Smuzhiyun #define SRST_CORE_L0_PO_NC 215 359*4882a593Smuzhiyun #define SRST_L2_L_NC 216 360*4882a593Smuzhiyun #define SRST_ADB_L_NC 217 361*4882a593Smuzhiyun #define SRST_PD_CORE_L_NIU_NC 218 362*4882a593Smuzhiyun #define SRST_CCI_SYS_NC 219 363*4882a593Smuzhiyun #define SRST_CCI_DDR_NC 220 364*4882a593Smuzhiyun #define SRST_CCI_NC 221 365*4882a593Smuzhiyun #define SRST_TRACE_NC 222 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun #define SRST_TIMER00 224 368*4882a593Smuzhiyun #define SRST_TIMER01 225 369*4882a593Smuzhiyun #define SRST_TIMER02 226 370*4882a593Smuzhiyun #define SRST_TIMER03 227 371*4882a593Smuzhiyun #define SRST_TIMER04 228 372*4882a593Smuzhiyun #define SRST_TIMER05 229 373*4882a593Smuzhiyun #define SRST_TIMER10 230 374*4882a593Smuzhiyun #define SRST_TIMER11 231 375*4882a593Smuzhiyun #define SRST_TIMER12 232 376*4882a593Smuzhiyun #define SRST_TIMER13 233 377*4882a593Smuzhiyun #define SRST_TIMER14 234 378*4882a593Smuzhiyun #define SRST_TIMER15 235 379*4882a593Smuzhiyun #define SRST_TIMER0_APB 236 380*4882a593Smuzhiyun #define SRST_TIMER1_APB 237 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #endif 383