1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 4 * Author: Xing Zheng <zhengxing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 9 10 #define RK3399_TWO_PLL_FOR_VOP 11 12 /* core clocks */ 13 #define PLL_APLLL 1 14 #define PLL_APLLB 2 15 #define PLL_DPLL 3 16 #define PLL_CPLL 4 17 #define PLL_GPLL 5 18 #define PLL_NPLL 6 19 #define PLL_VPLL 7 20 #define ARMCLKL 8 21 #define ARMCLKB 9 22 23 /* sclk gates (special clocks) */ 24 #define SCLK_I2SOUT_SRC 64 25 #define SCLK_I2C1 65 26 #define SCLK_I2C2 66 27 #define SCLK_I2C3 67 28 #define SCLK_I2C5 68 29 #define SCLK_I2C6 69 30 #define SCLK_I2C7 70 31 #define SCLK_SPI0 71 32 #define SCLK_SPI1 72 33 #define SCLK_SPI2 73 34 #define SCLK_SPI4 74 35 #define SCLK_SPI5 75 36 #define SCLK_SDMMC 76 37 #define SCLK_SDIO 77 38 #define SCLK_EMMC 78 39 #define SCLK_TSADC 79 40 #define SCLK_SARADC 80 41 #define SCLK_UART0 81 42 #define SCLK_UART1 82 43 #define SCLK_UART2 83 44 #define SCLK_UART3 84 45 #define SCLK_SPDIF_8CH 85 46 #define SCLK_I2S0_8CH 86 47 #define SCLK_I2S1_8CH 87 48 #define SCLK_I2S2_8CH 88 49 #define SCLK_I2S_8CH_OUT 89 50 #define SCLK_TIMER00 90 51 #define SCLK_TIMER01 91 52 #define SCLK_TIMER02 92 53 #define SCLK_TIMER03 93 54 #define SCLK_TIMER04 94 55 #define SCLK_TIMER05 95 56 #define SCLK_TIMER06 96 57 #define SCLK_TIMER07 97 58 #define SCLK_TIMER08 98 59 #define SCLK_TIMER09 99 60 #define SCLK_TIMER10 100 61 #define SCLK_TIMER11 101 62 #define SCLK_MACREF 102 63 #define SCLK_MAC_RX 103 64 #define SCLK_MAC_TX 104 65 #define SCLK_MAC 105 66 #define SCLK_MACREF_OUT 106 67 #define SCLK_VOP0_PWM 107 68 #define SCLK_VOP1_PWM 108 69 #define SCLK_RGA_CORE 109 70 #define SCLK_ISP0 110 71 #define SCLK_ISP1 111 72 #define SCLK_HDMI_CEC 112 73 #define SCLK_HDMI_SFR 113 74 #define SCLK_DP_CORE 114 75 #define SCLK_PVTM_CORE_L 115 76 #define SCLK_PVTM_CORE_B 116 77 #define SCLK_PVTM_GPU 117 78 #define SCLK_PVTM_DDR 118 79 #define SCLK_MIPIDPHY_REF 119 80 #define SCLK_MIPIDPHY_CFG 120 81 #define SCLK_HSICPHY 121 82 #define SCLK_USBPHY480M 122 83 #define SCLK_USB2PHY0_REF 123 84 #define SCLK_USB2PHY1_REF 124 85 #define SCLK_UPHY0_TCPDPHY_REF 125 86 #define SCLK_UPHY0_TCPDCORE 126 87 #define SCLK_UPHY1_TCPDPHY_REF 127 88 #define SCLK_UPHY1_TCPDCORE 128 89 #define SCLK_USB3OTG0_REF 129 90 #define SCLK_USB3OTG1_REF 130 91 #define SCLK_USB3OTG0_SUSPEND 131 92 #define SCLK_USB3OTG1_SUSPEND 132 93 #define SCLK_CRYPTO0 133 94 #define SCLK_CRYPTO1 134 95 #define SCLK_CCI_TRACE 135 96 #define SCLK_CS 136 97 #define SCLK_CIF_OUT 137 98 #define SCLK_PCIEPHY_REF 138 99 #define SCLK_PCIE_CORE 139 100 #define SCLK_M0_PERILP 140 101 #define SCLK_M0_PERILP_DEC 141 102 #define SCLK_CM0S 142 103 #define SCLK_DBG_NOC 143 104 #define SCLK_DBG_PD_CORE_B 144 105 #define SCLK_DBG_PD_CORE_L 145 106 #define SCLK_DFIMON0_TIMER 146 107 #define SCLK_DFIMON1_TIMER 147 108 #define SCLK_INTMEM0 148 109 #define SCLK_INTMEM1 149 110 #define SCLK_INTMEM2 150 111 #define SCLK_INTMEM3 151 112 #define SCLK_INTMEM4 152 113 #define SCLK_INTMEM5 153 114 #define SCLK_SDMMC_DRV 154 115 #define SCLK_SDMMC_SAMPLE 155 116 #define SCLK_SDIO_DRV 156 117 #define SCLK_SDIO_SAMPLE 157 118 #define SCLK_VDU_CORE 158 119 #define SCLK_VDU_CA 159 120 #define SCLK_PCIE_PM 160 121 #define SCLK_SPDIF_REC_DPTX 161 122 #define SCLK_DPHY_PLL 162 123 #define SCLK_DPHY_TX0_CFG 163 124 #define SCLK_DPHY_TX1RX1_CFG 164 125 #define SCLK_DPHY_RX0_CFG 165 126 #define SCLK_RMII_SRC 166 127 #define SCLK_PCIEPHY_REF100M 167 128 #define SCLK_USBPHY0_480M_SRC 168 129 #define SCLK_USBPHY1_480M_SRC 169 130 #define SCLK_DDRC 170 131 #define SCLK_TESTCLKOUT2 171 132 #define SCLK_UART0_SRC 172 133 #define SCLK_UART_SRC 173 134 #define SCLK_I2S0_DIV 174 135 #define SCLK_I2S1_DIV 175 136 #define SCLK_I2S2_DIV 176 137 #define SCLK_SPDIF_DIV 177 138 #define SCLK_TESTCLKOUT1 179 139 #define SCLK_CIF_OUT_SRC 178 140 141 #define DCLK_VOP0 180 142 #define DCLK_VOP1 181 143 #define DCLK_VOP0_DIV 182 144 #define DCLK_VOP1_DIV 183 145 #define DCLK_M0_PERILP 184 146 #define DCLK_VOP0_FRAC 185 147 #define DCLK_VOP1_FRAC 186 148 149 #define FCLK_CM0S 190 150 151 /* aclk gates */ 152 #define ACLK_PERIHP 192 153 #define ACLK_PERIHP_NOC 193 154 #define ACLK_PERILP0 194 155 #define ACLK_PERILP0_NOC 195 156 #define ACLK_PERF_PCIE 196 157 #define ACLK_PCIE 197 158 #define ACLK_INTMEM 198 159 #define ACLK_TZMA 199 160 #define ACLK_DCF 200 161 #define ACLK_CCI 201 162 #define ACLK_CCI_NOC0 202 163 #define ACLK_CCI_NOC1 203 164 #define ACLK_CCI_GRF 204 165 #define ACLK_CENTER 205 166 #define ACLK_CENTER_MAIN_NOC 206 167 #define ACLK_CENTER_PERI_NOC 207 168 #define ACLK_GPU 208 169 #define ACLK_PERF_GPU 209 170 #define ACLK_GPU_GRF 210 171 #define ACLK_DMAC0_PERILP 211 172 #define ACLK_DMAC1_PERILP 212 173 #define ACLK_GMAC 213 174 #define ACLK_GMAC_NOC 214 175 #define ACLK_PERF_GMAC 215 176 #define ACLK_VOP0_NOC 216 177 #define ACLK_VOP0 217 178 #define ACLK_VOP1_NOC 218 179 #define ACLK_VOP1 219 180 #define ACLK_RGA 220 181 #define ACLK_RGA_NOC 221 182 #define ACLK_HDCP 222 183 #define ACLK_HDCP_NOC 223 184 #define ACLK_HDCP22 224 185 #define ACLK_IEP 225 186 #define ACLK_IEP_NOC 226 187 #define ACLK_VIO 227 188 #define ACLK_VIO_NOC 228 189 #define ACLK_ISP0 229 190 #define ACLK_ISP1 230 191 #define ACLK_ISP0_NOC 231 192 #define ACLK_ISP1_NOC 232 193 #define ACLK_ISP0_WRAPPER 233 194 #define ACLK_ISP1_WRAPPER 234 195 #define ACLK_VCODEC 235 196 #define ACLK_VCODEC_NOC 236 197 #define ACLK_VDU 237 198 #define ACLK_VDU_NOC 238 199 #define ACLK_PERI 239 200 #define ACLK_EMMC 240 201 #define ACLK_EMMC_CORE 241 202 #define ACLK_EMMC_NOC 242 203 #define ACLK_EMMC_GRF 243 204 #define ACLK_USB3 244 205 #define ACLK_USB3_NOC 245 206 #define ACLK_USB3OTG0 246 207 #define ACLK_USB3OTG1 247 208 #define ACLK_USB3_RKSOC_AXI_PERF 248 209 #define ACLK_USB3_GRF 249 210 #define ACLK_GIC 250 211 #define ACLK_GIC_NOC 251 212 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 213 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 214 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 215 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 216 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 217 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 218 #define ACLK_ADB400M_PD_CORE_L 258 219 #define ACLK_ADB400M_PD_CORE_B 259 220 #define ACLK_PERF_CORE_L 260 221 #define ACLK_PERF_CORE_B 261 222 #define ACLK_GIC_PRE 262 223 #define ACLK_VOP0_PRE 263 224 #define ACLK_VOP1_PRE 264 225 226 /* pclk gates */ 227 #define PCLK_PERIHP 320 228 #define PCLK_PERIHP_NOC 321 229 #define PCLK_PERILP0 322 230 #define PCLK_PERILP1 323 231 #define PCLK_PERILP1_NOC 324 232 #define PCLK_PERILP_SGRF 325 233 #define PCLK_PERIHP_GRF 326 234 #define PCLK_PCIE 327 235 #define PCLK_SGRF 328 236 #define PCLK_INTR_ARB 329 237 #define PCLK_CENTER_MAIN_NOC 330 238 #define PCLK_CIC 331 239 #define PCLK_COREDBG_B 332 240 #define PCLK_COREDBG_L 333 241 #define PCLK_DBG_CXCS_PD_CORE_B 334 242 #define PCLK_DCF 335 243 #define PCLK_GPIO2 336 244 #define PCLK_GPIO3 337 245 #define PCLK_GPIO4 338 246 #define PCLK_GRF 339 247 #define PCLK_HSICPHY 340 248 #define PCLK_I2C1 341 249 #define PCLK_I2C2 342 250 #define PCLK_I2C3 343 251 #define PCLK_I2C5 344 252 #define PCLK_I2C6 345 253 #define PCLK_I2C7 346 254 #define PCLK_SPI0 347 255 #define PCLK_SPI1 348 256 #define PCLK_SPI2 349 257 #define PCLK_SPI4 350 258 #define PCLK_SPI5 351 259 #define PCLK_UART0 352 260 #define PCLK_UART1 353 261 #define PCLK_UART2 354 262 #define PCLK_UART3 355 263 #define PCLK_TSADC 356 264 #define PCLK_SARADC 357 265 #define PCLK_GMAC 358 266 #define PCLK_GMAC_NOC 359 267 #define PCLK_TIMER0 360 268 #define PCLK_TIMER1 361 269 #define PCLK_EDP 362 270 #define PCLK_EDP_NOC 363 271 #define PCLK_EDP_CTRL 364 272 #define PCLK_VIO 365 273 #define PCLK_VIO_NOC 366 274 #define PCLK_VIO_GRF 367 275 #define PCLK_MIPI_DSI0 368 276 #define PCLK_MIPI_DSI1 369 277 #define PCLK_HDCP 370 278 #define PCLK_HDCP_NOC 371 279 #define PCLK_HDMI_CTRL 372 280 #define PCLK_DP_CTRL 373 281 #define PCLK_HDCP22 374 282 #define PCLK_GASKET 375 283 #define PCLK_DDR 376 284 #define PCLK_DDR_MON 377 285 #define PCLK_DDR_SGRF 378 286 #define PCLK_ISP1_WRAPPER 379 287 #define PCLK_WDT 380 288 #define PCLK_EFUSE1024NS 381 289 #define PCLK_EFUSE1024S 382 290 #define PCLK_PMU_INTR_ARB 383 291 #define PCLK_MAILBOX0 384 292 #define PCLK_USBPHY_MUX_G 385 293 #define PCLK_UPHY0_TCPHY_G 386 294 #define PCLK_UPHY0_TCPD_G 387 295 #define PCLK_UPHY1_TCPHY_G 388 296 #define PCLK_UPHY1_TCPD_G 389 297 #define PCLK_ALIVE 390 298 299 /* hclk gates */ 300 #define HCLK_PERIHP 448 301 #define HCLK_PERILP0 449 302 #define HCLK_PERILP1 450 303 #define HCLK_PERILP0_NOC 451 304 #define HCLK_PERILP1_NOC 452 305 #define HCLK_M0_PERILP 453 306 #define HCLK_M0_PERILP_NOC 454 307 #define HCLK_AHB1TOM 455 308 #define HCLK_HOST0 456 309 #define HCLK_HOST0_ARB 457 310 #define HCLK_HOST1 458 311 #define HCLK_HOST1_ARB 459 312 #define HCLK_HSIC 460 313 #define HCLK_SD 461 314 #define HCLK_SDMMC 462 315 #define HCLK_SDMMC_NOC 463 316 #define HCLK_M_CRYPTO0 464 317 #define HCLK_M_CRYPTO1 465 318 #define HCLK_S_CRYPTO0 466 319 #define HCLK_S_CRYPTO1 467 320 #define HCLK_I2S0_8CH 468 321 #define HCLK_I2S1_8CH 469 322 #define HCLK_I2S2_8CH 470 323 #define HCLK_SPDIF 471 324 #define HCLK_VOP0_NOC 472 325 #define HCLK_VOP0 473 326 #define HCLK_VOP1_NOC 474 327 #define HCLK_VOP1 475 328 #define HCLK_ROM 476 329 #define HCLK_IEP 477 330 #define HCLK_IEP_NOC 478 331 #define HCLK_ISP0 479 332 #define HCLK_ISP1 480 333 #define HCLK_ISP0_NOC 481 334 #define HCLK_ISP1_NOC 482 335 #define HCLK_ISP0_WRAPPER 483 336 #define HCLK_ISP1_WRAPPER 484 337 #define HCLK_RGA 485 338 #define HCLK_RGA_NOC 486 339 #define HCLK_HDCP 487 340 #define HCLK_HDCP_NOC 488 341 #define HCLK_HDCP22 489 342 #define HCLK_VCODEC 490 343 #define HCLK_VCODEC_NOC 491 344 #define HCLK_VDU 492 345 #define HCLK_VDU_NOC 493 346 #define HCLK_SDIO 494 347 #define HCLK_SDIO_NOC 495 348 #define HCLK_SDIOAUDIO_NOC 496 349 350 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 351 352 /* pmu-clocks indices */ 353 354 #define PLL_PPLL 1 355 356 #define SCLK_32K_SUSPEND_PMU 2 357 #define SCLK_SPI3_PMU 3 358 #define SCLK_TIMER12_PMU 4 359 #define SCLK_TIMER13_PMU 5 360 #define SCLK_UART4_PMU 6 361 #define SCLK_PVTM_PMU 7 362 #define SCLK_WIFI_PMU 8 363 #define SCLK_I2C0_PMU 9 364 #define SCLK_I2C4_PMU 10 365 #define SCLK_I2C8_PMU 11 366 #define SCLK_UART4_SRC 12 367 368 #define PCLK_SRC_PMU 19 369 #define PCLK_PMU 20 370 #define PCLK_PMUGRF_PMU 21 371 #define PCLK_INTMEM1_PMU 22 372 #define PCLK_GPIO0_PMU 23 373 #define PCLK_GPIO1_PMU 24 374 #define PCLK_SGRF_PMU 25 375 #define PCLK_NOC_PMU 26 376 #define PCLK_I2C0_PMU 27 377 #define PCLK_I2C4_PMU 28 378 #define PCLK_I2C8_PMU 29 379 #define PCLK_RKPWM_PMU 30 380 #define PCLK_SPI3_PMU 31 381 #define PCLK_TIMER_PMU 32 382 #define PCLK_MAILBOX_PMU 33 383 #define PCLK_UART4_PMU 34 384 #define PCLK_WDT_M0_PMU 35 385 386 #define FCLK_CM0S_SRC_PMU 44 387 #define FCLK_CM0S_PMU 45 388 #define SCLK_CM0S_PMU 46 389 #define HCLK_CM0S_PMU 47 390 #define DCLK_CM0S_PMU 48 391 #define PCLK_INTR_ARB_PMU 49 392 #define HCLK_NOC_PMU 50 393 394 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 395 396 /* soft-reset indices */ 397 398 /* cru_softrst_con0 */ 399 #define SRST_CORE_L0 0 400 #define SRST_CORE_B0 1 401 #define SRST_CORE_PO_L0 2 402 #define SRST_CORE_PO_B0 3 403 #define SRST_L2_L 4 404 #define SRST_L2_B 5 405 #define SRST_ADB_L 6 406 #define SRST_ADB_B 7 407 #define SRST_A_CCI 8 408 #define SRST_A_CCIM0_NOC 9 409 #define SRST_A_CCIM1_NOC 10 410 #define SRST_DBG_NOC 11 411 412 /* cru_softrst_con1 */ 413 #define SRST_CORE_L0_T 16 414 #define SRST_CORE_L1 17 415 #define SRST_CORE_L2 18 416 #define SRST_CORE_L3 19 417 #define SRST_CORE_PO_L0_T 20 418 #define SRST_CORE_PO_L1 21 419 #define SRST_CORE_PO_L2 22 420 #define SRST_CORE_PO_L3 23 421 #define SRST_A_ADB400_GIC2COREL 24 422 #define SRST_A_ADB400_COREL2GIC 25 423 #define SRST_P_DBG_L 26 424 #define SRST_L2_L_T 28 425 #define SRST_ADB_L_T 29 426 #define SRST_A_RKPERF_L 30 427 #define SRST_PVTM_CORE_L 31 428 429 /* cru_softrst_con2 */ 430 #define SRST_CORE_B0_T 32 431 #define SRST_CORE_B1 33 432 #define SRST_CORE_PO_B0_T 36 433 #define SRST_CORE_PO_B1 37 434 #define SRST_A_ADB400_GIC2COREB 40 435 #define SRST_A_ADB400_COREB2GIC 41 436 #define SRST_P_DBG_B 42 437 #define SRST_L2_B_T 44 438 #define SRST_ADB_B_T 45 439 #define SRST_A_RKPERF_B 46 440 #define SRST_PVTM_CORE_B 47 441 442 /* cru_softrst_con3 */ 443 #define SRST_A_CCI_T 50 444 #define SRST_A_CCIM0_NOC_T 51 445 #define SRST_A_CCIM1_NOC_T 52 446 #define SRST_A_ADB400M_PD_CORE_B_T 53 447 #define SRST_A_ADB400M_PD_CORE_L_T 54 448 #define SRST_DBG_NOC_T 55 449 #define SRST_DBG_CXCS 56 450 #define SRST_CCI_TRACE 57 451 #define SRST_P_CCI_GRF 58 452 453 /* cru_softrst_con4 */ 454 #define SRST_A_CENTER_MAIN_NOC 64 455 #define SRST_A_CENTER_PERI_NOC 65 456 #define SRST_P_CENTER_MAIN 66 457 #define SRST_P_DDRMON 67 458 #define SRST_P_CIC 68 459 #define SRST_P_CENTER_SGRF 69 460 #define SRST_DDR0_MSCH 70 461 #define SRST_DDRCFG0_MSCH 71 462 #define SRST_DDR0 72 463 #define SRST_DDRPHY0 73 464 #define SRST_DDR1_MSCH 74 465 #define SRST_DDRCFG1_MSCH 75 466 #define SRST_DDR1 76 467 #define SRST_DDRPHY1 77 468 #define SRST_DDR_CIC 78 469 #define SRST_PVTM_DDR 79 470 471 /* cru_softrst_con5 */ 472 #define SRST_A_VCODEC_NOC 80 473 #define SRST_A_VCODEC 81 474 #define SRST_H_VCODEC_NOC 82 475 #define SRST_H_VCODEC 83 476 #define SRST_A_VDU_NOC 88 477 #define SRST_A_VDU 89 478 #define SRST_H_VDU_NOC 90 479 #define SRST_H_VDU 91 480 #define SRST_VDU_CORE 92 481 #define SRST_VDU_CA 93 482 483 /* cru_softrst_con6 */ 484 #define SRST_A_IEP_NOC 96 485 #define SRST_A_VOP_IEP 97 486 #define SRST_A_IEP 98 487 #define SRST_H_IEP_NOC 99 488 #define SRST_H_IEP 100 489 #define SRST_A_RGA_NOC 102 490 #define SRST_A_RGA 103 491 #define SRST_H_RGA_NOC 104 492 #define SRST_H_RGA 105 493 #define SRST_RGA_CORE 106 494 #define SRST_EMMC_NOC 108 495 #define SRST_EMMC 109 496 #define SRST_EMMC_GRF 110 497 498 /* cru_softrst_con7 */ 499 #define SRST_A_PERIHP_NOC 112 500 #define SRST_P_PERIHP_GRF 113 501 #define SRST_H_PERIHP_NOC 114 502 #define SRST_USBHOST0 115 503 #define SRST_HOSTC0_AUX 116 504 #define SRST_HOST0_ARB 117 505 #define SRST_USBHOST1 118 506 #define SRST_HOSTC1_AUX 119 507 #define SRST_HOST1_ARB 120 508 #define SRST_SDIO0 121 509 #define SRST_SDMMC 122 510 #define SRST_HSIC 123 511 #define SRST_HSIC_AUX 124 512 #define SRST_AHB1TOM 125 513 #define SRST_P_PERIHP_NOC 126 514 #define SRST_HSICPHY 127 515 516 /* cru_softrst_con8 */ 517 #define SRST_A_PCIE 128 518 #define SRST_P_PCIE 129 519 #define SRST_PCIE_CORE 130 520 #define SRST_PCIE_MGMT 131 521 #define SRST_PCIE_MGMT_STICKY 132 522 #define SRST_PCIE_PIPE 133 523 #define SRST_PCIE_PM 134 524 #define SRST_PCIEPHY 135 525 #define SRST_A_GMAC_NOC 136 526 #define SRST_A_GMAC 137 527 #define SRST_P_GMAC_NOC 138 528 #define SRST_P_GMAC_GRF 140 529 #define SRST_HSICPHY_POR 142 530 #define SRST_HSICPHY_UTMI 143 531 532 /* cru_softrst_con9 */ 533 #define SRST_USB2PHY0_POR 144 534 #define SRST_USB2PHY0_UTMI_PORT0 145 535 #define SRST_USB2PHY0_UTMI_PORT1 146 536 #define SRST_USB2PHY0_EHCIPHY 147 537 #define SRST_UPHY0_PIPE_L00 148 538 #define SRST_UPHY0 149 539 #define SRST_UPHY0_TCPDPWRUP 150 540 #define SRST_USB2PHY1_POR 152 541 #define SRST_USB2PHY1_UTMI_PORT0 153 542 #define SRST_USB2PHY1_UTMI_PORT1 154 543 #define SRST_USB2PHY1_EHCIPHY 155 544 #define SRST_UPHY1_PIPE_L00 156 545 #define SRST_UPHY1 157 546 #define SRST_UPHY1_TCPDPWRUP 158 547 548 /* cru_softrst_con10 */ 549 #define SRST_A_PERILP0_NOC 160 550 #define SRST_A_DCF 161 551 #define SRST_GIC500 162 552 #define SRST_DMAC0_PERILP0 163 553 #define SRST_DMAC1_PERILP0 164 554 #define SRST_TZMA 165 555 #define SRST_INTMEM 166 556 #define SRST_ADB400_MST0 167 557 #define SRST_ADB400_MST1 168 558 #define SRST_ADB400_SLV0 169 559 #define SRST_ADB400_SLV1 170 560 #define SRST_H_PERILP0 171 561 #define SRST_H_PERILP0_NOC 172 562 #define SRST_ROM 173 563 #define SRST_CRYPTO_S 174 564 #define SRST_CRYPTO_M 175 565 566 /* cru_softrst_con11 */ 567 #define SRST_P_DCF 176 568 #define SRST_CM0S_NOC 177 569 #define SRST_CM0S 178 570 #define SRST_CM0S_DBG 179 571 #define SRST_CM0S_PO 180 572 #define SRST_CRYPTO 181 573 #define SRST_P_PERILP1_SGRF 182 574 #define SRST_P_PERILP1_GRF 183 575 #define SRST_CRYPTO1_S 184 576 #define SRST_CRYPTO1_M 185 577 #define SRST_CRYPTO1 186 578 #define SRST_GIC_NOC 188 579 #define SRST_SD_NOC 189 580 #define SRST_SDIOAUDIO_BRG 190 581 582 /* cru_softrst_con12 */ 583 #define SRST_H_PERILP1 192 584 #define SRST_H_PERILP1_NOC 193 585 #define SRST_H_I2S0_8CH 194 586 #define SRST_H_I2S1_8CH 195 587 #define SRST_H_I2S2_8CH 196 588 #define SRST_H_SPDIF_8CH 197 589 #define SRST_P_PERILP1_NOC 198 590 #define SRST_P_EFUSE_1024 199 591 #define SRST_P_EFUSE_1024S 200 592 #define SRST_P_I2C0 201 593 #define SRST_P_I2C1 202 594 #define SRST_P_I2C2 203 595 #define SRST_P_I2C3 204 596 #define SRST_P_I2C4 205 597 #define SRST_P_I2C5 206 598 #define SRST_P_MAILBOX0 207 599 600 /* cru_softrst_con13 */ 601 #define SRST_P_UART0 208 602 #define SRST_P_UART1 209 603 #define SRST_P_UART2 210 604 #define SRST_P_UART3 211 605 #define SRST_P_SARADC 212 606 #define SRST_P_TSADC 213 607 #define SRST_P_SPI0 214 608 #define SRST_P_SPI1 215 609 #define SRST_P_SPI2 216 610 #define SRST_P_SPI4 217 611 #define SRST_P_SPI5 218 612 #define SRST_SPI0 219 613 #define SRST_SPI1 220 614 #define SRST_SPI2 221 615 #define SRST_SPI4 222 616 #define SRST_SPI5 223 617 618 /* cru_softrst_con14 */ 619 #define SRST_I2S0_8CH 224 620 #define SRST_I2S1_8CH 225 621 #define SRST_I2S2_8CH 226 622 #define SRST_SPDIF_8CH 227 623 #define SRST_UART0 228 624 #define SRST_UART1 229 625 #define SRST_UART2 230 626 #define SRST_UART3 231 627 #define SRST_TSADC 232 628 #define SRST_I2C0 233 629 #define SRST_I2C1 234 630 #define SRST_I2C2 235 631 #define SRST_I2C3 236 632 #define SRST_I2C4 237 633 #define SRST_I2C5 238 634 #define SRST_SDIOAUDIO_NOC 239 635 636 /* cru_softrst_con15 */ 637 #define SRST_A_VIO_NOC 240 638 #define SRST_A_HDCP_NOC 241 639 #define SRST_A_HDCP 242 640 #define SRST_H_HDCP_NOC 243 641 #define SRST_H_HDCP 244 642 #define SRST_P_HDCP_NOC 245 643 #define SRST_P_HDCP 246 644 #define SRST_P_HDMI_CTRL 247 645 #define SRST_P_DP_CTRL 248 646 #define SRST_S_DP_CTRL 249 647 #define SRST_C_DP_CTRL 250 648 #define SRST_P_MIPI_DSI0 251 649 #define SRST_P_MIPI_DSI1 252 650 #define SRST_DP_CORE 253 651 #define SRST_DP_I2S 254 652 653 /* cru_softrst_con16 */ 654 #define SRST_GASKET 256 655 #define SRST_VIO_GRF 258 656 #define SRST_DPTX_SPDIF_REC 259 657 #define SRST_HDMI_CTRL 260 658 #define SRST_HDCP_CTRL 261 659 #define SRST_A_ISP0_NOC 262 660 #define SRST_A_ISP1_NOC 263 661 #define SRST_H_ISP0_NOC 266 662 #define SRST_H_ISP1_NOC 267 663 #define SRST_H_ISP0 268 664 #define SRST_H_ISP1 269 665 #define SRST_ISP0 270 666 #define SRST_ISP1 271 667 668 /* cru_softrst_con17 */ 669 #define SRST_A_VOP0_NOC 272 670 #define SRST_A_VOP1_NOC 273 671 #define SRST_A_VOP0 274 672 #define SRST_A_VOP1 275 673 #define SRST_H_VOP0_NOC 276 674 #define SRST_H_VOP1_NOC 277 675 #define SRST_H_VOP0 278 676 #define SRST_H_VOP1 279 677 #define SRST_D_VOP0 280 678 #define SRST_D_VOP1 281 679 #define SRST_VOP0_PWM 282 680 #define SRST_VOP1_PWM 283 681 #define SRST_P_EDP_NOC 284 682 #define SRST_P_EDP_CTRL 285 683 684 /* cru_softrst_con18 */ 685 #define SRST_A_GPU 288 686 #define SRST_A_GPU_NOC 289 687 #define SRST_A_GPU_GRF 290 688 #define SRST_PVTM_GPU 291 689 #define SRST_A_USB3_NOC 292 690 #define SRST_A_USB3_OTG0 293 691 #define SRST_A_USB3_OTG1 294 692 #define SRST_A_USB3_GRF 295 693 #define SRST_PMU 296 694 695 /* cru_softrst_con19 */ 696 #define SRST_P_TIMER0_5 304 697 #define SRST_TIMER0 305 698 #define SRST_TIMER1 306 699 #define SRST_TIMER2 307 700 #define SRST_TIMER3 308 701 #define SRST_TIMER4 309 702 #define SRST_TIMER5 310 703 #define SRST_P_TIMER6_11 311 704 #define SRST_TIMER6 312 705 #define SRST_TIMER7 313 706 #define SRST_TIMER8 314 707 #define SRST_TIMER9 315 708 #define SRST_TIMER10 316 709 #define SRST_TIMER11 317 710 #define SRST_P_INTR_ARB_PMU 318 711 #define SRST_P_ALIVE_SGRF 319 712 713 /* cru_softrst_con20 */ 714 #define SRST_P_GPIO2 320 715 #define SRST_P_GPIO3 321 716 #define SRST_P_GPIO4 322 717 #define SRST_P_GRF 323 718 #define SRST_P_ALIVE_NOC 324 719 #define SRST_P_WDT0 325 720 #define SRST_P_WDT1 326 721 #define SRST_P_INTR_ARB 327 722 #define SRST_P_UPHY0_DPTX 328 723 #define SRST_P_UPHY0_APB 330 724 #define SRST_P_UPHY0_TCPHY 332 725 #define SRST_P_UPHY1_TCPHY 333 726 #define SRST_P_UPHY0_TCPDCTRL 334 727 #define SRST_P_UPHY1_TCPDCTRL 335 728 729 /* pmu soft-reset indices */ 730 731 /* pmu_cru_softrst_con0 */ 732 #define SRST_P_NOC 0 733 #define SRST_P_INTMEM 1 734 #define SRST_H_CM0S 2 735 #define SRST_H_CM0S_NOC 3 736 #define SRST_DBG_CM0S 4 737 #define SRST_PO_CM0S 5 738 #define SRST_P_SPI3 6 739 #define SRST_SPI3 7 740 #define SRST_P_TIMER_0_1 8 741 #define SRST_P_TIMER_0 9 742 #define SRST_P_TIMER_1 10 743 #define SRST_P_UART4 11 744 #define SRST_UART4 12 745 #define SRST_P_WDT 13 746 747 /* pmu_cru_softrst_con1 */ 748 #define SRST_P_I2C6 16 749 #define SRST_P_I2C7 17 750 #define SRST_P_I2C8 18 751 #define SRST_P_MAILBOX 19 752 #define SRST_P_RKPWM 20 753 #define SRST_P_PMUGRF 21 754 #define SRST_P_SGRF 22 755 #define SRST_P_GPIO0 23 756 #define SRST_P_GPIO1 24 757 #define SRST_P_CRU 25 758 #define SRST_P_INTR 26 759 #define SRST_PVTM 27 760 #define SRST_I2C6 28 761 #define SRST_I2C7 29 762 #define SRST_I2C8 30 763 764 #endif 765