1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 9 10 #define RK3399_TWO_PLL_FOR_VOP 11 12 /* core clocks */ 13 #define PLL_APLLL 1 14 #define PLL_APLLB 2 15 #define PLL_DPLL 3 16 #define PLL_CPLL 4 17 #define PLL_GPLL 5 18 #define PLL_NPLL 6 19 #define PLL_VPLL 7 20 #define ARMCLKL 8 21 #define ARMCLKB 9 22 23 /* sclk gates (special clocks) */ 24 #define SCLK_I2C1 65 25 #define SCLK_I2C2 66 26 #define SCLK_I2C3 67 27 #define SCLK_I2C5 68 28 #define SCLK_I2C6 69 29 #define SCLK_I2C7 70 30 #define SCLK_SPI0 71 31 #define SCLK_SPI1 72 32 #define SCLK_SPI2 73 33 #define SCLK_SPI4 74 34 #define SCLK_SPI5 75 35 #define SCLK_SDMMC 76 36 #define SCLK_SDIO 77 37 #define SCLK_EMMC 78 38 #define SCLK_TSADC 79 39 #define SCLK_SARADC 80 40 #define SCLK_UART0 81 41 #define SCLK_UART1 82 42 #define SCLK_UART2 83 43 #define SCLK_UART3 84 44 #define SCLK_SPDIF_8CH 85 45 #define SCLK_I2S0_8CH 86 46 #define SCLK_I2S1_8CH 87 47 #define SCLK_I2S2_8CH 88 48 #define SCLK_I2S_8CH_OUT 89 49 #define SCLK_TIMER00 90 50 #define SCLK_TIMER01 91 51 #define SCLK_TIMER02 92 52 #define SCLK_TIMER03 93 53 #define SCLK_TIMER04 94 54 #define SCLK_TIMER05 95 55 #define SCLK_TIMER06 96 56 #define SCLK_TIMER07 97 57 #define SCLK_TIMER08 98 58 #define SCLK_TIMER09 99 59 #define SCLK_TIMER10 100 60 #define SCLK_TIMER11 101 61 #define SCLK_MACREF 102 62 #define SCLK_MAC_RX 103 63 #define SCLK_MAC_TX 104 64 #define SCLK_MAC 105 65 #define SCLK_MACREF_OUT 106 66 #define SCLK_VOP0_PWM 107 67 #define SCLK_VOP1_PWM 108 68 #define SCLK_RGA_CORE 109 69 #define SCLK_ISP0 110 70 #define SCLK_ISP1 111 71 #define SCLK_HDMI_CEC 112 72 #define SCLK_HDMI_SFR 113 73 #define SCLK_DP_CORE 114 74 #define SCLK_PVTM_CORE_L 115 75 #define SCLK_PVTM_CORE_B 116 76 #define SCLK_PVTM_GPU 117 77 #define SCLK_PVTM_DDR 118 78 #define SCLK_MIPIDPHY_REF 119 79 #define SCLK_MIPIDPHY_CFG 120 80 #define SCLK_HSICPHY 121 81 #define SCLK_USBPHY480M 122 82 #define SCLK_USB2PHY0_REF 123 83 #define SCLK_USB2PHY1_REF 124 84 #define SCLK_UPHY0_TCPDPHY_REF 125 85 #define SCLK_UPHY0_TCPDCORE 126 86 #define SCLK_UPHY1_TCPDPHY_REF 127 87 #define SCLK_UPHY1_TCPDCORE 128 88 #define SCLK_USB3OTG0_REF 129 89 #define SCLK_USB3OTG1_REF 130 90 #define SCLK_USB3OTG0_SUSPEND 131 91 #define SCLK_USB3OTG1_SUSPEND 132 92 #define SCLK_CRYPTO0 133 93 #define SCLK_CRYPTO1 134 94 #define SCLK_CCI_TRACE 135 95 #define SCLK_CS 136 96 #define SCLK_CIF_OUT 137 97 #define SCLK_PCIEPHY_REF 138 98 #define SCLK_PCIE_CORE 139 99 #define SCLK_M0_PERILP 140 100 #define SCLK_M0_PERILP_DEC 141 101 #define SCLK_CM0S 142 102 #define SCLK_DBG_NOC 143 103 #define SCLK_DBG_PD_CORE_B 144 104 #define SCLK_DBG_PD_CORE_L 145 105 #define SCLK_DFIMON0_TIMER 146 106 #define SCLK_DFIMON1_TIMER 147 107 #define SCLK_INTMEM0 148 108 #define SCLK_INTMEM1 149 109 #define SCLK_INTMEM2 150 110 #define SCLK_INTMEM3 151 111 #define SCLK_INTMEM4 152 112 #define SCLK_INTMEM5 153 113 #define SCLK_SDMMC_DRV 154 114 #define SCLK_SDMMC_SAMPLE 155 115 #define SCLK_SDIO_DRV 156 116 #define SCLK_SDIO_SAMPLE 157 117 #define SCLK_VDU_CORE 158 118 #define SCLK_VDU_CA 159 119 #define SCLK_PCIE_PM 160 120 #define SCLK_SPDIF_REC_DPTX 161 121 #define SCLK_DPHY_PLL 162 122 #define SCLK_DPHY_TX0_CFG 163 123 #define SCLK_DPHY_TX1RX1_CFG 164 124 #define SCLK_DPHY_RX0_CFG 165 125 #define SCLK_RMII_SRC 166 126 #define SCLK_PCIEPHY_REF100M 167 127 #define SCLK_USBPHY0_480M_SRC 168 128 #define SCLK_USBPHY1_480M_SRC 169 129 #define SCLK_DDRCLK 170 130 #define SCLK_TESTOUT2 171 131 132 #define DCLK_VOP0 180 133 #define DCLK_VOP1 181 134 #define DCLK_VOP0_DIV 182 135 #define DCLK_VOP1_DIV 183 136 #define DCLK_M0_PERILP 184 137 138 #define FCLK_CM0S 190 139 140 /* aclk gates */ 141 #define ACLK_PERIHP 192 142 #define ACLK_PERIHP_NOC 193 143 #define ACLK_PERILP0 194 144 #define ACLK_PERILP0_NOC 195 145 #define ACLK_PERF_PCIE 196 146 #define ACLK_PCIE 197 147 #define ACLK_INTMEM 198 148 #define ACLK_TZMA 199 149 #define ACLK_DCF 200 150 #define ACLK_CCI 201 151 #define ACLK_CCI_NOC0 202 152 #define ACLK_CCI_NOC1 203 153 #define ACLK_CCI_GRF 204 154 #define ACLK_CENTER 205 155 #define ACLK_CENTER_MAIN_NOC 206 156 #define ACLK_CENTER_PERI_NOC 207 157 #define ACLK_GPU 208 158 #define ACLK_PERF_GPU 209 159 #define ACLK_GPU_GRF 210 160 #define ACLK_DMAC0_PERILP 211 161 #define ACLK_DMAC1_PERILP 212 162 #define ACLK_GMAC 213 163 #define ACLK_GMAC_NOC 214 164 #define ACLK_PERF_GMAC 215 165 #define ACLK_VOP0_NOC 216 166 #define ACLK_VOP0 217 167 #define ACLK_VOP1_NOC 218 168 #define ACLK_VOP1 219 169 #define ACLK_RGA 220 170 #define ACLK_RGA_NOC 221 171 #define ACLK_HDCP 222 172 #define ACLK_HDCP_NOC 223 173 #define ACLK_HDCP22 224 174 #define ACLK_IEP 225 175 #define ACLK_IEP_NOC 226 176 #define ACLK_VIO 227 177 #define ACLK_VIO_NOC 228 178 #define ACLK_ISP0 229 179 #define ACLK_ISP1 230 180 #define ACLK_ISP0_NOC 231 181 #define ACLK_ISP1_NOC 232 182 #define ACLK_ISP0_WRAPPER 233 183 #define ACLK_ISP1_WRAPPER 234 184 #define ACLK_VCODEC 235 185 #define ACLK_VCODEC_NOC 236 186 #define ACLK_VDU 237 187 #define ACLK_VDU_NOC 238 188 #define ACLK_PERI 239 189 #define ACLK_EMMC 240 190 #define ACLK_EMMC_CORE 241 191 #define ACLK_EMMC_NOC 242 192 #define ACLK_EMMC_GRF 243 193 #define ACLK_USB3 244 194 #define ACLK_USB3_NOC 245 195 #define ACLK_USB3OTG0 246 196 #define ACLK_USB3OTG1 247 197 #define ACLK_USB3_RKSOC_AXI_PERF 248 198 #define ACLK_USB3_GRF 249 199 #define ACLK_GIC 250 200 #define ACLK_GIC_NOC 251 201 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 202 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 203 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 204 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 205 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 206 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 207 #define ACLK_ADB400M_PD_CORE_L 258 208 #define ACLK_ADB400M_PD_CORE_B 259 209 #define ACLK_PERF_CORE_L 260 210 #define ACLK_PERF_CORE_B 261 211 #define ACLK_GIC_PRE 262 212 #define ACLK_VOP0_PRE 263 213 #define ACLK_VOP1_PRE 264 214 215 /* pclk gates */ 216 #define PCLK_PERIHP 320 217 #define PCLK_PERIHP_NOC 321 218 #define PCLK_PERILP0 322 219 #define PCLK_PERILP1 323 220 #define PCLK_PERILP1_NOC 324 221 #define PCLK_PERILP_SGRF 325 222 #define PCLK_PERIHP_GRF 326 223 #define PCLK_PCIE 327 224 #define PCLK_SGRF 328 225 #define PCLK_INTR_ARB 329 226 #define PCLK_CENTER_MAIN_NOC 330 227 #define PCLK_CIC 331 228 #define PCLK_COREDBG_B 332 229 #define PCLK_COREDBG_L 333 230 #define PCLK_DBG_CXCS_PD_CORE_B 334 231 #define PCLK_DCF 335 232 #define PCLK_GPIO2 336 233 #define PCLK_GPIO3 337 234 #define PCLK_GPIO4 338 235 #define PCLK_GRF 339 236 #define PCLK_HSICPHY 340 237 #define PCLK_I2C1 341 238 #define PCLK_I2C2 342 239 #define PCLK_I2C3 343 240 #define PCLK_I2C5 344 241 #define PCLK_I2C6 345 242 #define PCLK_I2C7 346 243 #define PCLK_SPI0 347 244 #define PCLK_SPI1 348 245 #define PCLK_SPI2 349 246 #define PCLK_SPI4 350 247 #define PCLK_SPI5 351 248 #define PCLK_UART0 352 249 #define PCLK_UART1 353 250 #define PCLK_UART2 354 251 #define PCLK_UART3 355 252 #define PCLK_TSADC 356 253 #define PCLK_SARADC 357 254 #define PCLK_GMAC 358 255 #define PCLK_GMAC_NOC 359 256 #define PCLK_TIMER0 360 257 #define PCLK_TIMER1 361 258 #define PCLK_EDP 362 259 #define PCLK_EDP_NOC 363 260 #define PCLK_EDP_CTRL 364 261 #define PCLK_VIO 365 262 #define PCLK_VIO_NOC 366 263 #define PCLK_VIO_GRF 367 264 #define PCLK_MIPI_DSI0 368 265 #define PCLK_MIPI_DSI1 369 266 #define PCLK_HDCP 370 267 #define PCLK_HDCP_NOC 371 268 #define PCLK_HDMI_CTRL 372 269 #define PCLK_DP_CTRL 373 270 #define PCLK_HDCP22 374 271 #define PCLK_GASKET 375 272 #define PCLK_DDR 376 273 #define PCLK_DDR_MON 377 274 #define PCLK_DDR_SGRF 378 275 #define PCLK_ISP1_WRAPPER 379 276 #define PCLK_WDT 380 277 #define PCLK_EFUSE1024NS 381 278 #define PCLK_EFUSE1024S 382 279 #define PCLK_PMU_INTR_ARB 383 280 #define PCLK_MAILBOX0 384 281 #define PCLK_USBPHY_MUX_G 385 282 #define PCLK_UPHY0_TCPHY_G 386 283 #define PCLK_UPHY0_TCPD_G 387 284 #define PCLK_UPHY1_TCPHY_G 388 285 #define PCLK_UPHY1_TCPD_G 389 286 #define PCLK_ALIVE 390 287 288 /* hclk gates */ 289 #define HCLK_PERIHP 448 290 #define HCLK_PERILP0 449 291 #define HCLK_PERILP1 450 292 #define HCLK_PERILP0_NOC 451 293 #define HCLK_PERILP1_NOC 452 294 #define HCLK_M0_PERILP 453 295 #define HCLK_M0_PERILP_NOC 454 296 #define HCLK_AHB1TOM 455 297 #define HCLK_HOST0 456 298 #define HCLK_HOST0_ARB 457 299 #define HCLK_HOST1 458 300 #define HCLK_HOST1_ARB 459 301 #define HCLK_HSIC 460 302 #define HCLK_SD 461 303 #define HCLK_SDMMC 462 304 #define HCLK_SDMMC_NOC 463 305 #define HCLK_M_CRYPTO0 464 306 #define HCLK_M_CRYPTO1 465 307 #define HCLK_S_CRYPTO0 466 308 #define HCLK_S_CRYPTO1 467 309 #define HCLK_I2S0_8CH 468 310 #define HCLK_I2S1_8CH 469 311 #define HCLK_I2S2_8CH 470 312 #define HCLK_SPDIF 471 313 #define HCLK_VOP0_NOC 472 314 #define HCLK_VOP0 473 315 #define HCLK_VOP1_NOC 474 316 #define HCLK_VOP1 475 317 #define HCLK_ROM 476 318 #define HCLK_IEP 477 319 #define HCLK_IEP_NOC 478 320 #define HCLK_ISP0 479 321 #define HCLK_ISP1 480 322 #define HCLK_ISP0_NOC 481 323 #define HCLK_ISP1_NOC 482 324 #define HCLK_ISP0_WRAPPER 483 325 #define HCLK_ISP1_WRAPPER 484 326 #define HCLK_RGA 485 327 #define HCLK_RGA_NOC 486 328 #define HCLK_HDCP 487 329 #define HCLK_HDCP_NOC 488 330 #define HCLK_HDCP22 489 331 #define HCLK_VCODEC 490 332 #define HCLK_VCODEC_NOC 491 333 #define HCLK_VDU 492 334 #define HCLK_VDU_NOC 493 335 #define HCLK_SDIO 494 336 #define HCLK_SDIO_NOC 495 337 #define HCLK_SDIOAUDIO_NOC 496 338 339 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 340 341 /* pmu-clocks indices */ 342 343 #define PLL_PPLL 1 344 345 #define SCLK_32K_SUSPEND_PMU 2 346 #define SCLK_SPI3_PMU 3 347 #define SCLK_TIMER12_PMU 4 348 #define SCLK_TIMER13_PMU 5 349 #define SCLK_UART4_PMU 6 350 #define SCLK_PVTM_PMU 7 351 #define SCLK_WIFI_PMU 8 352 #define SCLK_I2C0_PMU 9 353 #define SCLK_I2C4_PMU 10 354 #define SCLK_I2C8_PMU 11 355 356 #define PCLK_SRC_PMU 19 357 #define PCLK_PMU 20 358 #define PCLK_PMUGRF_PMU 21 359 #define PCLK_INTMEM1_PMU 22 360 #define PCLK_GPIO0_PMU 23 361 #define PCLK_GPIO1_PMU 24 362 #define PCLK_SGRF_PMU 25 363 #define PCLK_NOC_PMU 26 364 #define PCLK_I2C0_PMU 27 365 #define PCLK_I2C4_PMU 28 366 #define PCLK_I2C8_PMU 29 367 #define PCLK_RKPWM_PMU 30 368 #define PCLK_SPI3_PMU 31 369 #define PCLK_TIMER_PMU 32 370 #define PCLK_MAILBOX_PMU 33 371 #define PCLK_UART4_PMU 34 372 #define PCLK_WDT_M0_PMU 35 373 374 #define FCLK_CM0S_SRC_PMU 44 375 #define FCLK_CM0S_PMU 45 376 #define SCLK_CM0S_PMU 46 377 #define HCLK_CM0S_PMU 47 378 #define DCLK_CM0S_PMU 48 379 #define PCLK_INTR_ARB_PMU 49 380 #define HCLK_NOC_PMU 50 381 382 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 383 384 /* soft-reset indices */ 385 386 /* cru_softrst_con0 */ 387 #define SRST_CORE_L0 0 388 #define SRST_CORE_B0 1 389 #define SRST_CORE_PO_L0 2 390 #define SRST_CORE_PO_B0 3 391 #define SRST_L2_L 4 392 #define SRST_L2_B 5 393 #define SRST_ADB_L 6 394 #define SRST_ADB_B 7 395 #define SRST_A_CCI 8 396 #define SRST_A_CCIM0_NOC 9 397 #define SRST_A_CCIM1_NOC 10 398 #define SRST_DBG_NOC 11 399 400 /* cru_softrst_con1 */ 401 #define SRST_CORE_L0_T 16 402 #define SRST_CORE_L1 17 403 #define SRST_CORE_L2 18 404 #define SRST_CORE_L3 19 405 #define SRST_CORE_PO_L0_T 20 406 #define SRST_CORE_PO_L1 21 407 #define SRST_CORE_PO_L2 22 408 #define SRST_CORE_PO_L3 23 409 #define SRST_A_ADB400_GIC2COREL 24 410 #define SRST_A_ADB400_COREL2GIC 25 411 #define SRST_P_DBG_L 26 412 #define SRST_L2_L_T 28 413 #define SRST_ADB_L_T 29 414 #define SRST_A_RKPERF_L 30 415 #define SRST_PVTM_CORE_L 31 416 417 /* cru_softrst_con2 */ 418 #define SRST_CORE_B0_T 32 419 #define SRST_CORE_B1 33 420 #define SRST_CORE_PO_B0_T 36 421 #define SRST_CORE_PO_B1 37 422 #define SRST_A_ADB400_GIC2COREB 40 423 #define SRST_A_ADB400_COREB2GIC 41 424 #define SRST_P_DBG_B 42 425 #define SRST_L2_B_T 43 426 #define SRST_ADB_B_T 45 427 #define SRST_A_RKPERF_B 46 428 #define SRST_PVTM_CORE_B 47 429 430 /* cru_softrst_con3 */ 431 #define SRST_A_CCI_T 50 432 #define SRST_A_CCIM0_NOC_T 51 433 #define SRST_A_CCIM1_NOC_T 52 434 #define SRST_A_ADB400M_PD_CORE_B_T 53 435 #define SRST_A_ADB400M_PD_CORE_L_T 54 436 #define SRST_DBG_NOC_T 55 437 #define SRST_DBG_CXCS 56 438 #define SRST_CCI_TRACE 57 439 #define SRST_P_CCI_GRF 58 440 441 /* cru_softrst_con4 */ 442 #define SRST_A_CENTER_MAIN_NOC 64 443 #define SRST_A_CENTER_PERI_NOC 65 444 #define SRST_P_CENTER_MAIN 66 445 #define SRST_P_DDRMON 67 446 #define SRST_P_CIC 68 447 #define SRST_P_CENTER_SGRF 69 448 #define SRST_DDR0_MSCH 70 449 #define SRST_DDRCFG0_MSCH 71 450 #define SRST_DDR0 72 451 #define SRST_DDRPHY0 73 452 #define SRST_DDR1_MSCH 74 453 #define SRST_DDRCFG1_MSCH 75 454 #define SRST_DDR1 76 455 #define SRST_DDRPHY1 77 456 #define SRST_DDR_CIC 78 457 #define SRST_PVTM_DDR 79 458 459 /* cru_softrst_con5 */ 460 #define SRST_A_VCODEC_NOC 80 461 #define SRST_A_VCODEC 81 462 #define SRST_H_VCODEC_NOC 82 463 #define SRST_H_VCODEC 83 464 #define SRST_A_VDU_NOC 88 465 #define SRST_A_VDU 89 466 #define SRST_H_VDU_NOC 90 467 #define SRST_H_VDU 91 468 #define SRST_VDU_CORE 92 469 #define SRST_VDU_CA 93 470 471 /* cru_softrst_con6 */ 472 #define SRST_A_IEP_NOC 96 473 #define SRST_A_VOP_IEP 97 474 #define SRST_A_IEP 98 475 #define SRST_H_IEP_NOC 99 476 #define SRST_H_IEP 100 477 #define SRST_A_RGA_NOC 102 478 #define SRST_A_RGA 103 479 #define SRST_H_RGA_NOC 104 480 #define SRST_H_RGA 105 481 #define SRST_RGA_CORE 106 482 #define SRST_EMMC_NOC 108 483 #define SRST_EMMC 109 484 #define SRST_EMMC_GRF 110 485 486 /* cru_softrst_con7 */ 487 #define SRST_A_PERIHP_NOC 112 488 #define SRST_P_PERIHP_GRF 113 489 #define SRST_H_PERIHP_NOC 114 490 #define SRST_USBHOST0 115 491 #define SRST_HOSTC0_AUX 116 492 #define SRST_HOST0_ARB 117 493 #define SRST_USBHOST1 118 494 #define SRST_HOSTC1_AUX 119 495 #define SRST_HOST1_ARB 120 496 #define SRST_SDIO0 121 497 #define SRST_SDMMC 122 498 #define SRST_HSIC 123 499 #define SRST_HSIC_AUX 124 500 #define SRST_AHB1TOM 125 501 #define SRST_P_PERIHP_NOC 126 502 #define SRST_HSICPHY 127 503 504 /* cru_softrst_con8 */ 505 #define SRST_A_PCIE 128 506 #define SRST_P_PCIE 129 507 #define SRST_PCIE_CORE 130 508 #define SRST_PCIE_MGMT 131 509 #define SRST_PCIE_MGMT_STICKY 132 510 #define SRST_PCIE_PIPE 133 511 #define SRST_PCIE_PM 134 512 #define SRST_PCIEPHY 135 513 #define SRST_A_GMAC_NOC 136 514 #define SRST_A_GMAC 137 515 #define SRST_P_GMAC_NOC 138 516 #define SRST_P_GMAC_GRF 140 517 #define SRST_HSICPHY_POR 142 518 #define SRST_HSICPHY_UTMI 143 519 520 /* cru_softrst_con9 */ 521 #define SRST_USB2PHY0_POR 144 522 #define SRST_USB2PHY0_UTMI_PORT0 145 523 #define SRST_USB2PHY0_UTMI_PORT1 146 524 #define SRST_USB2PHY0_EHCIPHY 147 525 #define SRST_UPHY0_PIPE_L00 148 526 #define SRST_UPHY0 149 527 #define SRST_UPHY0_TCPDPWRUP 150 528 #define SRST_USB2PHY1_POR 152 529 #define SRST_USB2PHY1_UTMI_PORT0 153 530 #define SRST_USB2PHY1_UTMI_PORT1 154 531 #define SRST_USB2PHY1_EHCIPHY 155 532 #define SRST_UPHY1_PIPE_L00 156 533 #define SRST_UPHY1 157 534 #define SRST_UPHY1_TCPDPWRUP 158 535 536 /* cru_softrst_con10 */ 537 #define SRST_A_PERILP0_NOC 160 538 #define SRST_A_DCF 161 539 #define SRST_GIC500 162 540 #define SRST_DMAC0_PERILP0 163 541 #define SRST_DMAC1_PERILP0 164 542 #define SRST_TZMA 165 543 #define SRST_INTMEM 166 544 #define SRST_ADB400_MST0 167 545 #define SRST_ADB400_MST1 168 546 #define SRST_ADB400_SLV0 169 547 #define SRST_ADB400_SLV1 170 548 #define SRST_H_PERILP0 171 549 #define SRST_H_PERILP0_NOC 172 550 #define SRST_ROM 173 551 #define SRST_CRYPTO_S 174 552 #define SRST_CRYPTO_M 175 553 554 /* cru_softrst_con11 */ 555 #define SRST_P_DCF 176 556 #define SRST_CM0S_NOC 177 557 #define SRST_CM0S 178 558 #define SRST_CM0S_DBG 179 559 #define SRST_CM0S_PO 180 560 #define SRST_CRYPTO 181 561 #define SRST_P_PERILP1_SGRF 182 562 #define SRST_P_PERILP1_GRF 183 563 #define SRST_CRYPTO1_S 184 564 #define SRST_CRYPTO1_M 185 565 #define SRST_CRYPTO1 186 566 #define SRST_GIC_NOC 188 567 #define SRST_SD_NOC 189 568 #define SRST_SDIOAUDIO_BRG 190 569 570 /* cru_softrst_con12 */ 571 #define SRST_H_PERILP1 192 572 #define SRST_H_PERILP1_NOC 193 573 #define SRST_H_I2S0_8CH 194 574 #define SRST_H_I2S1_8CH 195 575 #define SRST_H_I2S2_8CH 196 576 #define SRST_H_SPDIF_8CH 197 577 #define SRST_P_PERILP1_NOC 198 578 #define SRST_P_EFUSE_1024 199 579 #define SRST_P_EFUSE_1024S 200 580 #define SRST_P_I2C0 201 581 #define SRST_P_I2C1 202 582 #define SRST_P_I2C2 203 583 #define SRST_P_I2C3 204 584 #define SRST_P_I2C4 205 585 #define SRST_P_I2C5 206 586 #define SRST_P_MAILBOX0 207 587 588 /* cru_softrst_con13 */ 589 #define SRST_P_UART0 208 590 #define SRST_P_UART1 209 591 #define SRST_P_UART2 210 592 #define SRST_P_UART3 211 593 #define SRST_P_SARADC 212 594 #define SRST_P_TSADC 213 595 #define SRST_P_SPI0 214 596 #define SRST_P_SPI1 215 597 #define SRST_P_SPI2 216 598 #define SRST_P_SPI4 217 599 #define SRST_P_SPI5 218 600 #define SRST_SPI0 219 601 #define SRST_SPI1 220 602 #define SRST_SPI2 221 603 #define SRST_SPI4 222 604 #define SRST_SPI5 223 605 606 /* cru_softrst_con14 */ 607 #define SRST_I2S0_8CH 224 608 #define SRST_I2S1_8CH 225 609 #define SRST_I2S2_8CH 226 610 #define SRST_SPDIF_8CH 227 611 #define SRST_UART0 228 612 #define SRST_UART1 229 613 #define SRST_UART2 230 614 #define SRST_UART3 231 615 #define SRST_TSADC 232 616 #define SRST_I2C0 233 617 #define SRST_I2C1 234 618 #define SRST_I2C2 235 619 #define SRST_I2C3 236 620 #define SRST_I2C4 237 621 #define SRST_I2C5 238 622 #define SRST_SDIOAUDIO_NOC 239 623 624 /* cru_softrst_con15 */ 625 #define SRST_A_VIO_NOC 240 626 #define SRST_A_HDCP_NOC 241 627 #define SRST_A_HDCP 242 628 #define SRST_H_HDCP_NOC 243 629 #define SRST_H_HDCP 244 630 #define SRST_P_HDCP_NOC 245 631 #define SRST_P_HDCP 246 632 #define SRST_P_HDMI_CTRL 247 633 #define SRST_P_DP_CTRL 248 634 #define SRST_S_DP_CTRL 249 635 #define SRST_C_DP_CTRL 250 636 #define SRST_P_MIPI_DSI0 251 637 #define SRST_P_MIPI_DSI1 252 638 #define SRST_DP_CORE 253 639 #define SRST_DP_I2S 254 640 641 /* cru_softrst_con16 */ 642 #define SRST_GASKET 256 643 #define SRST_VIO_GRF 258 644 #define SRST_DPTX_SPDIF_REC 259 645 #define SRST_HDMI_CTRL 260 646 #define SRST_HDCP_CTRL 261 647 #define SRST_A_ISP0_NOC 262 648 #define SRST_A_ISP1_NOC 263 649 #define SRST_H_ISP0_NOC 266 650 #define SRST_H_ISP1_NOC 267 651 #define SRST_H_ISP0 268 652 #define SRST_H_ISP1 269 653 #define SRST_ISP0 270 654 #define SRST_ISP1 271 655 656 /* cru_softrst_con17 */ 657 #define SRST_A_VOP0_NOC 272 658 #define SRST_A_VOP1_NOC 273 659 #define SRST_A_VOP0 274 660 #define SRST_A_VOP1 275 661 #define SRST_H_VOP0_NOC 276 662 #define SRST_H_VOP1_NOC 277 663 #define SRST_H_VOP0 278 664 #define SRST_H_VOP1 279 665 #define SRST_D_VOP0 280 666 #define SRST_D_VOP1 281 667 #define SRST_VOP0_PWM 282 668 #define SRST_VOP1_PWM 283 669 #define SRST_P_EDP_NOC 284 670 #define SRST_P_EDP_CTRL 285 671 672 /* cru_softrst_con18 */ 673 #define SRST_A_GPU 288 674 #define SRST_A_GPU_NOC 289 675 #define SRST_A_GPU_GRF 290 676 #define SRST_PVTM_GPU 291 677 #define SRST_A_USB3_NOC 292 678 #define SRST_A_USB3_OTG0 293 679 #define SRST_A_USB3_OTG1 294 680 #define SRST_A_USB3_GRF 295 681 #define SRST_PMU 296 682 683 /* cru_softrst_con19 */ 684 #define SRST_P_TIMER0_5 304 685 #define SRST_TIMER0 305 686 #define SRST_TIMER1 306 687 #define SRST_TIMER2 307 688 #define SRST_TIMER3 308 689 #define SRST_TIMER4 309 690 #define SRST_TIMER5 310 691 #define SRST_P_TIMER6_11 311 692 #define SRST_TIMER6 312 693 #define SRST_TIMER7 313 694 #define SRST_TIMER8 314 695 #define SRST_TIMER9 315 696 #define SRST_TIMER10 316 697 #define SRST_TIMER11 317 698 #define SRST_P_INTR_ARB_PMU 318 699 #define SRST_P_ALIVE_SGRF 319 700 701 /* cru_softrst_con20 */ 702 #define SRST_P_GPIO2 320 703 #define SRST_P_GPIO3 321 704 #define SRST_P_GPIO4 322 705 #define SRST_P_GRF 323 706 #define SRST_P_ALIVE_NOC 324 707 #define SRST_P_WDT0 325 708 #define SRST_P_WDT1 326 709 #define SRST_P_INTR_ARB 327 710 #define SRST_P_UPHY0_DPTX 328 711 #define SRST_P_UPHY0_APB 330 712 #define SRST_P_UPHY0_TCPHY 332 713 #define SRST_P_UPHY1_TCPHY 333 714 #define SRST_P_UPHY0_TCPDCTRL 334 715 #define SRST_P_UPHY1_TCPDCTRL 335 716 717 /* pmu soft-reset indices */ 718 719 /* pmu_cru_softrst_con0 */ 720 #define SRST_P_NOC 0 721 #define SRST_P_INTMEM 1 722 #define SRST_H_CM0S 2 723 #define SRST_H_CM0S_NOC 3 724 #define SRST_DBG_CM0S 4 725 #define SRST_PO_CM0S 5 726 #define SRST_P_SPI3 6 727 #define SRST_SPI3 7 728 #define SRST_P_TIMER_0_1 8 729 #define SRST_P_TIMER_0 9 730 #define SRST_P_TIMER_1 10 731 #define SRST_P_UART4 11 732 #define SRST_UART4 12 733 #define SRST_P_WDT 13 734 735 /* pmu_cru_softrst_con1 */ 736 #define SRST_P_I2C6 16 737 #define SRST_P_I2C7 17 738 #define SRST_P_I2C8 18 739 #define SRST_P_MAILBOX 19 740 #define SRST_P_RKPWM 20 741 #define SRST_P_PMUGRF 21 742 #define SRST_P_SGRF 22 743 #define SRST_P_GPIO0 23 744 #define SRST_P_GPIO1 24 745 #define SRST_P_CRU 25 746 #define SRST_P_INTR 26 747 #define SRST_PVTM 27 748 #define SRST_I2C6 28 749 #define SRST_I2C7 29 750 #define SRST_I2C8 30 751 752 #endif 753