| 6c8dda19 | 17-May-2021 |
Chris Kay <chris.kay@arm.com> |
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
With the introduction of MPMM, the auxiliary AMU counter logic requires
refactoring to move away from a single platform-defined group 1 counter
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
With the introduction of MPMM, the auxiliary AMU counter logic requires
refactoring to move away from a single platform-defined group 1 counter
mask in order to support microarchitectural (per-core) group 1 counters.
BREAKING CHANGE: The `PLAT_AMU_GROUP1_COUNTERS_MASK` platform definition
has been removed. Platforms should specify per-core AMU counter masks
via FCONF or a platform-specific mechanism going forward.
Change-Id: I1e852797c7954f92409222b066a1ae57bc72bb05
Signed-off-by: Chris Kay <chris.kay@arm.com>
show more ...
|
| 700e7685 | 21-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
fix: remove "experimental" tag for stable features
there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer mark
fix: remove "experimental" tag for stable features
there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer marked as experimental
- SPMD
- MEASURED_BOOT
- FCONF and associated build flags
- DECRYPTION_SUPPORT and associated build flags
- ENABLE_PAUTH
- ENABLE_BTI
- USE_SPINLOCK_CAS
- GICv3 Multichip support
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9
show more ...
|
| 403f4cb3 | 18-Oct-2021 |
Daniel Boulby <daniel.boulby@arm.com> |
docs(gcc): update GCC to version 10.3-2021.07
This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal target (a
docs(gcc): update GCC to version 10.3-2021.07
This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I673e0dce8eb3ca3a004a43158a948431b032e93a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
show more ...
|
| 9b3004cf | 20-Sep-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(measured boot): add measured boot platform functions
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I411ee37cfeec32925849042689e8fdc7a26b7b13 |
| 5b18de09 | 11-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add ENABLE_RME build option and support for RMM image
The changes include:
- A new build option (ENABLE_RME) to enable FEAT_RME
- New image called RMM. RMM is R-EL2 firmware that manage
feat(rme): add ENABLE_RME build option and support for RMM image
The changes include:
- A new build option (ENABLE_RME) to enable FEAT_RME
- New image called RMM. RMM is R-EL2 firmware that manages Realms.
When building TF-A, a path to RMM image can be specified using
the "RMM" build flag. If RMM image is not provided, TRP is built
by default and used as RMM image.
- Support for RMM image in fiptool
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I017c23ef02e465a5198baafd665a60858ecd1b25
show more ...
|
| 5447302f | 29-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "build(bl2): enable SP pkg loading for S-EL1 SPMC" into integration |
| 46789a7c | 26-Mar-2021 |
Balint Dobszay <balint.dobszay@arm.com> |
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balin
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
show more ...
|
| cb4ec47b | 05-Aug-2021 |
johpow01 <john.powell@arm.com> |
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
show more ...
|
| b3210f4d | 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
show more ...
|
| 2c248ade | 04-May-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(gic600ae): introduce support for Fault Management Unit
The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:
* Provides software the
feat(gic600ae): introduce support for Fault Management Unit
The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:
* Provides software the means to enable or disable a Safety Mechanism
within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
blocks.
* Maintains error records for each GIC block, for software inspection
and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
capabilities in a Safety Mechanism.
This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.
The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.
Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 8fcd3d96 | 08-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2
feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| d4582d30 | 29-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when N
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 813524ea | 02-Jul-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when N
feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).
Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 0f20e50b | 20-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and update
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and updated components in I/O policy
Change-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 34f702d5 | 16-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-b
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 9fa5db4d | 05-Jul-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "sb/measured-boot" into integration
* changes:
refactor(plat/fvp): tidy up list of images to measure
docs: explain Measured Boot dependency on Trusted Boot |
| cc255b9f | 10-Jun-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: explain Measured Boot dependency on Trusted Boot
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 0c5e7d1c | 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
show more ...
|
| 99a99eb4 | 01-Jun-2021 |
Zelalem <zelalem.aweke@arm.com> |
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm
docs: change Linaro release version to 20.01
We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173
show more ...
|
| e55d12b7 | 27-May-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI con
Merge changes from topic "Arm_PCI_Config_Space_Interface" into integration
* changes:
TF-A: Document SMC_PCI_SUPPORT option
SMCCC/PCI: Handle std svc boilerplate
SMCCC/PCI: Add initial PCI conduit definitions
SMCCC: Hoist SMC_32 sanitization
show more ...
|
| 481c7b6b | 25-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(docs): fix typos in v2.5 release documentation
Two issues in documentation were identified after the release.
This patch fixes these typos.
1. Matternhorn ELP CPU was made available through v2.
fix(docs): fix typos in v2.5 release documentation
Two issues in documentation were identified after the release.
This patch fixes these typos.
1. Matternhorn ELP CPU was made available through v2.5 release, not
Matternhorn CPU
2. We had upgraded TF-A to use GCC 10.2 toolchain family and used this
toolchain for release testing
Change-Id: I33e59bb5a6d13f4d40dbb3352004d5b133431d65
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| 2d31cb07 | 27-Jan-2021 |
Jeremy Linton <jeremy.linton@arm.com> |
TF-A: Document SMC_PCI_SUPPORT option
Add some basic documentation and pointers for the SMCCC PCI
build options.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ia35f31d15066ea74135
TF-A: Document SMC_PCI_SUPPORT option
Add some basic documentation and pointers for the SMCCC PCI
build options.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e
show more ...
|
| a4371d1c | 17-May-2021 |
Chris Kay <chris.kay@arm.com> |
docs(prerequisites): add `--no-save` to `npm install`
To avoid the mistake fixed by the previous commit, ensure users install
the Node.js dependencies without polluting the lock file by passing
`--n
docs(prerequisites): add `--no-save` to `npm install`
To avoid the mistake fixed by the previous commit, ensure users install
the Node.js dependencies without polluting the lock file by passing
`--no-save` to the `npm install` line.
Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1
Signed-off-by: Chris Kay <chris.kay@arm.com>
show more ...
|
| 4324a14b | 05-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.
Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| 745df305 | 21-Apr-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "ck/conventional-commits" into integration
* changes:
build(hooks): add commitlint hook
build(hooks): add Commitizen hook
build(hooks): add Gerrit hook
build(hooks):
Merge changes from topic "ck/conventional-commits" into integration
* changes:
build(hooks): add commitlint hook
build(hooks): add Commitizen hook
build(hooks): add Gerrit hook
build(hooks): add Husky configuration
show more ...
|