1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <endian.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #include <i2c.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <ls_interconnect.h> 18 #include <mmio.h> 19 #if TRUSTED_BOARD_BOOT 20 #include <nxp_smmu.h> 21 #endif 22 #include <nxp_timer.h> 23 #ifdef CONFIG_OCRAM_ECC_EN 24 #include <ocram.h> 25 #endif 26 #include <plat_console.h> 27 #include <plat_gic.h> 28 #include <plat_tzc400.h> 29 #include <pmu.h> 30 #include <scfg.h> 31 #if defined(NXP_SFP_ENABLED) 32 #include <sfp.h> 33 #endif 34 35 #include <errata.h> 36 #include "plat_common.h" 37 #include "platform_def.h" 38 #include "soc.h" 39 40 static dcfg_init_info_t dcfg_init_data = { 41 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 42 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 43 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 44 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 45 }; 46 47 static struct soc_type soc_list[] = { 48 SOC_ENTRY(LS1017AN, LS1017AN, 1, 1), 49 SOC_ENTRY(LS1017AE, LS1017AE, 1, 1), 50 SOC_ENTRY(LS1018AN, LS1018AN, 1, 1), 51 SOC_ENTRY(LS1018AE, LS1018AE, 1, 1), 52 SOC_ENTRY(LS1027AN, LS1027AN, 1, 2), 53 SOC_ENTRY(LS1027AE, LS1027AE, 1, 2), 54 SOC_ENTRY(LS1028AN, LS1028AN, 1, 2), 55 SOC_ENTRY(LS1028AE, LS1028AE, 1, 2), 56 }; 57 58 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 59 assert_invalid_ls1028a_cluster_count); 60 61 /* 62 * Function returns the base counter frequency 63 * after reading the first entry at CNTFID0 (0x20 offset). 64 * 65 * Function is used by: 66 * 1. ARM common code for PSCI management. 67 * 2. ARM Generic Timer init. 68 * 69 */ 70 unsigned int plat_get_syscnt_freq2(void) 71 { 72 unsigned int counter_base_frequency; 73 /* 74 * Below register specifies the base frequency of the system counter. 75 * As per NXP Board Manuals: 76 * The system counter always works with SYS_REF_CLK/4 frequency clock. 77 */ 78 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 79 80 return counter_base_frequency; 81 } 82 83 #ifdef IMAGE_BL2 84 void soc_preload_setup(void) 85 { 86 } 87 88 void soc_early_init(void) 89 { 90 uint8_t num_clusters, cores_per_cluster; 91 92 #ifdef CONFIG_OCRAM_ECC_EN 93 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 94 #endif 95 dcfg_init(&dcfg_init_data); 96 enable_timer_base_to_cluster(NXP_PMU_ADDR); 97 enable_core_tb(NXP_PMU_ADDR); 98 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 99 100 #ifdef POLICY_FUSE_PROVISION 101 gpio_init(&gpio_init_data); 102 sec_init(NXP_CAAM_ADDR); 103 #endif 104 105 #if LOG_LEVEL > 0 106 /* Initialize the console to provide early debug support */ 107 plat_console_init(NXP_CONSOLE_ADDR, 108 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 109 #endif 110 enum boot_device dev = get_boot_dev(); 111 /* 112 * Mark the buffer for SD in OCRAM as non secure. 113 * The buffer is assumed to be at end of OCRAM for 114 * the logic below to calculate TZPC programming 115 */ 116 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 117 /* 118 * Calculate the region in OCRAM which is secure 119 * The buffer for SD needs to be marked non-secure 120 * to allow SD to do DMA operations on it 121 */ 122 uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE); 123 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 124 125 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 126 127 /* Add the entry for buffer in MMU Table */ 128 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 129 NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS); 130 } 131 132 #if TRUSTED_BOARD_BOOT 133 uint32_t mode; 134 135 sfp_init(NXP_SFP_ADDR); 136 137 /* 138 * For secure boot disable SMMU. 139 * Later when platform security policy comes in picture, 140 * this might get modified based on the policy 141 */ 142 if (check_boot_mode_secure(&mode) == true) { 143 bypass_smmu(NXP_SMMU_ADDR); 144 } 145 146 /* 147 * For Mbedtls currently crypto is not supported via CAAM 148 * enable it when that support is there. In tbbr.mk 149 * the CAAM_INTEG is set as 0. 150 */ 151 #ifndef MBEDTLS_X509 152 /* Initialize the crypto accelerator if enabled */ 153 if (is_sec_enabled()) { 154 sec_init(NXP_CAAM_ADDR); 155 } else { 156 INFO("SEC is disabled.\n"); 157 } 158 #endif 159 #endif 160 161 /* Set eDDRTQ for DDR performance */ 162 scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f); 163 164 soc_errata(); 165 166 /* 167 * Initialize Interconnect for this cluster during cold boot. 168 * No need for locks as no other CPU is active. 169 */ 170 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 171 172 /* 173 * Enable Interconnect coherency for the primary CPU's cluster. 174 */ 175 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 176 plat_ls_interconnect_enter_coherency(num_clusters); 177 178 delay_timer_init(NXP_TIMER_ADDR); 179 i2c_init(NXP_I2C_ADDR); 180 dram_regions_info->total_dram_size = init_ddr(); 181 } 182 183 void soc_bl2_prepare_exit(void) 184 { 185 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 186 set_sfp_wr_disable(); 187 #endif 188 } 189 190 /* 191 * This function returns the boot device based on RCW_SRC 192 */ 193 enum boot_device get_boot_dev(void) 194 { 195 enum boot_device src = BOOT_DEVICE_NONE; 196 uint32_t porsr1; 197 uint32_t rcw_src; 198 199 porsr1 = read_reg_porsr1(); 200 201 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 202 switch (rcw_src) { 203 case FLEXSPI_NOR: 204 src = BOOT_DEVICE_FLEXSPI_NOR; 205 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 206 break; 207 case FLEXSPI_NAND2K_VAL: 208 case FLEXSPI_NAND4K_VAL: 209 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 210 src = BOOT_DEVICE_FLEXSPI_NAND; 211 break; 212 case SDHC1_VAL: 213 src = BOOT_DEVICE_EMMC; 214 INFO("RCW BOOT SRC is SD\n"); 215 break; 216 case SDHC2_VAL: 217 src = BOOT_DEVICE_SDHC2_EMMC; 218 INFO("RCW BOOT SRC is EMMC\n"); 219 break; 220 default: 221 break; 222 } 223 224 return src; 225 } 226 227 /* 228 * This function sets up access permissions on memory regions 229 ****************************************************************************/ 230 void soc_mem_access(void) 231 { 232 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 233 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 234 int dram_idx = 0; 235 /* index 0 is reserved for region-0 */ 236 int index = 1; 237 238 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; 239 dram_idx++) { 240 if (info_dram_regions->region[dram_idx].size == 0) { 241 ERROR("DDR init failure, or"); 242 ERROR("DRAM regions not populated correctly.\n"); 243 break; 244 } 245 246 index = populate_tzc400_reg_list(tzc400_reg_list, 247 dram_idx, index, 248 info_dram_regions->region[dram_idx].addr, 249 info_dram_regions->region[dram_idx].size, 250 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 251 } 252 253 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); 254 } 255 256 #else 257 258 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; 259 /* 260 * This function dynamically constructs the topology according to 261 * SoC Flavor and returns it. 262 */ 263 const unsigned char *plat_get_power_domain_tree_desc(void) 264 { 265 uint8_t num_clusters, cores_per_cluster; 266 unsigned int i; 267 268 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 269 /* 270 * The highest level is the system level. The next level is constituted 271 * by clusters and then cores in clusters. 272 */ 273 _power_domain_tree_desc[0] = 1; 274 _power_domain_tree_desc[1] = num_clusters; 275 276 for (i = 0; i < _power_domain_tree_desc[1]; i++) 277 _power_domain_tree_desc[i + 2] = cores_per_cluster; 278 279 return _power_domain_tree_desc; 280 } 281 282 /* 283 * This function returns the core count within the cluster corresponding to 284 * `mpidr`. 285 */ 286 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 287 { 288 uint8_t num_clusters, cores_per_cluster; 289 290 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 291 return num_clusters; 292 } 293 294 void soc_early_platform_setup2(void) 295 { 296 dcfg_init(&dcfg_init_data); 297 /* Initialize system level generic timer for Socs */ 298 delay_timer_init(NXP_TIMER_ADDR); 299 300 #if LOG_LEVEL > 0 301 /* Initialize the console to provide early debug support */ 302 plat_console_init(NXP_CONSOLE_ADDR, 303 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 304 #endif 305 } 306 307 void soc_platform_setup(void) 308 { 309 /* Initialize the GIC driver, cpu and distributor interfaces */ 310 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 311 static interrupt_prop_t ls_interrupt_props[] = { 312 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 313 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 314 }; 315 316 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 317 PLATFORM_CORE_COUNT, 318 ls_interrupt_props, 319 ARRAY_SIZE(ls_interrupt_props), 320 target_mask_array, 321 plat_core_pos); 322 323 plat_ls_gic_init(); 324 enable_init_timer(); 325 } 326 327 /* This function initializes the soc from the BL31 module */ 328 void soc_init(void) 329 { 330 uint8_t num_clusters, cores_per_cluster; 331 332 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 333 334 /* Low-level init of the soc */ 335 soc_init_lowlevel(); 336 _init_global_data(); 337 soc_init_percpu(); 338 _initialize_psci(); 339 340 /* 341 * Initialize Interconnect for this cluster during cold boot. 342 * No need for locks as no other CPU is active. 343 */ 344 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 345 346 /* Enable Interconnect coherency for the primary CPU's cluster. */ 347 plat_ls_interconnect_enter_coherency(num_clusters); 348 349 /* Set platform security policies */ 350 _set_platform_security(); 351 352 /* Init SEC Engine which will be used by SiP */ 353 if (is_sec_enabled()) { 354 sec_init(NXP_CAAM_ADDR); 355 } else { 356 INFO("SEC is disabled.\n"); 357 } 358 } 359 360 #ifdef NXP_WDOG_RESTART 361 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 362 void *handle, void *cookie) 363 { 364 uint8_t data = WDOG_RESET_FLAG; 365 366 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 367 (uint8_t *)&data, sizeof(data)); 368 369 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 370 371 return 0; 372 } 373 #endif 374 375 void soc_runtime_setup(void) 376 { 377 #ifdef NXP_WDOG_RESTART 378 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 379 #endif 380 } 381 382 /* This function returns the total number of cores in the SoC. */ 383 unsigned int get_tot_num_cores(void) 384 { 385 uint8_t num_clusters, cores_per_cluster; 386 387 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 388 return (num_clusters * cores_per_cluster); 389 } 390 391 /* This function returns the PMU IDLE Cluster mask. */ 392 unsigned int get_pmu_idle_cluster_mask(void) 393 { 394 uint8_t num_clusters, cores_per_cluster; 395 396 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 397 return ((1 << num_clusters) - 2); 398 } 399 400 /* This function returns the PMU Flush Cluster mask. */ 401 unsigned int get_pmu_flush_cluster_mask(void) 402 { 403 uint8_t num_clusters, cores_per_cluster; 404 405 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 406 return ((1 << num_clusters) - 2); 407 } 408 409 /* This function returns the PMU idle core mask. */ 410 unsigned int get_pmu_idle_core_mask(void) 411 { 412 return ((1 << get_tot_num_cores()) - 2); 413 } 414 415 /* Function to return the SoC SYS CLK */ 416 unsigned int get_sys_clk(void) 417 { 418 return NXP_SYSCLK_FREQ; 419 } 420 #endif 421