1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/sys_reg_trace.h> 26 #include <lib/extensions/trbe.h> 27 #include <lib/extensions/trf.h> 28 #include <lib/extensions/twed.h> 29 #include <lib/utils.h> 30 31 static void enable_extensions_secure(cpu_context_t *ctx); 32 33 /******************************************************************************* 34 * Context management library initialisation routine. This library is used by 35 * runtime services to share pointers to 'cpu_context' structures for the secure 36 * and non-secure states. Management of the structures and their associated 37 * memory is not done by the context management library e.g. the PSCI service 38 * manages the cpu context used for entry from and exit to the non-secure state. 39 * The Secure payload dispatcher service manages the context(s) corresponding to 40 * the secure state. It also uses this library to get access to the non-secure 41 * state cpu context pointers. 42 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 43 * which will used for programming an entry into a lower EL. The same context 44 * will used to save state upon exception entry from that EL. 45 ******************************************************************************/ 46 void __init cm_init(void) 47 { 48 /* 49 * The context management library has only global data to intialize, but 50 * that will be done when the BSS is zeroed out 51 */ 52 } 53 54 /******************************************************************************* 55 * The following function initializes the cpu_context 'ctx' for 56 * first use, and sets the initial entrypoint state as specified by the 57 * entry_point_info structure. 58 * 59 * The security state to initialize is determined by the SECURE attribute 60 * of the entry_point_info. 61 * 62 * The EE and ST attributes are used to configure the endianness and secure 63 * timer availability for the new execution context. 64 * 65 * To prepare the register state for entry call cm_prepare_el3_exit() and 66 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 67 * cm_el1_sysregs_context_restore(). 68 ******************************************************************************/ 69 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 70 { 71 unsigned int security_state; 72 u_register_t scr_el3; 73 el3_state_t *state; 74 gp_regs_t *gp_regs; 75 u_register_t sctlr_elx, actlr_elx; 76 77 assert(ctx != NULL); 78 79 security_state = GET_SECURITY_STATE(ep->h.attr); 80 81 /* Clear any residual register values from the context */ 82 zeromem(ctx, sizeof(*ctx)); 83 84 /* 85 * SCR_EL3 was initialised during reset sequence in macro 86 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 87 * affect the next EL. 88 * 89 * The following fields are initially set to zero and then updated to 90 * the required value depending on the state of the SPSR_EL3 and the 91 * Security state and entrypoint attributes of the next EL. 92 */ 93 scr_el3 = read_scr(); 94 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 95 SCR_ST_BIT | SCR_HCE_BIT); 96 /* 97 * SCR_NS: Set the security state of the next EL. 98 */ 99 if (security_state != SECURE) 100 scr_el3 |= SCR_NS_BIT; 101 /* 102 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 103 * Exception level as specified by SPSR. 104 */ 105 if (GET_RW(ep->spsr) == MODE_RW_64) 106 scr_el3 |= SCR_RW_BIT; 107 /* 108 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 109 * Secure timer registers to EL3, from AArch64 state only, if specified 110 * by the entrypoint attributes. 111 */ 112 if (EP_GET_ST(ep->h.attr) != 0U) 113 scr_el3 |= SCR_ST_BIT; 114 115 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 116 /* 117 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 118 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 119 */ 120 scr_el3 |= SCR_TERR_BIT; 121 #endif 122 123 #if !HANDLE_EA_EL3_FIRST 124 /* 125 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 126 * to EL3 when executing at a lower EL. When executing at EL3, External 127 * Aborts are taken to EL3. 128 */ 129 scr_el3 &= ~SCR_EA_BIT; 130 #endif 131 132 #if FAULT_INJECTION_SUPPORT 133 /* Enable fault injection from lower ELs */ 134 scr_el3 |= SCR_FIEN_BIT; 135 #endif 136 137 #if !CTX_INCLUDE_PAUTH_REGS 138 /* 139 * If the pointer authentication registers aren't saved during world 140 * switches the value of the registers can be leaked from the Secure to 141 * the Non-secure world. To prevent this, rather than enabling pointer 142 * authentication everywhere, we only enable it in the Non-secure world. 143 * 144 * If the Secure world wants to use pointer authentication, 145 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 146 */ 147 if (security_state == NON_SECURE) 148 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 149 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 150 151 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 152 /* Get Memory Tagging Extension support level */ 153 unsigned int mte = get_armv8_5_mte_support(); 154 #endif 155 /* 156 * Enable MTE support. Support is enabled unilaterally for the normal 157 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 158 * set. 159 */ 160 #if CTX_INCLUDE_MTE_REGS 161 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 162 scr_el3 |= SCR_ATA_BIT; 163 #else 164 /* 165 * When MTE is only implemented at EL0, it can be enabled 166 * across both worlds as no MTE registers are used. 167 */ 168 if ((mte == MTE_IMPLEMENTED_EL0) || 169 /* 170 * When MTE is implemented at all ELs, it can be only enabled 171 * in Non-Secure world without register saving. 172 */ 173 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 174 (security_state == NON_SECURE))) { 175 scr_el3 |= SCR_ATA_BIT; 176 } 177 #endif /* CTX_INCLUDE_MTE_REGS */ 178 179 #ifdef IMAGE_BL31 180 /* 181 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 182 * indicated by the interrupt routing model for BL31. 183 */ 184 scr_el3 |= get_scr_el3_from_routing_model(security_state); 185 #endif 186 187 /* Save the initialized value of CPTR_EL3 register */ 188 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 189 if (security_state == SECURE) { 190 enable_extensions_secure(ctx); 191 } 192 193 /* 194 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 195 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 196 * next mode is Hyp. 197 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 198 * same conditions as HVC instructions and when the processor supports 199 * ARMv8.6-FGT. 200 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 201 * CNTPOFF_EL2 register under the same conditions as HVC instructions 202 * and when the processor supports ECV. 203 */ 204 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 205 || ((GET_RW(ep->spsr) != MODE_RW_64) 206 && (GET_M32(ep->spsr) == MODE32_hyp))) { 207 scr_el3 |= SCR_HCE_BIT; 208 209 if (is_armv8_6_fgt_present()) { 210 scr_el3 |= SCR_FGTEN_BIT; 211 } 212 213 if (get_armv8_6_ecv_support() 214 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 215 scr_el3 |= SCR_ECVEN_BIT; 216 } 217 } 218 219 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 220 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 221 if (GET_RW(ep->spsr) != MODE_RW_64) { 222 ERROR("S-EL2 can not be used in AArch32."); 223 panic(); 224 } 225 226 scr_el3 |= SCR_EEL2_BIT; 227 } 228 229 /* 230 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 231 * and EL2, when clear, this bit traps accesses from EL2 so we set it 232 * to 1 when EL2 is present. 233 */ 234 if (is_armv8_6_feat_amuv1p1_present() && 235 (el_implemented(2) != EL_IMPL_NONE)) { 236 scr_el3 |= SCR_AMVOFFEN_BIT; 237 } 238 239 /* 240 * Initialise SCTLR_EL1 to the reset value corresponding to the target 241 * execution state setting all fields rather than relying of the hw. 242 * Some fields have architecturally UNKNOWN reset values and these are 243 * set to zero. 244 * 245 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 246 * 247 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 248 * required by PSCI specification) 249 */ 250 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 251 if (GET_RW(ep->spsr) == MODE_RW_64) 252 sctlr_elx |= SCTLR_EL1_RES1; 253 else { 254 /* 255 * If the target execution state is AArch32 then the following 256 * fields need to be set. 257 * 258 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 259 * instructions are not trapped to EL1. 260 * 261 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 262 * instructions are not trapped to EL1. 263 * 264 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 265 * CP15DMB, CP15DSB, and CP15ISB instructions. 266 */ 267 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 268 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 269 } 270 271 #if ERRATA_A75_764081 272 /* 273 * If workaround of errata 764081 for Cortex-A75 is used then set 274 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 275 */ 276 sctlr_elx |= SCTLR_IESB_BIT; 277 #endif 278 279 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 280 if (is_armv8_6_twed_present()) { 281 uint32_t delay = plat_arm_set_twedel_scr_el3(); 282 283 if (delay != TWED_DISABLED) { 284 /* Make sure delay value fits */ 285 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 286 287 /* Set delay in SCR_EL3 */ 288 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 289 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 290 << SCR_TWEDEL_SHIFT); 291 292 /* Enable WFE delay */ 293 scr_el3 |= SCR_TWEDEn_BIT; 294 } 295 } 296 297 /* 298 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 299 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 300 * are not part of the stored cpu_context. 301 */ 302 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 303 304 /* 305 * Base the context ACTLR_EL1 on the current value, as it is 306 * implementation defined. The context restore process will write 307 * the value from the context to the actual register and can cause 308 * problems for processor cores that don't expect certain bits to 309 * be zero. 310 */ 311 actlr_elx = read_actlr_el1(); 312 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 313 314 /* 315 * Populate EL3 state so that we've the right context 316 * before doing ERET 317 */ 318 state = get_el3state_ctx(ctx); 319 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 320 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 321 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 322 323 /* 324 * Store the X0-X7 value from the entrypoint into the context 325 * Use memcpy as we are in control of the layout of the structures 326 */ 327 gp_regs = get_gpregs_ctx(ctx); 328 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 329 } 330 331 /******************************************************************************* 332 * Enable architecture extensions on first entry to Non-secure world. 333 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 334 * it is zero. 335 ******************************************************************************/ 336 static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 337 { 338 #if IMAGE_BL31 339 #if ENABLE_SPE_FOR_LOWER_ELS 340 spe_enable(el2_unused); 341 #endif 342 343 #if ENABLE_AMU 344 amu_enable(el2_unused, ctx); 345 #endif 346 347 #if ENABLE_SVE_FOR_NS 348 sve_enable(ctx); 349 #endif 350 351 #if ENABLE_MPAM_FOR_LOWER_ELS 352 mpam_enable(el2_unused); 353 #endif 354 355 #if ENABLE_TRBE_FOR_NS 356 trbe_enable(); 357 #endif /* ENABLE_TRBE_FOR_NS */ 358 359 #if ENABLE_SYS_REG_TRACE_FOR_NS 360 sys_reg_trace_enable(ctx); 361 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 362 363 #if ENABLE_TRF_FOR_NS 364 trf_enable(); 365 #endif /* ENABLE_TRF_FOR_NS */ 366 367 #endif 368 } 369 370 /******************************************************************************* 371 * Enable architecture extensions on first entry to Secure world. 372 ******************************************************************************/ 373 static void enable_extensions_secure(cpu_context_t *ctx) 374 { 375 #if IMAGE_BL31 376 #if ENABLE_SVE_FOR_SWD 377 sve_enable(ctx); 378 #endif 379 #endif 380 } 381 382 /******************************************************************************* 383 * The following function initializes the cpu_context for a CPU specified by 384 * its `cpu_idx` for first use, and sets the initial entrypoint state as 385 * specified by the entry_point_info structure. 386 ******************************************************************************/ 387 void cm_init_context_by_index(unsigned int cpu_idx, 388 const entry_point_info_t *ep) 389 { 390 cpu_context_t *ctx; 391 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 392 cm_setup_context(ctx, ep); 393 } 394 395 /******************************************************************************* 396 * The following function initializes the cpu_context for the current CPU 397 * for first use, and sets the initial entrypoint state as specified by the 398 * entry_point_info structure. 399 ******************************************************************************/ 400 void cm_init_my_context(const entry_point_info_t *ep) 401 { 402 cpu_context_t *ctx; 403 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 404 cm_setup_context(ctx, ep); 405 } 406 407 /******************************************************************************* 408 * Prepare the CPU system registers for first entry into secure or normal world 409 * 410 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 411 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 412 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 413 * For all entries, the EL1 registers are initialized from the cpu_context 414 ******************************************************************************/ 415 void cm_prepare_el3_exit(uint32_t security_state) 416 { 417 u_register_t sctlr_elx, scr_el3, mdcr_el2; 418 cpu_context_t *ctx = cm_get_context(security_state); 419 bool el2_unused = false; 420 uint64_t hcr_el2 = 0U; 421 422 assert(ctx != NULL); 423 424 if (security_state == NON_SECURE) { 425 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 426 CTX_SCR_EL3); 427 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 428 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 429 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 430 CTX_SCTLR_EL1); 431 sctlr_elx &= SCTLR_EE_BIT; 432 sctlr_elx |= SCTLR_EL2_RES1; 433 #if ERRATA_A75_764081 434 /* 435 * If workaround of errata 764081 for Cortex-A75 is used 436 * then set SCTLR_EL2.IESB to enable Implicit Error 437 * Synchronization Barrier. 438 */ 439 sctlr_elx |= SCTLR_IESB_BIT; 440 #endif 441 write_sctlr_el2(sctlr_elx); 442 } else if (el_implemented(2) != EL_IMPL_NONE) { 443 el2_unused = true; 444 445 /* 446 * EL2 present but unused, need to disable safely. 447 * SCTLR_EL2 can be ignored in this case. 448 * 449 * Set EL2 register width appropriately: Set HCR_EL2 450 * field to match SCR_EL3.RW. 451 */ 452 if ((scr_el3 & SCR_RW_BIT) != 0U) 453 hcr_el2 |= HCR_RW_BIT; 454 455 /* 456 * For Armv8.3 pointer authentication feature, disable 457 * traps to EL2 when accessing key registers or using 458 * pointer authentication instructions from lower ELs. 459 */ 460 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 461 462 write_hcr_el2(hcr_el2); 463 464 /* 465 * Initialise CPTR_EL2 setting all fields rather than 466 * relying on the hw. All fields have architecturally 467 * UNKNOWN reset values. 468 * 469 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 470 * accesses to the CPACR_EL1 or CPACR from both 471 * Execution states do not trap to EL2. 472 * 473 * CPTR_EL2.TTA: Set to zero so that Non-secure System 474 * register accesses to the trace registers from both 475 * Execution states do not trap to EL2. 476 * If PE trace unit System registers are not implemented 477 * then this bit is reserved, and must be set to zero. 478 * 479 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 480 * to SIMD and floating-point functionality from both 481 * Execution states do not trap to EL2. 482 */ 483 write_cptr_el2(CPTR_EL2_RESET_VAL & 484 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 485 | CPTR_EL2_TFP_BIT)); 486 487 /* 488 * Initialise CNTHCTL_EL2. All fields are 489 * architecturally UNKNOWN on reset and are set to zero 490 * except for field(s) listed below. 491 * 492 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 493 * Hyp mode of Non-secure EL0 and EL1 accesses to the 494 * physical timer registers. 495 * 496 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 497 * Hyp mode of Non-secure EL0 and EL1 accesses to the 498 * physical counter registers. 499 */ 500 write_cnthctl_el2(CNTHCTL_RESET_VAL | 501 EL1PCEN_BIT | EL1PCTEN_BIT); 502 503 /* 504 * Initialise CNTVOFF_EL2 to zero as it resets to an 505 * architecturally UNKNOWN value. 506 */ 507 write_cntvoff_el2(0); 508 509 /* 510 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 511 * MPIDR_EL1 respectively. 512 */ 513 write_vpidr_el2(read_midr_el1()); 514 write_vmpidr_el2(read_mpidr_el1()); 515 516 /* 517 * Initialise VTTBR_EL2. All fields are architecturally 518 * UNKNOWN on reset. 519 * 520 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 521 * 2 address translation is disabled, cache maintenance 522 * operations depend on the VMID. 523 * 524 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 525 * translation is disabled. 526 */ 527 write_vttbr_el2(VTTBR_RESET_VAL & 528 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 529 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 530 531 /* 532 * Initialise MDCR_EL2, setting all fields rather than 533 * relying on hw. Some fields are architecturally 534 * UNKNOWN on reset. 535 * 536 * MDCR_EL2.HLP: Set to one so that event counter 537 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 538 * occurs on the increment that changes 539 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 540 * implemented. This bit is RES0 in versions of the 541 * architecture earlier than ARMv8.5, setting it to 1 542 * doesn't have any effect on them. 543 * 544 * MDCR_EL2.TTRF: Set to zero so that access to Trace 545 * Filter Control register TRFCR_EL1 at EL1 is not 546 * trapped to EL2. This bit is RES0 in versions of 547 * the architecture earlier than ARMv8.4. 548 * 549 * MDCR_EL2.HPMD: Set to one so that event counting is 550 * prohibited at EL2. This bit is RES0 in versions of 551 * the architecture earlier than ARMv8.1, setting it 552 * to 1 doesn't have any effect on them. 553 * 554 * MDCR_EL2.TPMS: Set to zero so that accesses to 555 * Statistical Profiling control registers from EL1 556 * do not trap to EL2. This bit is RES0 when SPE is 557 * not implemented. 558 * 559 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 560 * EL1 System register accesses to the Debug ROM 561 * registers are not trapped to EL2. 562 * 563 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 564 * System register accesses to the powerdown debug 565 * registers are not trapped to EL2. 566 * 567 * MDCR_EL2.TDA: Set to zero so that System register 568 * accesses to the debug registers do not trap to EL2. 569 * 570 * MDCR_EL2.TDE: Set to zero so that debug exceptions 571 * are not routed to EL2. 572 * 573 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 574 * Monitors. 575 * 576 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 577 * EL1 accesses to all Performance Monitors registers 578 * are not trapped to EL2. 579 * 580 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 581 * and EL1 accesses to the PMCR_EL0 or PMCR are not 582 * trapped to EL2. 583 * 584 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 585 * architecturally-defined reset value. 586 * 587 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 588 * owning exception level is NS-EL1 and, tracing is 589 * prohibited at NS-EL2. These bits are RES0 when 590 * FEAT_TRBE is not implemented. 591 */ 592 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 593 MDCR_EL2_HPMD) | 594 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 595 >> PMCR_EL0_N_SHIFT)) & 596 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 597 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 598 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 599 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 600 MDCR_EL2_TPMCR_BIT | 601 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 602 603 write_mdcr_el2(mdcr_el2); 604 605 /* 606 * Initialise HSTR_EL2. All fields are architecturally 607 * UNKNOWN on reset. 608 * 609 * HSTR_EL2.T<n>: Set all these fields to zero so that 610 * Non-secure EL0 or EL1 accesses to System registers 611 * do not trap to EL2. 612 */ 613 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 614 /* 615 * Initialise CNTHP_CTL_EL2. All fields are 616 * architecturally UNKNOWN on reset. 617 * 618 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 619 * physical timer and prevent timer interrupts. 620 */ 621 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 622 ~(CNTHP_CTL_ENABLE_BIT)); 623 } 624 enable_extensions_nonsecure(el2_unused, ctx); 625 } 626 627 cm_el1_sysregs_context_restore(security_state); 628 cm_set_next_eret_context(security_state); 629 } 630 631 #if CTX_INCLUDE_EL2_REGS 632 /******************************************************************************* 633 * Save EL2 sysreg context 634 ******************************************************************************/ 635 void cm_el2_sysregs_context_save(uint32_t security_state) 636 { 637 u_register_t scr_el3 = read_scr(); 638 639 /* 640 * Always save the non-secure EL2 context, only save the 641 * S-EL2 context if S-EL2 is enabled. 642 */ 643 if ((security_state == NON_SECURE) || 644 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 645 cpu_context_t *ctx; 646 647 ctx = cm_get_context(security_state); 648 assert(ctx != NULL); 649 650 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 651 } 652 } 653 654 /******************************************************************************* 655 * Restore EL2 sysreg context 656 ******************************************************************************/ 657 void cm_el2_sysregs_context_restore(uint32_t security_state) 658 { 659 u_register_t scr_el3 = read_scr(); 660 661 /* 662 * Always restore the non-secure EL2 context, only restore the 663 * S-EL2 context if S-EL2 is enabled. 664 */ 665 if ((security_state == NON_SECURE) || 666 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 667 cpu_context_t *ctx; 668 669 ctx = cm_get_context(security_state); 670 assert(ctx != NULL); 671 672 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 673 } 674 } 675 #endif /* CTX_INCLUDE_EL2_REGS */ 676 677 /******************************************************************************* 678 * The next four functions are used by runtime services to save and restore 679 * EL1 context on the 'cpu_context' structure for the specified security 680 * state. 681 ******************************************************************************/ 682 void cm_el1_sysregs_context_save(uint32_t security_state) 683 { 684 cpu_context_t *ctx; 685 686 ctx = cm_get_context(security_state); 687 assert(ctx != NULL); 688 689 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 690 691 #if IMAGE_BL31 692 if (security_state == SECURE) 693 PUBLISH_EVENT(cm_exited_secure_world); 694 else 695 PUBLISH_EVENT(cm_exited_normal_world); 696 #endif 697 } 698 699 void cm_el1_sysregs_context_restore(uint32_t security_state) 700 { 701 cpu_context_t *ctx; 702 703 ctx = cm_get_context(security_state); 704 assert(ctx != NULL); 705 706 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 707 708 #if IMAGE_BL31 709 if (security_state == SECURE) 710 PUBLISH_EVENT(cm_entering_secure_world); 711 else 712 PUBLISH_EVENT(cm_entering_normal_world); 713 #endif 714 } 715 716 /******************************************************************************* 717 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 718 * given security state with the given entrypoint 719 ******************************************************************************/ 720 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 721 { 722 cpu_context_t *ctx; 723 el3_state_t *state; 724 725 ctx = cm_get_context(security_state); 726 assert(ctx != NULL); 727 728 /* Populate EL3 state so that ERET jumps to the correct entry */ 729 state = get_el3state_ctx(ctx); 730 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 731 } 732 733 /******************************************************************************* 734 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 735 * pertaining to the given security state 736 ******************************************************************************/ 737 void cm_set_elr_spsr_el3(uint32_t security_state, 738 uintptr_t entrypoint, uint32_t spsr) 739 { 740 cpu_context_t *ctx; 741 el3_state_t *state; 742 743 ctx = cm_get_context(security_state); 744 assert(ctx != NULL); 745 746 /* Populate EL3 state so that ERET jumps to the correct entry */ 747 state = get_el3state_ctx(ctx); 748 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 749 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 750 } 751 752 /******************************************************************************* 753 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 754 * pertaining to the given security state using the value and bit position 755 * specified in the parameters. It preserves all other bits. 756 ******************************************************************************/ 757 void cm_write_scr_el3_bit(uint32_t security_state, 758 uint32_t bit_pos, 759 uint32_t value) 760 { 761 cpu_context_t *ctx; 762 el3_state_t *state; 763 u_register_t scr_el3; 764 765 ctx = cm_get_context(security_state); 766 assert(ctx != NULL); 767 768 /* Ensure that the bit position is a valid one */ 769 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 770 771 /* Ensure that the 'value' is only a bit wide */ 772 assert(value <= 1U); 773 774 /* 775 * Get the SCR_EL3 value from the cpu context, clear the desired bit 776 * and set it to its new value. 777 */ 778 state = get_el3state_ctx(ctx); 779 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 780 scr_el3 &= ~(1UL << bit_pos); 781 scr_el3 |= (u_register_t)value << bit_pos; 782 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 783 } 784 785 /******************************************************************************* 786 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 787 * given security state. 788 ******************************************************************************/ 789 u_register_t cm_get_scr_el3(uint32_t security_state) 790 { 791 cpu_context_t *ctx; 792 el3_state_t *state; 793 794 ctx = cm_get_context(security_state); 795 assert(ctx != NULL); 796 797 /* Populate EL3 state so that ERET jumps to the correct entry */ 798 state = get_el3state_ctx(ctx); 799 return read_ctx_reg(state, CTX_SCR_EL3); 800 } 801 802 /******************************************************************************* 803 * This function is used to program the context that's used for exception 804 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 805 * the required security state 806 ******************************************************************************/ 807 void cm_set_next_eret_context(uint32_t security_state) 808 { 809 cpu_context_t *ctx; 810 811 ctx = cm_get_context(security_state); 812 assert(ctx != NULL); 813 814 cm_set_next_context(ctx); 815 } 816