1 /* 2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <common/bl_common.h> 16 #include <context.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/extensions/amu.h> 19 #include <lib/extensions/sys_reg_trace.h> 20 #include <lib/utils.h> 21 22 /******************************************************************************* 23 * Context management library initialisation routine. This library is used by 24 * runtime services to share pointers to 'cpu_context' structures for the secure 25 * and non-secure states. Management of the structures and their associated 26 * memory is not done by the context management library e.g. the PSCI service 27 * manages the cpu context used for entry from and exit to the non-secure state. 28 * The Secure payload manages the context(s) corresponding to the secure state. 29 * It also uses this library to get access to the non-secure 30 * state cpu context pointers. 31 ******************************************************************************/ 32 void cm_init(void) 33 { 34 /* 35 * The context management library has only global data to initialize, but 36 * that will be done when the BSS is zeroed out 37 */ 38 } 39 40 /******************************************************************************* 41 * The following function initializes the cpu_context 'ctx' for 42 * first use, and sets the initial entrypoint state as specified by the 43 * entry_point_info structure. 44 * 45 * The security state to initialize is determined by the SECURE attribute 46 * of the entry_point_info. 47 * 48 * The EE and ST attributes are used to configure the endianness and secure 49 * timer availability for the new execution context. 50 * 51 * To prepare the register state for entry call cm_prepare_el3_exit() and 52 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 53 * cm_el1_sysregs_context_restore(). 54 ******************************************************************************/ 55 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 56 { 57 unsigned int security_state; 58 uint32_t scr, sctlr; 59 regs_t *reg_ctx; 60 61 assert(ctx != NULL); 62 63 security_state = GET_SECURITY_STATE(ep->h.attr); 64 65 /* Clear any residual register values from the context */ 66 zeromem(ctx, sizeof(*ctx)); 67 68 reg_ctx = get_regs_ctx(ctx); 69 70 /* 71 * Base the context SCR on the current value, adjust for entry point 72 * specific requirements 73 */ 74 scr = read_scr(); 75 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); 76 77 if (security_state != SECURE) 78 scr |= SCR_NS_BIT; 79 80 if (security_state != SECURE) { 81 /* 82 * Set up SCTLR for the Non-secure context. 83 * 84 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 85 * 86 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 87 * required by PSCI specification) 88 * 89 * Set remaining SCTLR fields to their architecturally defined 90 * values. Some fields reset to an IMPLEMENTATION DEFINED value: 91 * 92 * SCTLR.TE: Set to zero so that exceptions to an Exception 93 * Level executing at PL1 are taken to A32 state. 94 * 95 * SCTLR.V: Set to zero to select the normal exception vectors 96 * with base address held in VBAR. 97 */ 98 assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) == 99 (EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT)); 100 101 sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 102 sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT)); 103 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); 104 } 105 106 /* 107 * The target exception level is based on the spsr mode requested. If 108 * execution is requested to hyp mode, HVC is enabled via SCR.HCE. 109 */ 110 if (GET_M32(ep->spsr) == MODE32_hyp) 111 scr |= SCR_HCE_BIT; 112 113 /* 114 * Store the initialised values for SCTLR and SCR in the cpu_context. 115 * The Hyp mode registers are not part of the saved context and are 116 * set-up in cm_prepare_el3_exit(). 117 */ 118 write_ctx_reg(reg_ctx, CTX_SCR, scr); 119 write_ctx_reg(reg_ctx, CTX_LR, ep->pc); 120 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); 121 122 /* 123 * Store the r0-r3 value from the entrypoint into the context 124 * Use memcpy as we are in control of the layout of the structures 125 */ 126 memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t)); 127 } 128 129 /******************************************************************************* 130 * Enable architecture extensions on first entry to Non-secure world. 131 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 132 * it is zero. 133 ******************************************************************************/ 134 static void enable_extensions_nonsecure(bool el2_unused) 135 { 136 #if IMAGE_BL32 137 #if ENABLE_AMU 138 amu_enable(el2_unused); 139 #endif 140 141 #if ENABLE_SYS_REG_TRACE_FOR_NS 142 sys_reg_trace_enable(); 143 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 144 #endif 145 } 146 147 /******************************************************************************* 148 * The following function initializes the cpu_context for a CPU specified by 149 * its `cpu_idx` for first use, and sets the initial entrypoint state as 150 * specified by the entry_point_info structure. 151 ******************************************************************************/ 152 void cm_init_context_by_index(unsigned int cpu_idx, 153 const entry_point_info_t *ep) 154 { 155 cpu_context_t *ctx; 156 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 157 cm_setup_context(ctx, ep); 158 } 159 160 /******************************************************************************* 161 * The following function initializes the cpu_context for the current CPU 162 * for first use, and sets the initial entrypoint state as specified by the 163 * entry_point_info structure. 164 ******************************************************************************/ 165 void cm_init_my_context(const entry_point_info_t *ep) 166 { 167 cpu_context_t *ctx; 168 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 169 cm_setup_context(ctx, ep); 170 } 171 172 /******************************************************************************* 173 * Prepare the CPU system registers for first entry into secure or normal world 174 * 175 * If execution is requested to hyp mode, HSCTLR is initialized 176 * If execution is requested to non-secure PL1, and the CPU supports 177 * HYP mode then HYP mode is disabled by configuring all necessary HYP mode 178 * registers. 179 ******************************************************************************/ 180 void cm_prepare_el3_exit(uint32_t security_state) 181 { 182 uint32_t hsctlr, scr; 183 cpu_context_t *ctx = cm_get_context(security_state); 184 bool el2_unused = false; 185 186 assert(ctx != NULL); 187 188 if (security_state == NON_SECURE) { 189 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); 190 if ((scr & SCR_HCE_BIT) != 0U) { 191 /* Use SCTLR value to initialize HSCTLR */ 192 hsctlr = read_ctx_reg(get_regs_ctx(ctx), 193 CTX_NS_SCTLR); 194 hsctlr |= HSCTLR_RES1; 195 /* Temporarily set the NS bit to access HSCTLR */ 196 write_scr(read_scr() | SCR_NS_BIT); 197 /* 198 * Make sure the write to SCR is complete so that 199 * we can access HSCTLR 200 */ 201 isb(); 202 write_hsctlr(hsctlr); 203 isb(); 204 205 write_scr(read_scr() & ~SCR_NS_BIT); 206 isb(); 207 } else if ((read_id_pfr1() & 208 (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) { 209 el2_unused = true; 210 211 /* 212 * Set the NS bit to access NS copies of certain banked 213 * registers 214 */ 215 write_scr(read_scr() | SCR_NS_BIT); 216 isb(); 217 218 /* 219 * Hyp / PL2 present but unused, need to disable safely. 220 * HSCTLR can be ignored in this case. 221 * 222 * Set HCR to its architectural reset value so that 223 * Non-secure operations do not trap to Hyp mode. 224 */ 225 write_hcr(HCR_RESET_VAL); 226 227 /* 228 * Set HCPTR to its architectural reset value so that 229 * Non-secure access from EL1 or EL0 to trace and to 230 * Advanced SIMD and floating point functionality does 231 * not trap to Hyp mode. 232 */ 233 write_hcptr(HCPTR_RESET_VAL); 234 235 /* 236 * Initialise CNTHCTL. All fields are architecturally 237 * UNKNOWN on reset and are set to zero except for 238 * field(s) listed below. 239 * 240 * CNTHCTL.PL1PCEN: Disable traps to Hyp mode of 241 * Non-secure EL0 and EL1 accessed to the physical 242 * timer registers. 243 * 244 * CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of 245 * Non-secure EL0 and EL1 accessed to the physical 246 * counter registers. 247 */ 248 write_cnthctl(CNTHCTL_RESET_VAL | 249 PL1PCEN_BIT | PL1PCTEN_BIT); 250 251 /* 252 * Initialise CNTVOFF to zero as it resets to an 253 * IMPLEMENTATION DEFINED value. 254 */ 255 write64_cntvoff(0); 256 257 /* 258 * Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR 259 * respectively. 260 */ 261 write_vpidr(read_midr()); 262 write_vmpidr(read_mpidr()); 263 264 /* 265 * Initialise VTTBR, setting all fields rather than 266 * relying on the hw. Some fields are architecturally 267 * UNKNOWN at reset. 268 * 269 * VTTBR.VMID: Set to zero which is the architecturally 270 * defined reset value. Even though EL1&0 stage 2 271 * address translation is disabled, cache maintenance 272 * operations depend on the VMID. 273 * 274 * VTTBR.BADDR: Set to zero as EL1&0 stage 2 address 275 * translation is disabled. 276 */ 277 write64_vttbr(VTTBR_RESET_VAL & 278 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 279 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 280 281 /* 282 * Initialise HDCR, setting all the fields rather than 283 * relying on hw. 284 * 285 * HDCR.HPMN: Set to value of PMCR.N which is the 286 * architecturally-defined reset value. 287 * 288 * HDCR.HLP: Set to one so that event counter 289 * overflow, that is recorded in PMOVSCLR[0-30], 290 * occurs on the increment that changes 291 * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is 292 * implemented. This bit is RES0 in versions of the 293 * architecture earlier than ARMv8.5, setting it to 1 294 * doesn't have any effect on them. 295 * This bit is Reserved, UNK/SBZP in ARMv7. 296 * 297 * HDCR.HPME: Set to zero to disable EL2 Event 298 * counters. 299 */ 300 #if (ARM_ARCH_MAJOR > 7) 301 write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT | 302 ((read_pmcr() & PMCR_N_BITS) >> 303 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); 304 #else 305 write_hdcr((HDCR_RESET_VAL | 306 ((read_pmcr() & PMCR_N_BITS) >> 307 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); 308 #endif 309 /* 310 * Set HSTR to its architectural reset value so that 311 * access to system registers in the cproc=1111 312 * encoding space do not trap to Hyp mode. 313 */ 314 write_hstr(HSTR_RESET_VAL); 315 /* 316 * Set CNTHP_CTL to its architectural reset value to 317 * disable the EL2 physical timer and prevent timer 318 * interrupts. Some fields are architecturally UNKNOWN 319 * on reset and are set to zero. 320 */ 321 write_cnthp_ctl(CNTHP_CTL_RESET_VAL); 322 isb(); 323 324 write_scr(read_scr() & ~SCR_NS_BIT); 325 isb(); 326 } 327 enable_extensions_nonsecure(el2_unused); 328 } 329 } 330