1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``BL2_AT_EL3``: This is an optional build option that enables the use of 56 BL2 at EL3 execution level. 57 58- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 60 61- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 62 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 63 the RW sections in RAM, while leaving the RO sections in place. This option 64 enable this use-case. For now, this option is only supported when BL2_AT_EL3 65 is set to '1'. 66 67- ``BL31``: This is an optional build option which specifies the path to 68 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 69 be built. 70 71- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 72 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 73 this file name will be used to save the key. 74 75- ``BL32``: This is an optional build option which specifies the path to 76 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 77 be built. 78 79- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 80 Trusted OS Extra1 image for the ``fip`` target. 81 82- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 83 Trusted OS Extra2 image for the ``fip`` target. 84 85- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 86 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 87 this file name will be used to save the key. 88 89- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 90 ``fip`` target in case TF-A BL2 is used. 91 92- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 93 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 94 this file name will be used to save the key. 95 96- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 97 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 98 If enabled, it is needed to use a compiler that supports the option 99 ``-mbranch-protection``. Selects the branch protection features to use: 100- 0: Default value turns off all types of branch protection 101- 1: Enables all types of branch protection features 102- 2: Return address signing to its standard level 103- 3: Extend the signing to include leaf functions 104- 4: Turn on branch target identification mechanism 105 106 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 107 and resulting PAuth/BTI features. 108 109 +-------+--------------+-------+-----+ 110 | Value | GCC option | PAuth | BTI | 111 +=======+==============+=======+=====+ 112 | 0 | none | N | N | 113 +-------+--------------+-------+-----+ 114 | 1 | standard | Y | Y | 115 +-------+--------------+-------+-----+ 116 | 2 | pac-ret | Y | N | 117 +-------+--------------+-------+-----+ 118 | 3 | pac-ret+leaf | Y | N | 119 +-------+--------------+-------+-----+ 120 | 4 | bti | N | Y | 121 +-------+--------------+-------+-----+ 122 123 This option defaults to 0. 124 Note that Pointer Authentication is enabled for Non-secure world 125 irrespective of the value of this option if the CPU supports it. 126 127- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 128 compilation of each build. It must be set to a C string (including quotes 129 where applicable). Defaults to a string that contains the time and date of 130 the compilation. 131 132- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 133 build to be uniquely identified. Defaults to the current git commit id. 134 135- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 136 137- ``CFLAGS``: Extra user options appended on the compiler's command line in 138 addition to the options set by the build system. 139 140- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 141 release several CPUs out of reset. It can take either 0 (several CPUs may be 142 brought up) or 1 (only one CPU will ever be brought up during cold reset). 143 Default is 0. If the platform always brings up a single CPU, there is no 144 need to distinguish between primary and secondary CPUs and the boot path can 145 be optimised. The ``plat_is_my_cpu_primary()`` and 146 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 147 to be implemented in this case. 148 149- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 150 Defaults to ``tbbr``. 151 152- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 153 register state when an unexpected exception occurs during execution of 154 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 155 this is only enabled for a debug build of the firmware. 156 157- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 158 certificate generation tool to create new keys in case no valid keys are 159 present or specified. Allowed options are '0' or '1'. Default is '1'. 160 161- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 162 the AArch32 system registers to be included when saving and restoring the 163 CPU context. The option must be set to 0 for AArch64-only platforms (that 164 is on hardware that does not implement AArch32, or at least not at EL1 and 165 higher ELs). Default value is 1. 166 167- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 168 operations when entering/exiting an EL2 execution context. This is of primary 169 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 171 ``SPMD_SPM_AT_SEL2`` is set. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 178 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 179 execution context. Default value is 0. 180 181- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 182 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 183 registers to be included when saving and restoring the CPU context as 184 part of world switch. Default value is 0. 185 Note that Pointer Authentication is enabled for Non-secure world irrespective 186 of the value of this flag if the CPU supports it. 187 188- ``DEBUG``: Chooses between a debug and release build. It can take either 0 189 (release) or 1 (debug) as values. 0 is the default. 190 191- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 192 authenticated decryption algorithm to be used to decrypt firmware/s during 193 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 194 this flag is ``none`` to disable firmware decryption which is an optional 195 feature as per TBBR. 196 197- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 198 of the binary image. If set to 1, then only the ELF image is built. 199 0 is the default. 200 201- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 202 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 203 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 204 check the latest Arm ARM. 205 206- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 207 Board Boot authentication at runtime. This option is meant to be enabled only 208 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 209 flag has to be enabled. 0 is the default. 210 211- ``E``: Boolean option to make warnings into errors. Default is 1. 212 213- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 214 the normal boot flow. It must specify the entry point address of the EL3 215 payload. Please refer to the "Booting an EL3 payload" section for more 216 details. 217 218- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 219 This is an optional architectural feature available on v8.4 onwards. Some 220 v8.2 implementations also implement an AMU and this option can be used to 221 enable this feature on those systems as well. Default is 0. 222 223- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 224 are compiled out. For debug builds, this option defaults to 1, and calls to 225 ``assert()`` are left in place. For release builds, this option defaults to 0 226 and calls to ``assert()`` function are compiled out. This option can be set 227 independently of ``DEBUG``. It can also be used to hide any auxiliary code 228 that is only required for the assertion and does not fit in the assertion 229 itself. 230 231- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 232 dumps or not. It is supported in both AArch64 and AArch32. However, in 233 AArch32 the format of the frame records are not defined in the AAPCS and they 234 are defined by the implementation. This implementation of backtrace only 235 supports the format used by GCC when T32 interworking is disabled. For this 236 reason enabling this option in AArch32 will force the compiler to only 237 generate A32 code. This option is enabled by default only in AArch64 debug 238 builds, but this behaviour can be overridden in each platform's Makefile or 239 in the build command line. 240 241- ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow 242 access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as 243 adding HCRX_EL2 to the EL2 context save/restore operations. 244 245- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 246 support in GCC for TF-A. This option is currently only supported for 247 AArch64. Default is 0. 248 249- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 250 feature. MPAM is an optional Armv8.4 extension that enables various memory 251 system components and resources to define partitions; software running at 252 various ELs can assign themselves to desired partition to control their 253 performance aspects. 254 255 When this option is set to ``1``, EL3 allows lower ELs to access their own 256 MPAM registers without trapping into EL3. This option doesn't make use of 257 partitioning in EL3, however. Platform initialisation code should configure 258 and use partitions in EL3 as required. This option defaults to ``0``. 259 260- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 261 support within generic code in TF-A. This option is currently only supported 262 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 263 (SP_min) for AARCH32. Default is 0. 264 265- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 266 Measurement Framework(PMF). Default is 0. 267 268- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 269 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 270 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 271 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 272 software. 273 274- ``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm 275 Management Extension. Default value is 0. This is currently an experimental 276 feature. 277 278- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 279 instrumentation which injects timestamp collection points into TF-A to 280 allow runtime performance to be measured. Currently, only PSCI is 281 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 282 as well. Default is 0. 283 284- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 285 extensions. This is an optional architectural feature for AArch64. 286 The default is 1 but is automatically disabled when the target architecture 287 is AArch32. 288 289- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 290 (SVE) for the Non-secure world only. SVE is an optional architectural feature 291 for AArch64. Note that when SVE is enabled for the Non-secure world, access 292 to SIMD and floating-point functionality from the Secure world is disabled by 293 default and controlled with ENABLE_SVE_FOR_SWD. 294 This is to avoid corruption of the Non-secure world data in the Z-registers 295 which are aliased by the SIMD and FP registers. The build option is not 296 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 297 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 298 1. The default is 1 but is automatically disabled when the target 299 architecture is AArch32. 300 301- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 302 SVE is an optional architectural feature for AArch64. Note that this option 303 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 304 automatically disabled when the target architecture is AArch32. 305 306- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 307 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 308 default value is set to "none". "strong" is the recommended stack protection 309 level if this feature is desired. "none" disables the stack protection. For 310 all values other than "none", the ``plat_get_stack_protector_canary()`` 311 platform hook needs to be implemented. The value is passed as the last 312 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 313 314- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 315 flag depends on ``DECRYPTION_SUPPORT`` build flag. 316 317- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 318 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 319 320- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 321 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 322 on ``DECRYPTION_SUPPORT`` build flag. 323 324- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 325 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 326 build flag. 327 328- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 329 deprecated platform APIs, helper functions or drivers within Trusted 330 Firmware as error. It can take the value 1 (flag the use of deprecated 331 APIs as error) or 0. The default is 0. 332 333- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 334 targeted at EL3. When set ``0`` (default), no exceptions are expected or 335 handled at EL3, and a panic will result. This is supported only for AArch64 336 builds. 337 338- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 339 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 340 Default value is 40 (LOG_LEVEL_INFO). 341 342- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 343 injection from lower ELs, and this build option enables lower ELs to use 344 Error Records accessed via System Registers to inject faults. This is 345 applicable only to AArch64 builds. 346 347 This feature is intended for testing purposes only, and is advisable to keep 348 disabled for production images. 349 350- ``FIP_NAME``: This is an optional build option which specifies the FIP 351 filename for the ``fip`` target. Default is ``fip.bin``. 352 353- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 354 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 355 356- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 357 358 :: 359 360 0: Encryption is done with Secret Symmetric Key (SSK) which is common 361 for a class of devices. 362 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 363 unique per device. 364 365 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 366 367- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 368 tool to create certificates as per the Chain of Trust described in 369 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 370 include the certificates in the FIP and FWU_FIP. Default value is '0'. 371 372 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 373 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 374 the corresponding certificates, and to include those certificates in the 375 FIP and FWU_FIP. 376 377 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 378 images will not include support for Trusted Board Boot. The FIP will still 379 include the corresponding certificates. This FIP can be used to verify the 380 Chain of Trust on the host machine through other mechanisms. 381 382 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 383 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 384 will not include the corresponding certificates, causing a boot failure. 385 386- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 387 inherent support for specific EL3 type interrupts. Setting this build option 388 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 389 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 390 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 391 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 392 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 393 the Secure Payload interrupts needs to be synchronously handed over to Secure 394 EL1 for handling. The default value of this option is ``0``, which means the 395 Group 0 interrupts are assumed to be handled by Secure EL1. 396 397- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 398 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 399 ``0`` (default), these exceptions will be trapped in the current exception 400 level (or in EL1 if the current exception level is EL0). 401 402- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 403 software operations are required for CPUs to enter and exit coherency. 404 However, newer systems exist where CPUs' entry to and exit from coherency 405 is managed in hardware. Such systems require software to only initiate these 406 operations, and the rest is managed in hardware, minimizing active software 407 management. In such systems, this boolean option enables TF-A to carry out 408 build and run-time optimizations during boot and power management operations. 409 This option defaults to 0 and if it is enabled, then it implies 410 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 411 412 If this flag is disabled while the platform which TF-A is compiled for 413 includes cores that manage coherency in hardware, then a compilation error is 414 generated. This is based on the fact that a system cannot have, at the same 415 time, cores that manage coherency in hardware and cores that don't. In other 416 words, a platform cannot have, at the same time, cores that require 417 ``HW_ASSISTED_COHERENCY=1`` and cores that require 418 ``HW_ASSISTED_COHERENCY=0``. 419 420 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 421 translation library (xlat tables v2) must be used; version 1 of translation 422 library is not supported. 423 424- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 425 bottom, higher addresses at the top. This build flag can be set to '1' to 426 invert this behavior. Lower addresses will be printed at the top and higher 427 addresses at the bottom. 428 429- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 430 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 431 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 432 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 433 images. 434 435- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 436 used for generating the PKCS keys and subsequent signing of the certificate. 437 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 438 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 439 compliant and is retained only for compatibility. The default value of this 440 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 441 442- ``KEY_SIZE``: This build flag enables the user to select the key size for 443 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 444 depend on the chosen algorithm and the cryptographic module. 445 446 +-----------+------------------------------------+ 447 | KEY_ALG | Possible key sizes | 448 +===========+====================================+ 449 | rsa | 1024 , 2048 (default), 3072, 4096* | 450 +-----------+------------------------------------+ 451 | ecdsa | unavailable | 452 +-----------+------------------------------------+ 453 454 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 455 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 456 457- ``HASH_ALG``: This build flag enables the user to select the secure hash 458 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 459 The default value of this flag is ``sha256``. 460 461- ``LDFLAGS``: Extra user options appended to the linkers' command line in 462 addition to the one set by the build system. 463 464- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 465 output compiled into the build. This should be one of the following: 466 467 :: 468 469 0 (LOG_LEVEL_NONE) 470 10 (LOG_LEVEL_ERROR) 471 20 (LOG_LEVEL_NOTICE) 472 30 (LOG_LEVEL_WARNING) 473 40 (LOG_LEVEL_INFO) 474 50 (LOG_LEVEL_VERBOSE) 475 476 All log output up to and including the selected log level is compiled into 477 the build. The default value is 40 in debug builds and 20 in release builds. 478 479- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 480 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well 481 in order to provide trust that the code taking the measurements and recording 482 them has not been tampered with. 483 484 This option defaults to 0. 485 486- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 487 specifies the file that contains the Non-Trusted World private key in PEM 488 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 489 490- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 491 optional. It is only needed if the platform makefile specifies that it 492 is required in order to build the ``fwu_fip`` target. 493 494- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 495 contents upon world switch. It can take either 0 (don't save and restore) or 496 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 497 wants the timer registers to be saved and restored. 498 499- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 500 for the BL image. It can be either 0 (include) or 1 (remove). The default 501 value is 0. 502 503- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 504 the underlying hardware is not a full PL011 UART but a minimally compliant 505 generic UART, which is a subset of the PL011. The driver will not access 506 any register that is not part of the SBSA generic UART specification. 507 Default value is 0 (a full PL011 compliant UART is present). 508 509- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 510 must be subdirectory of any depth under ``plat/``, and must contain a 511 platform makefile named ``platform.mk``. For example, to build TF-A for the 512 Arm Juno board, select PLAT=juno. 513 514- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 515 instead of the normal boot flow. When defined, it must specify the entry 516 point address for the preloaded BL33 image. This option is incompatible with 517 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 518 over ``PRELOADED_BL33_BASE``. 519 520- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 521 vector address can be programmed or is fixed on the platform. It can take 522 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 523 programmable reset address, it is expected that a CPU will start executing 524 code directly at the right address, both on a cold and warm reset. In this 525 case, there is no need to identify the entrypoint on boot and the boot path 526 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 527 does not need to be implemented in this case. 528 529- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 530 possible for the PSCI power-state parameter: original and extended State-ID 531 formats. This flag if set to 1, configures the generic PSCI layer to use the 532 extended format. The default value of this flag is 0, which means by default 533 the original power-state format is used by the PSCI implementation. This flag 534 should be specified by the platform makefile and it governs the return value 535 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 536 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 537 set to 1 as well. 538 539- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 540 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 541 or later CPUs. 542 543 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 544 set to ``1``. 545 546 This option is disabled by default. 547 548- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 549 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 550 entrypoint) or 1 (CPU reset to BL31 entrypoint). 551 The default value is 0. 552 553- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 554 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 555 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 556 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 557 558- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 559 file that contains the ROT private key in PEM format and enforces public key 560 hash generation. If ``SAVE_KEYS=1``, this 561 file name will be used to save the key. 562 563- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 564 certificate generation tool to save the keys used to establish the Chain of 565 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 566 567- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 568 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 569 target. 570 571- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 572 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 573 this file name will be used to save the key. 574 575- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 576 optional. It is only needed if the platform makefile specifies that it 577 is required in order to build the ``fwu_fip`` target. 578 579- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 580 Delegated Exception Interface to BL31 image. This defaults to ``0``. 581 582 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 583 set to ``1``. 584 585- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 586 isolated on separate memory pages. This is a trade-off between security and 587 memory usage. See "Isolating code and read-only data on separate memory 588 pages" section in :ref:`Firmware Design`. This flag is disabled by default 589 and affects all BL images. 590 591- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 592 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 593 allocated in RAM discontiguous from the loaded firmware image. When set, the 594 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 595 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 596 sections are placed in RAM immediately following the loaded firmware image. 597 598- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 599 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 600 UEFI+ACPI this can provide a certain amount of OS forward compatibility 601 with newer platforms that aren't ECAM compliant. 602 603- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 604 This build option is only valid if ``ARCH=aarch64``. The value should be 605 the path to the directory containing the SPD source, relative to 606 ``services/spd/``; the directory is expected to contain a makefile called 607 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 608 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 609 cannot be enabled when the ``SPM_MM`` option is enabled. 610 611- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 612 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 613 execution in BL1 just before handing over to BL31. At this point, all 614 firmware images have been loaded in memory, and the MMU and caches are 615 turned off. Refer to the "Debugging options" section for more details. 616 617- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 618 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 619 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 620 extension. This is the default when enabling the SPM Dispatcher. When 621 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 622 state. This latter configuration supports pre-Armv8.4 platforms (aka not 623 implementing the Armv8.4-SecEL2 extension). 624 625- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 626 Partition Manager (SPM) implementation. The default value is ``0`` 627 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 628 enabled (``SPD=spmd``). 629 630- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 631 description of secure partitions. The build system will parse this file and 632 package all secure partition blobs into the FIP. This file is not 633 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 634 635- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 636 secure interrupts (caught through the FIQ line). Platforms can enable 637 this directive if they need to handle such interruption. When enabled, 638 the FIQ are handled in monitor mode and non secure world is not allowed 639 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 640 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 641 642- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 643 Boot feature. When set to '1', BL1 and BL2 images include support to load 644 and verify the certificates and images in a FIP, and BL1 includes support 645 for the Firmware Update. The default value is '0'. Generation and inclusion 646 of certificates in the FIP and FWU_FIP depends upon the value of the 647 ``GENERATE_COT`` option. 648 649 .. warning:: 650 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 651 already exist in disk, they will be overwritten without further notice. 652 653- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 654 specifies the file that contains the Trusted World private key in PEM 655 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 656 657- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 658 synchronous, (see "Initializing a BL32 Image" section in 659 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 660 synchronous method) or 1 (BL32 is initialized using asynchronous method). 661 Default is 0. 662 663- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 664 routing model which routes non-secure interrupts asynchronously from TSP 665 to EL3 causing immediate preemption of TSP. The EL3 is responsible 666 for saving and restoring the TSP context in this routing model. The 667 default routing model (when the value is 0) is to route non-secure 668 interrupts to TSP allowing it to save its context and hand over 669 synchronously to EL3 via an SMC. 670 671 .. note:: 672 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 673 must also be set to ``1``. 674 675- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 676 linker. When the ``LINKER`` build variable points to the armlink linker, 677 this flag is enabled automatically. To enable support for armlink, platforms 678 will have to provide a scatter file for the BL image. Currently, Tegra 679 platforms use the armlink support to compile BL3-1 images. 680 681- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 682 memory region in the BL memory map or not (see "Use of Coherent memory in 683 TF-A" section in :ref:`Firmware Design`). It can take the value 1 684 (Coherent memory region is included) or 0 (Coherent memory region is 685 excluded). Default is 1. 686 687- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 688 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 689 Default is 0. 690 691- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 692 firmware configuration framework. This will move the io_policies into a 693 configuration device tree, instead of static structure in the code base. 694 695- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 696 at runtime using fconf. If this flag is enabled, COT descriptors are 697 statically captured in tb_fw_config file in the form of device tree nodes 698 and properties. Currently, COT descriptors used by BL2 are moved to the 699 device tree and COT descriptors used by BL1 are retained in the code 700 base statically. 701 702- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 703 runtime using firmware configuration framework. The platform specific SDEI 704 shared and private events configuration is retrieved from device tree rather 705 than static C structures at compile time. This is only supported if 706 SDEI_SUPPORT build flag is enabled. 707 708- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 709 and Group1 secure interrupts using the firmware configuration framework. The 710 platform specific secure interrupt property descriptor is retrieved from 711 device tree in runtime rather than depending on static C structure at compile 712 time. 713 714- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 715 This feature creates a library of functions to be placed in ROM and thus 716 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 717 is 0. 718 719- ``V``: Verbose build. If assigned anything other than 0, the build commands 720 are printed. Default is 0. 721 722- ``VERSION_STRING``: String used in the log output for each TF-A image. 723 Defaults to a string formed by concatenating the version number, build type 724 and build string. 725 726- ``W``: Warning level. Some compiler warning options of interest have been 727 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 728 each level enabling more warning options. Default is 0. 729 730- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 731 the CPU after warm boot. This is applicable for platforms which do not 732 require interconnect programming to enable cache coherency (eg: single 733 cluster platforms). If this option is enabled, then warm boot path 734 enables D-caches immediately after enabling MMU. This option defaults to 0. 735 736- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 737 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 738 default value of this flag is ``no``. Note this option must be enabled only 739 for ARM architecture greater than Armv8.5-A. 740 741- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 742 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 743 The default value of this flag is ``0``. 744 745 ``AT`` speculative errata workaround disables stage1 page table walk for 746 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 747 produces either the correct result or failure without TLB allocation. 748 749 This boolean option enables errata for all below CPUs. 750 751 +---------+--------------+-------------------------+ 752 | Errata | CPU | Workaround Define | 753 +=========+==============+=========================+ 754 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 755 +---------+--------------+-------------------------+ 756 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 757 +---------+--------------+-------------------------+ 758 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 759 +---------+--------------+-------------------------+ 760 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 761 +---------+--------------+-------------------------+ 762 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 763 +---------+--------------+-------------------------+ 764 765 .. note:: 766 This option is enabled by build only if platform sets any of above defines 767 mentioned in ’Workaround Define' column in the table. 768 If this option is enabled for the EL3 software then EL2 software also must 769 implement this workaround due to the behaviour of the errata mentioned 770 in new SDEN document which will get published soon. 771 772- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 773 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 774 This flag is disabled by default. 775 776- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 777 path on the host machine which is used to build certificate generation and 778 firmware encryption tool. 779 780- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 781 functions that wait for an arbitrary time length (udelay and mdelay). The 782 default value is 0. 783 784- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer 785 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 786 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 787 feature for AArch64. The default is 0 and it is automatically disabled when 788 the target architecture is AArch32. 789 790- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 791 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 792 but unused). This feature is available if trace unit such as ETMv4.x, and 793 ETE(extending ETM feature) is implemented. This flag is disabled by default. 794 795- ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers 796 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 797 if FEAT_TRF is implemented. This flag is disabled by default. 798 799GICv3 driver options 800-------------------- 801 802GICv3 driver files are included using directive: 803 804``include drivers/arm/gic/v3/gicv3.mk`` 805 806The driver can be configured with the following options set in the platform 807makefile: 808 809- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 810 Enabling this option will add runtime detection support for the 811 GIC-600, so is safe to select even for a GIC500 implementation. 812 This option defaults to 0. 813 814- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 815 for GIC-600 AE. Enabling this option will introduce support to initialize 816 the FMU. Platforms should call the init function during boot to enable the 817 FMU and its safety mechanisms. This option defaults to 0. 818 819- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 820 functionality. This option defaults to 0 821 822- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 823 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 824 functions. This is required for FVP platform which need to simulate GIC save 825 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 826 827- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 828 This option defaults to 0. 829 830- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 831 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 832 833Debugging options 834----------------- 835 836To compile a debug version and make the build more verbose use 837 838.. code:: shell 839 840 make PLAT=<platform> DEBUG=1 V=1 all 841 842AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 843example DS-5) might not support this and may need an older version of DWARF 844symbols to be emitted by GCC. This can be achieved by using the 845``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 846version to 2 is recommended for DS-5 versions older than 5.16. 847 848When debugging logic problems it might also be useful to disable all compiler 849optimizations by using ``-O0``. 850 851.. warning:: 852 Using ``-O0`` could cause output images to be larger and base addresses 853 might need to be recalculated (see the **Memory layout on Arm development 854 platforms** section in the :ref:`Firmware Design`). 855 856Extra debug options can be passed to the build system by setting ``CFLAGS`` or 857``LDFLAGS``: 858 859.. code:: shell 860 861 CFLAGS='-O0 -gdwarf-2' \ 862 make PLAT=<platform> DEBUG=1 V=1 all 863 864Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 865ignored as the linker is called directly. 866 867It is also possible to introduce an infinite loop to help in debugging the 868post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 869``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 870section. In this case, the developer may take control of the target using a 871debugger when indicated by the console output. When using DS-5, the following 872commands can be used: 873 874:: 875 876 # Stop target execution 877 interrupt 878 879 # 880 # Prepare your debugging environment, e.g. set breakpoints 881 # 882 883 # Jump over the debug loop 884 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 885 886 # Resume execution 887 continue 888 889Firmware update options 890----------------------- 891 892- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 893 in defining the firmware update metadata structure. This flag is by default 894 set to '2'. 895 896- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 897 firmware bank. Each firmware bank must have the same number of images as per 898 the `PSA FW update specification`_. 899 This flag is used in defining the firmware update metadata structure. This 900 flag is by default set to '1'. 901 902- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 903 `PSA FW update specification`_. The default value is 0, and this is an 904 experimental feature. 905 PSA firmware update implementation has some limitations, such as BL2 is 906 not part of the protocol-updatable images, if BL2 needs to be updated, then 907 it should be done through another platform-defined mechanism, and it assumes 908 that the platform's hardware supports CRC32 instructions. 909 910-------------- 911 912*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* 913 914.. _DEN0115: https://developer.arm.com/docs/den0115/latest 915.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 916 917