1/* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <context.h> 13#include <lib/xlat_tables/xlat_tables_defs.h> 14 15 /* 16 * Helper macro to initialise EL3 registers we care about. 17 */ 18 .macro el3_arch_init_common 19 /* --------------------------------------------------------------------- 20 * SCTLR_EL3 has already been initialised - read current value before 21 * modifying. 22 * 23 * SCTLR_EL3.I: Enable the instruction cache. 24 * 25 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 26 * exception is generated if a load or store instruction executed at 27 * EL3 uses the SP as the base address and the SP is not aligned to a 28 * 16-byte boundary. 29 * 30 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 31 * load or store one or more registers have an alignment check that the 32 * address being accessed is aligned to the size of the data element(s) 33 * being accessed. 34 * --------------------------------------------------------------------- 35 */ 36 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 37 mrs x0, sctlr_el3 38 orr x0, x0, x1 39 msr sctlr_el3, x0 40 isb 41 42#ifdef IMAGE_BL31 43 /* --------------------------------------------------------------------- 44 * Initialise the per-cpu cache pointer to the CPU. 45 * This is done early to enable crash reporting to have access to crash 46 * stack. Since crash reporting depends on cpu_data to report the 47 * unhandled exception, not doing so can lead to recursive exceptions 48 * due to a NULL TPIDR_EL3. 49 * --------------------------------------------------------------------- 50 */ 51 bl init_cpu_data_ptr 52#endif /* IMAGE_BL31 */ 53 54 /* --------------------------------------------------------------------- 55 * Initialise SCR_EL3, setting all fields rather than relying on hw. 56 * All fields are architecturally UNKNOWN on reset. The following fields 57 * do not change during the TF lifetime. The remaining fields are set to 58 * zero here but are updated ahead of transitioning to a lower EL in the 59 * function cm_init_context_common(). 60 * 61 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 62 * EL2, EL1 and EL0 are not trapped to EL3. 63 * 64 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 65 * EL2, EL1 and EL0 are not trapped to EL3. 66 * 67 * SCR_EL3.SIF: Set to one to disable instruction fetches from 68 * Non-secure memory. 69 * 70 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 71 * both Security states and both Execution states. 72 * 73 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 74 * to EL3 when executing at any EL. 75 * 76 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 77 * disable traps to EL3 when accessing key registers or using pointer 78 * authentication instructions from lower ELs. 79 * --------------------------------------------------------------------- 80 */ 81 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 82 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 83#if CTX_INCLUDE_PAUTH_REGS 84 /* 85 * If the pointer authentication registers are saved during world 86 * switches, enable pointer authentication everywhere, as it is safe to 87 * do so. 88 */ 89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 90#endif 91 msr scr_el3, x0 92 93 /* --------------------------------------------------------------------- 94 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 95 * Some fields are architecturally UNKNOWN on reset. 96 * 97 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 98 * Debug exceptions, other than Breakpoint Instruction exceptions, are 99 * disabled from all ELs in Secure state. 100 * 101 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 102 * privileged debug from S-EL1. 103 * 104 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 105 * access to the powerdown debug registers do not trap to EL3. 106 * 107 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 108 * debug registers, other than those registers that are controlled by 109 * MDCR_EL3.TDOSA. 110 * 111 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 112 * accesses to all Performance Monitors registers do not trap to EL3. 113 * 114 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 115 * prohibited in Secure state. This bit is RES0 in versions of the 116 * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 117 * doesn't have any effect on them. 118 * 119 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 120 * prohibited in EL3. This bit is RES0 in versions of the 121 * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 122 * doesn't have any effect on them. 123 * 124 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 125 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 126 * Debug is not implemented this bit does not have any effect on the 127 * counters unless there is support for the implementation defined 128 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 129 * 130 * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer 131 * owning security state is Secure state. If FEAT_TRBE is implemented, 132 * accesses to Trace Buffer control registers at EL2 and EL1 in any 133 * security state generates trap exceptions to EL3. 134 * If FEAT_TRBE is not implemented, these bits are RES0. 135 * 136 * MDCR_EL3.TTRF: Set to one so that access to trace filter control 137 * registers in non-monitor mode generate EL3 trap exception, 138 * unless the access generates a higher priority exception when trace 139 * filter control(FEAT_TRF) is implemented. 140 * When FEAT_TRF is not implemented, this bit is RES0. 141 * --------------------------------------------------------------------- 142 */ 143 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 144 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ 145 MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ 146 MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \ 147 MDCR_NSTBE | MDCR_TTRF_BIT)) 148 149 mrs x1, id_aa64dfr0_el1 150 ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH 151 cbz x1, 1f 152 orr x0, x0, #MDCR_TTRF_BIT 1531: 154 msr mdcr_el3, x0 155 156 /* --------------------------------------------------------------------- 157 * Initialise PMCR_EL0 setting all fields rather than relying 158 * on hw. Some fields are architecturally UNKNOWN on reset. 159 * 160 * PMCR_EL0.LP: Set to one so that event counter overflow, that 161 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 162 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 163 * is implemented. This bit is RES0 in versions of the architecture 164 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 165 * on them. 166 * 167 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 168 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 169 * that changes PMCCNTR_EL0[63] from 1 to 0. 170 * 171 * PMCR_EL0.DP: Set to one so that the cycle counter, 172 * PMCCNTR_EL0 does not count when event counting is prohibited. 173 * 174 * PMCR_EL0.X: Set to zero to disable export of events. 175 * 176 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 177 * counts on every clock cycle. 178 * --------------------------------------------------------------------- 179 */ 180 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 181 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 182 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 183 184 msr pmcr_el0, x0 185 186 /* --------------------------------------------------------------------- 187 * Enable External Aborts and SError Interrupts now that the exception 188 * vectors have been setup. 189 * --------------------------------------------------------------------- 190 */ 191 msr daifclr, #DAIF_ABT_BIT 192 193 /* --------------------------------------------------------------------- 194 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 195 * All fields are architecturally UNKNOWN on reset. 196 * 197 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 198 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 199 * 200 * CPTR_EL3.TTA: Set to one so that accesses to the trace system 201 * registers trap to EL3 from all exception levels and security 202 * states when system register trace is implemented. 203 * When system register trace is not implemented, this bit is RES0 and 204 * hence set to zero. 205 * 206 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 207 * trace registers do not trap to EL3. 208 * 209 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 210 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 211 * do not trap to EL3. 212 * 213 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is 214 * trapped to EL3 by default. 215 * 216 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped 217 * to EL3 by default. 218 */ 219 220 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 221 mrs x1, id_aa64dfr0_el1 222 ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH 223 cbz x1, 1f 224 orr x0, x0, #TTA_BIT 2251: 226 msr cptr_el3, x0 227 228 /* 229 * If Data Independent Timing (DIT) functionality is implemented, 230 * always enable DIT in EL3 231 */ 232 mrs x0, id_aa64pfr0_el1 233 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 234 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 235 bne 1f 236 mov x0, #DIT_BIT 237 msr DIT, x0 2381: 239 .endm 240 241/* ----------------------------------------------------------------------------- 242 * This is the super set of actions that need to be performed during a cold boot 243 * or a warm boot in EL3. This code is shared by BL1 and BL31. 244 * 245 * This macro will always perform reset handling, architectural initialisations 246 * and stack setup. The rest of the actions are optional because they might not 247 * be needed, depending on the context in which this macro is called. This is 248 * why this macro is parameterised ; each parameter allows to enable/disable 249 * some actions. 250 * 251 * _init_sctlr: 252 * Whether the macro needs to initialise SCTLR_EL3, including configuring 253 * the endianness of data accesses. 254 * 255 * _warm_boot_mailbox: 256 * Whether the macro needs to detect the type of boot (cold/warm). The 257 * detection is based on the platform entrypoint address : if it is zero 258 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 259 * this macro jumps on the platform entrypoint address. 260 * 261 * _secondary_cold_boot: 262 * Whether the macro needs to identify the CPU that is calling it: primary 263 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 264 * the platform initialisations, while the secondaries will be put in a 265 * platform-specific state in the meantime. 266 * 267 * If the caller knows this macro will only be called by the primary CPU 268 * then this parameter can be defined to 0 to skip this step. 269 * 270 * _init_memory: 271 * Whether the macro needs to initialise the memory. 272 * 273 * _init_c_runtime: 274 * Whether the macro needs to initialise the C runtime environment. 275 * 276 * _exception_vectors: 277 * Address of the exception vectors to program in the VBAR_EL3 register. 278 * 279 * _pie_fixup_size: 280 * Size of memory region to fixup Global Descriptor Table (GDT). 281 * 282 * A non-zero value is expected when firmware needs GDT to be fixed-up. 283 * 284 * ----------------------------------------------------------------------------- 285 */ 286 .macro el3_entrypoint_common \ 287 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 288 _init_memory, _init_c_runtime, _exception_vectors, \ 289 _pie_fixup_size 290 291 .if \_init_sctlr 292 /* ------------------------------------------------------------- 293 * This is the initialisation of SCTLR_EL3 and so must ensure 294 * that all fields are explicitly set rather than relying on hw. 295 * Some fields reset to an IMPLEMENTATION DEFINED value and 296 * others are architecturally UNKNOWN on reset. 297 * 298 * SCTLR.EE: Set the CPU endianness before doing anything that 299 * might involve memory reads or writes. Set to zero to select 300 * Little Endian. 301 * 302 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 303 * force all memory regions that are writeable to be treated as 304 * XN (Execute-never). Set to zero so that this control has no 305 * effect on memory access permissions. 306 * 307 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 308 * 309 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 310 * 311 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 312 * safe behaviour upon exception entry to EL3. 313 * ------------------------------------------------------------- 314 */ 315 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 316 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 317 msr sctlr_el3, x0 318 isb 319 .endif /* _init_sctlr */ 320 321#if DISABLE_MTPMU 322 bl mtpmu_disable 323#endif 324 325 .if \_warm_boot_mailbox 326 /* ------------------------------------------------------------- 327 * This code will be executed for both warm and cold resets. 328 * Now is the time to distinguish between the two. 329 * Query the platform entrypoint address and if it is not zero 330 * then it means it is a warm boot so jump to this address. 331 * ------------------------------------------------------------- 332 */ 333 bl plat_get_my_entrypoint 334 cbz x0, do_cold_boot 335 br x0 336 337 do_cold_boot: 338 .endif /* _warm_boot_mailbox */ 339 340 .if \_pie_fixup_size 341#if ENABLE_PIE 342 /* 343 * ------------------------------------------------------------ 344 * If PIE is enabled fixup the Global descriptor Table only 345 * once during primary core cold boot path. 346 * 347 * Compile time base address, required for fixup, is calculated 348 * using "pie_fixup" label present within first page. 349 * ------------------------------------------------------------ 350 */ 351 pie_fixup: 352 ldr x0, =pie_fixup 353 and x0, x0, #~(PAGE_SIZE_MASK) 354 mov_imm x1, \_pie_fixup_size 355 add x1, x1, x0 356 bl fixup_gdt_reloc 357#endif /* ENABLE_PIE */ 358 .endif /* _pie_fixup_size */ 359 360 /* --------------------------------------------------------------------- 361 * Set the exception vectors. 362 * --------------------------------------------------------------------- 363 */ 364 adr x0, \_exception_vectors 365 msr vbar_el3, x0 366 isb 367 368 /* --------------------------------------------------------------------- 369 * It is a cold boot. 370 * Perform any processor specific actions upon reset e.g. cache, TLB 371 * invalidations etc. 372 * --------------------------------------------------------------------- 373 */ 374 bl reset_handler 375 376 el3_arch_init_common 377 378 .if \_secondary_cold_boot 379 /* ------------------------------------------------------------- 380 * Check if this is a primary or secondary CPU cold boot. 381 * The primary CPU will set up the platform while the 382 * secondaries are placed in a platform-specific state until the 383 * primary CPU performs the necessary actions to bring them out 384 * of that state and allows entry into the OS. 385 * ------------------------------------------------------------- 386 */ 387 bl plat_is_my_cpu_primary 388 cbnz w0, do_primary_cold_boot 389 390 /* This is a cold boot on a secondary CPU */ 391 bl plat_secondary_cold_boot_setup 392 /* plat_secondary_cold_boot_setup() is not supposed to return */ 393 bl el3_panic 394 395 do_primary_cold_boot: 396 .endif /* _secondary_cold_boot */ 397 398 /* --------------------------------------------------------------------- 399 * Initialize memory now. Secondary CPU initialization won't get to this 400 * point. 401 * --------------------------------------------------------------------- 402 */ 403 404 .if \_init_memory 405 bl platform_mem_init 406 .endif /* _init_memory */ 407 408 /* --------------------------------------------------------------------- 409 * Init C runtime environment: 410 * - Zero-initialise the NOBITS sections. There are 2 of them: 411 * - the .bss section; 412 * - the coherent memory section (if any). 413 * - Relocate the data section from ROM to RAM, if required. 414 * --------------------------------------------------------------------- 415 */ 416 .if \_init_c_runtime 417#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) 418 /* ------------------------------------------------------------- 419 * Invalidate the RW memory used by the BL31 image. This 420 * includes the data and NOBITS sections. This is done to 421 * safeguard against possible corruption of this memory by 422 * dirty cache lines in a system cache as a result of use by 423 * an earlier boot loader stage. 424 * ------------------------------------------------------------- 425 */ 426 adrp x0, __RW_START__ 427 add x0, x0, :lo12:__RW_START__ 428 adrp x1, __RW_END__ 429 add x1, x1, :lo12:__RW_END__ 430 sub x1, x1, x0 431 bl inv_dcache_range 432#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 433 adrp x0, __NOBITS_START__ 434 add x0, x0, :lo12:__NOBITS_START__ 435 adrp x1, __NOBITS_END__ 436 add x1, x1, :lo12:__NOBITS_END__ 437 sub x1, x1, x0 438 bl inv_dcache_range 439#endif 440#endif 441 adrp x0, __BSS_START__ 442 add x0, x0, :lo12:__BSS_START__ 443 444 adrp x1, __BSS_END__ 445 add x1, x1, :lo12:__BSS_END__ 446 sub x1, x1, x0 447 bl zeromem 448 449#if USE_COHERENT_MEM 450 adrp x0, __COHERENT_RAM_START__ 451 add x0, x0, :lo12:__COHERENT_RAM_START__ 452 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 453 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 454 sub x1, x1, x0 455 bl zeromem 456#endif 457 458#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) 459 adrp x0, __DATA_RAM_START__ 460 add x0, x0, :lo12:__DATA_RAM_START__ 461 adrp x1, __DATA_ROM_START__ 462 add x1, x1, :lo12:__DATA_ROM_START__ 463 adrp x2, __DATA_RAM_END__ 464 add x2, x2, :lo12:__DATA_RAM_END__ 465 sub x2, x2, x0 466 bl memcpy16 467#endif 468 .endif /* _init_c_runtime */ 469 470 /* --------------------------------------------------------------------- 471 * Use SP_EL0 for the C runtime stack. 472 * --------------------------------------------------------------------- 473 */ 474 msr spsel, #0 475 476 /* --------------------------------------------------------------------- 477 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 478 * the MMU is enabled. There is no risk of reading stale stack memory 479 * after enabling the MMU as only the primary CPU is running at the 480 * moment. 481 * --------------------------------------------------------------------- 482 */ 483 bl plat_set_my_stack 484 485#if STACK_PROTECTOR_ENABLED 486 .if \_init_c_runtime 487 bl update_stack_protector_canary 488 .endif /* _init_c_runtime */ 489#endif 490 .endm 491 492 .macro apply_at_speculative_wa 493#if ERRATA_SPECULATIVE_AT 494 /* 495 * Explicitly save x30 so as to free up a register and to enable 496 * branching and also, save x29 which will be used in the called 497 * function 498 */ 499 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 500 bl save_and_update_ptw_el1_sys_regs 501 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 502#endif 503 .endm 504 505 .macro restore_ptw_el1_sys_regs 506#if ERRATA_SPECULATIVE_AT 507 /* ----------------------------------------------------------- 508 * In case of ERRATA_SPECULATIVE_AT, must follow below order 509 * to ensure that page table walk is not enabled until 510 * restoration of all EL1 system registers. TCR_EL1 register 511 * should be updated at the end which restores previous page 512 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 513 * ensures that CPU does below steps in order. 514 * 515 * 1. Ensure all other system registers are written before 516 * updating SCTLR_EL1 using ISB. 517 * 2. Restore SCTLR_EL1 register. 518 * 3. Ensure SCTLR_EL1 written successfully using ISB. 519 * 4. Restore TCR_EL1 register. 520 * ----------------------------------------------------------- 521 */ 522 isb 523 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 524 msr sctlr_el1, x28 525 isb 526 msr tcr_el1, x29 527#endif 528 .endm 529 530#endif /* EL3_COMMON_MACROS_S */ 531