1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 U(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 168 #define ID_AA64PFR0_GIC_SHIFT U(24) 169 #define ID_AA64PFR0_GIC_WIDTH U(4) 170 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 171 #define ID_AA64PFR0_SVE_SHIFT U(32) 172 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 173 #define ID_AA64PFR0_SVE_LENGTH U(4) 174 #define ID_AA64PFR0_SEL2_SHIFT U(36) 175 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 176 #define ID_AA64PFR0_MPAM_SHIFT U(40) 177 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 178 #define ID_AA64PFR0_DIT_SHIFT U(48) 179 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 180 #define ID_AA64PFR0_DIT_LENGTH U(4) 181 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 182 #define ID_AA64PFR0_CSV2_SHIFT U(56) 183 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 184 #define ID_AA64PFR0_CSV2_LENGTH U(4) 185 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 186 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 187 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 188 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 189 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 190 191 /* Exception level handling */ 192 #define EL_IMPL_NONE ULL(0) 193 #define EL_IMPL_A64ONLY ULL(1) 194 #define EL_IMPL_A64_A32 ULL(2) 195 196 /* ID_AA64DFR0_EL1.TraceVer definitions */ 197 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 198 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 199 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 200 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 201 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 202 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 203 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 204 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 205 206 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 207 #define ID_AA64DFR0_PMS_SHIFT U(32) 208 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 209 210 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 211 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 212 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 213 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 214 215 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 216 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 217 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 218 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 219 220 /* ID_AA64ISAR0_EL1 definitions */ 221 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 222 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 223 224 /* ID_AA64ISAR1_EL1 definitions */ 225 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 226 #define ID_AA64ISAR1_GPI_SHIFT U(28) 227 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 228 #define ID_AA64ISAR1_GPA_SHIFT U(24) 229 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 230 #define ID_AA64ISAR1_API_SHIFT U(8) 231 #define ID_AA64ISAR1_API_MASK ULL(0xf) 232 #define ID_AA64ISAR1_APA_SHIFT U(4) 233 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 234 235 /* ID_AA64MMFR0_EL1 definitions */ 236 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 237 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 238 239 #define PARANGE_0000 U(32) 240 #define PARANGE_0001 U(36) 241 #define PARANGE_0010 U(40) 242 #define PARANGE_0011 U(42) 243 #define PARANGE_0100 U(44) 244 #define PARANGE_0101 U(48) 245 #define PARANGE_0110 U(52) 246 247 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 248 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 249 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 250 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 251 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 252 253 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 254 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 255 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 256 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 257 258 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 259 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 260 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 261 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 262 263 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 264 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 265 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 266 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 267 268 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 269 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 270 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 271 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 272 273 /* ID_AA64MMFR1_EL1 definitions */ 274 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 275 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 276 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 277 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 278 279 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 280 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 281 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 282 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 283 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 284 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 285 286 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 287 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 288 289 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 290 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 291 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 292 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 293 294 /* ID_AA64MMFR2_EL1 definitions */ 295 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 296 297 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 298 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 299 300 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 301 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 302 303 /* ID_AA64PFR1_EL1 definitions */ 304 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 305 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 306 307 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 308 309 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 310 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 311 312 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 313 314 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 315 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 316 317 /* Memory Tagging Extension is not implemented */ 318 #define MTE_UNIMPLEMENTED U(0) 319 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 320 #define MTE_IMPLEMENTED_EL0 U(1) 321 /* FEAT_MTE2: Full MTE is implemented */ 322 #define MTE_IMPLEMENTED_ELX U(2) 323 /* 324 * FEAT_MTE3: MTE is implemented with support for 325 * asymmetric Tag Check Fault handling 326 */ 327 #define MTE_IMPLEMENTED_ASY U(3) 328 329 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 330 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 331 332 /* ID_PFR1_EL1 definitions */ 333 #define ID_PFR1_VIRTEXT_SHIFT U(12) 334 #define ID_PFR1_VIRTEXT_MASK U(0xf) 335 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 336 & ID_PFR1_VIRTEXT_MASK) 337 338 /* SCTLR definitions */ 339 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 340 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 341 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 342 343 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 344 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 345 346 #define SCTLR_AARCH32_EL1_RES1 \ 347 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 348 (U(1) << 4) | (U(1) << 3)) 349 350 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 351 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 352 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 353 354 #define SCTLR_M_BIT (ULL(1) << 0) 355 #define SCTLR_A_BIT (ULL(1) << 1) 356 #define SCTLR_C_BIT (ULL(1) << 2) 357 #define SCTLR_SA_BIT (ULL(1) << 3) 358 #define SCTLR_SA0_BIT (ULL(1) << 4) 359 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 360 #define SCTLR_nAA_BIT (ULL(1) << 6) 361 #define SCTLR_ITD_BIT (ULL(1) << 7) 362 #define SCTLR_SED_BIT (ULL(1) << 8) 363 #define SCTLR_UMA_BIT (ULL(1) << 9) 364 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 365 #define SCTLR_EOS_BIT (ULL(1) << 11) 366 #define SCTLR_I_BIT (ULL(1) << 12) 367 #define SCTLR_EnDB_BIT (ULL(1) << 13) 368 #define SCTLR_DZE_BIT (ULL(1) << 14) 369 #define SCTLR_UCT_BIT (ULL(1) << 15) 370 #define SCTLR_NTWI_BIT (ULL(1) << 16) 371 #define SCTLR_NTWE_BIT (ULL(1) << 18) 372 #define SCTLR_WXN_BIT (ULL(1) << 19) 373 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 374 #define SCTLR_IESB_BIT (ULL(1) << 21) 375 #define SCTLR_EIS_BIT (ULL(1) << 22) 376 #define SCTLR_SPAN_BIT (ULL(1) << 23) 377 #define SCTLR_E0E_BIT (ULL(1) << 24) 378 #define SCTLR_EE_BIT (ULL(1) << 25) 379 #define SCTLR_UCI_BIT (ULL(1) << 26) 380 #define SCTLR_EnDA_BIT (ULL(1) << 27) 381 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 382 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 383 #define SCTLR_EnIB_BIT (ULL(1) << 30) 384 #define SCTLR_EnIA_BIT (ULL(1) << 31) 385 #define SCTLR_BT0_BIT (ULL(1) << 35) 386 #define SCTLR_BT1_BIT (ULL(1) << 36) 387 #define SCTLR_BT_BIT (ULL(1) << 36) 388 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 389 #define SCTLR_TCF0_SHIFT U(38) 390 #define SCTLR_TCF0_MASK ULL(3) 391 392 /* Tag Check Faults in EL0 have no effect on the PE */ 393 #define SCTLR_TCF0_NO_EFFECT U(0) 394 /* Tag Check Faults in EL0 cause a synchronous exception */ 395 #define SCTLR_TCF0_SYNC U(1) 396 /* Tag Check Faults in EL0 are asynchronously accumulated */ 397 #define SCTLR_TCF0_ASYNC U(2) 398 /* 399 * Tag Check Faults in EL0 cause a synchronous exception on reads, 400 * and are asynchronously accumulated on writes 401 */ 402 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 403 404 #define SCTLR_TCF_SHIFT U(40) 405 #define SCTLR_TCF_MASK ULL(3) 406 407 /* Tag Check Faults in EL1 have no effect on the PE */ 408 #define SCTLR_TCF_NO_EFFECT U(0) 409 /* Tag Check Faults in EL1 cause a synchronous exception */ 410 #define SCTLR_TCF_SYNC U(1) 411 /* Tag Check Faults in EL1 are asynchronously accumulated */ 412 #define SCTLR_TCF_ASYNC U(2) 413 /* 414 * Tag Check Faults in EL1 cause a synchronous exception on reads, 415 * and are asynchronously accumulated on writes 416 */ 417 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 418 419 #define SCTLR_ATA0_BIT (ULL(1) << 42) 420 #define SCTLR_ATA_BIT (ULL(1) << 43) 421 #define SCTLR_DSSBS_SHIFT U(44) 422 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 423 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 424 #define SCTLR_TWEDEL_SHIFT U(46) 425 #define SCTLR_TWEDEL_MASK ULL(0xf) 426 #define SCTLR_EnASR_BIT (ULL(1) << 54) 427 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 428 #define SCTLR_EnALS_BIT (ULL(1) << 56) 429 #define SCTLR_EPAN_BIT (ULL(1) << 57) 430 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 431 432 /* CPACR_EL1 definitions */ 433 #define CPACR_EL1_FPEN(x) ((x) << 20) 434 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 435 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 436 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 437 438 /* SCR definitions */ 439 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 440 #define SCR_NSE_SHIFT U(62) 441 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 442 #define SCR_GPF_BIT (UL(1) << 48) 443 #define SCR_TWEDEL_SHIFT U(30) 444 #define SCR_TWEDEL_MASK ULL(0xf) 445 #define SCR_HXEn_BIT (UL(1) << 38) 446 #define SCR_AMVOFFEN_BIT (UL(1) << 35) 447 #define SCR_TWEDEn_BIT (UL(1) << 29) 448 #define SCR_ECVEN_BIT (UL(1) << 28) 449 #define SCR_FGTEN_BIT (UL(1) << 27) 450 #define SCR_ATA_BIT (UL(1) << 26) 451 #define SCR_EnSCXT_BIT (UL(1) << 25) 452 #define SCR_FIEN_BIT (UL(1) << 21) 453 #define SCR_EEL2_BIT (UL(1) << 18) 454 #define SCR_API_BIT (UL(1) << 17) 455 #define SCR_APK_BIT (UL(1) << 16) 456 #define SCR_TERR_BIT (UL(1) << 15) 457 #define SCR_TWE_BIT (UL(1) << 13) 458 #define SCR_TWI_BIT (UL(1) << 12) 459 #define SCR_ST_BIT (UL(1) << 11) 460 #define SCR_RW_BIT (UL(1) << 10) 461 #define SCR_SIF_BIT (UL(1) << 9) 462 #define SCR_HCE_BIT (UL(1) << 8) 463 #define SCR_SMD_BIT (UL(1) << 7) 464 #define SCR_EA_BIT (UL(1) << 3) 465 #define SCR_FIQ_BIT (UL(1) << 2) 466 #define SCR_IRQ_BIT (UL(1) << 1) 467 #define SCR_NS_BIT (UL(1) << 0) 468 #define SCR_VALID_BIT_MASK U(0x2f8f) 469 #define SCR_RESET_VAL SCR_RES1_BITS 470 471 /* MDCR_EL3 definitions */ 472 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 473 #define MDCR_MPMX_BIT (ULL(1) << 35) 474 #define MDCR_MCCD_BIT (ULL(1) << 34) 475 #define MDCR_NSTB(x) ((x) << 24) 476 #define MDCR_NSTB_EL1 ULL(0x3) 477 #define MDCR_NSTBE (ULL(1) << 26) 478 #define MDCR_MTPME_BIT (ULL(1) << 28) 479 #define MDCR_TDCC_BIT (ULL(1) << 27) 480 #define MDCR_SCCD_BIT (ULL(1) << 23) 481 #define MDCR_EPMAD_BIT (ULL(1) << 21) 482 #define MDCR_EDAD_BIT (ULL(1) << 20) 483 #define MDCR_TTRF_BIT (ULL(1) << 19) 484 #define MDCR_STE_BIT (ULL(1) << 18) 485 #define MDCR_SPME_BIT (ULL(1) << 17) 486 #define MDCR_SDD_BIT (ULL(1) << 16) 487 #define MDCR_SPD32(x) ((x) << 14) 488 #define MDCR_SPD32_LEGACY ULL(0x0) 489 #define MDCR_SPD32_DISABLE ULL(0x2) 490 #define MDCR_SPD32_ENABLE ULL(0x3) 491 #define MDCR_NSPB(x) ((x) << 12) 492 #define MDCR_NSPB_EL1 ULL(0x3) 493 #define MDCR_TDOSA_BIT (ULL(1) << 10) 494 #define MDCR_TDA_BIT (ULL(1) << 9) 495 #define MDCR_TPM_BIT (ULL(1) << 6) 496 #define MDCR_EL3_RESET_VAL ULL(0x0) 497 498 /* MDCR_EL2 definitions */ 499 #define MDCR_EL2_MTPME (U(1) << 28) 500 #define MDCR_EL2_HLP (U(1) << 26) 501 #define MDCR_EL2_E2TB(x) ((x) << 24) 502 #define MDCR_EL2_E2TB_EL1 U(0x3) 503 #define MDCR_EL2_HCCD (U(1) << 23) 504 #define MDCR_EL2_TTRF (U(1) << 19) 505 #define MDCR_EL2_HPMD (U(1) << 17) 506 #define MDCR_EL2_TPMS (U(1) << 14) 507 #define MDCR_EL2_E2PB(x) ((x) << 12) 508 #define MDCR_EL2_E2PB_EL1 U(0x3) 509 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 510 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 511 #define MDCR_EL2_TDA_BIT (U(1) << 9) 512 #define MDCR_EL2_TDE_BIT (U(1) << 8) 513 #define MDCR_EL2_HPME_BIT (U(1) << 7) 514 #define MDCR_EL2_TPM_BIT (U(1) << 6) 515 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 516 #define MDCR_EL2_RESET_VAL U(0x0) 517 518 /* HSTR_EL2 definitions */ 519 #define HSTR_EL2_RESET_VAL U(0x0) 520 #define HSTR_EL2_T_MASK U(0xff) 521 522 /* CNTHP_CTL_EL2 definitions */ 523 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 524 #define CNTHP_CTL_RESET_VAL U(0x0) 525 526 /* VTTBR_EL2 definitions */ 527 #define VTTBR_RESET_VAL ULL(0x0) 528 #define VTTBR_VMID_MASK ULL(0xff) 529 #define VTTBR_VMID_SHIFT U(48) 530 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 531 #define VTTBR_BADDR_SHIFT U(0) 532 533 /* HCR definitions */ 534 #define HCR_RESET_VAL ULL(0x0) 535 #define HCR_AMVOFFEN_BIT (ULL(1) << 51) 536 #define HCR_TEA_BIT (ULL(1) << 47) 537 #define HCR_API_BIT (ULL(1) << 41) 538 #define HCR_APK_BIT (ULL(1) << 40) 539 #define HCR_E2H_BIT (ULL(1) << 34) 540 #define HCR_HCD_BIT (ULL(1) << 29) 541 #define HCR_TGE_BIT (ULL(1) << 27) 542 #define HCR_RW_SHIFT U(31) 543 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 544 #define HCR_TWE_BIT (ULL(1) << 14) 545 #define HCR_TWI_BIT (ULL(1) << 13) 546 #define HCR_AMO_BIT (ULL(1) << 5) 547 #define HCR_IMO_BIT (ULL(1) << 4) 548 #define HCR_FMO_BIT (ULL(1) << 3) 549 550 /* ISR definitions */ 551 #define ISR_A_SHIFT U(8) 552 #define ISR_I_SHIFT U(7) 553 #define ISR_F_SHIFT U(6) 554 555 /* CNTHCTL_EL2 definitions */ 556 #define CNTHCTL_RESET_VAL U(0x0) 557 #define EVNTEN_BIT (U(1) << 2) 558 #define EL1PCEN_BIT (U(1) << 1) 559 #define EL1PCTEN_BIT (U(1) << 0) 560 561 /* CNTKCTL_EL1 definitions */ 562 #define EL0PTEN_BIT (U(1) << 9) 563 #define EL0VTEN_BIT (U(1) << 8) 564 #define EL0PCTEN_BIT (U(1) << 0) 565 #define EL0VCTEN_BIT (U(1) << 1) 566 #define EVNTEN_BIT (U(1) << 2) 567 #define EVNTDIR_BIT (U(1) << 3) 568 #define EVNTI_SHIFT U(4) 569 #define EVNTI_MASK U(0xf) 570 571 /* CPTR_EL3 definitions */ 572 #define TCPAC_BIT (U(1) << 31) 573 #define TAM_BIT (U(1) << 30) 574 #define TTA_BIT (U(1) << 20) 575 #define TFP_BIT (U(1) << 10) 576 #define CPTR_EZ_BIT (U(1) << 8) 577 #define CPTR_EL3_RESET_VAL (TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT)) 578 579 /* CPTR_EL2 definitions */ 580 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 581 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 582 #define CPTR_EL2_TAM_BIT (U(1) << 30) 583 #define CPTR_EL2_TTA_BIT (U(1) << 20) 584 #define CPTR_EL2_TFP_BIT (U(1) << 10) 585 #define CPTR_EL2_TZ_BIT (U(1) << 8) 586 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 587 588 /* CPSR/SPSR definitions */ 589 #define DAIF_FIQ_BIT (U(1) << 0) 590 #define DAIF_IRQ_BIT (U(1) << 1) 591 #define DAIF_ABT_BIT (U(1) << 2) 592 #define DAIF_DBG_BIT (U(1) << 3) 593 #define SPSR_DAIF_SHIFT U(6) 594 #define SPSR_DAIF_MASK U(0xf) 595 596 #define SPSR_AIF_SHIFT U(6) 597 #define SPSR_AIF_MASK U(0x7) 598 599 #define SPSR_E_SHIFT U(9) 600 #define SPSR_E_MASK U(0x1) 601 #define SPSR_E_LITTLE U(0x0) 602 #define SPSR_E_BIG U(0x1) 603 604 #define SPSR_T_SHIFT U(5) 605 #define SPSR_T_MASK U(0x1) 606 #define SPSR_T_ARM U(0x0) 607 #define SPSR_T_THUMB U(0x1) 608 609 #define SPSR_M_SHIFT U(4) 610 #define SPSR_M_MASK U(0x1) 611 #define SPSR_M_AARCH64 U(0x0) 612 #define SPSR_M_AARCH32 U(0x1) 613 #define SPSR_M_EL2H U(0x9) 614 615 #define SPSR_EL_SHIFT U(2) 616 #define SPSR_EL_WIDTH U(2) 617 618 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 619 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 620 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 621 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 622 623 #define SPSR_PAN_BIT BIT_64(22) 624 625 #define SPSR_DIT_BIT BIT(24) 626 627 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 628 629 #define DISABLE_ALL_EXCEPTIONS \ 630 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 631 632 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 633 634 /* 635 * RMR_EL3 definitions 636 */ 637 #define RMR_EL3_RR_BIT (U(1) << 1) 638 #define RMR_EL3_AA64_BIT (U(1) << 0) 639 640 /* 641 * HI-VECTOR address for AArch32 state 642 */ 643 #define HI_VECTOR_BASE U(0xFFFF0000) 644 645 /* 646 * TCR defintions 647 */ 648 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 649 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 650 #define TCR_EL1_IPS_SHIFT U(32) 651 #define TCR_EL2_PS_SHIFT U(16) 652 #define TCR_EL3_PS_SHIFT U(16) 653 654 #define TCR_TxSZ_MIN ULL(16) 655 #define TCR_TxSZ_MAX ULL(39) 656 #define TCR_TxSZ_MAX_TTST ULL(48) 657 658 #define TCR_T0SZ_SHIFT U(0) 659 #define TCR_T1SZ_SHIFT U(16) 660 661 /* (internal) physical address size bits in EL3/EL1 */ 662 #define TCR_PS_BITS_4GB ULL(0x0) 663 #define TCR_PS_BITS_64GB ULL(0x1) 664 #define TCR_PS_BITS_1TB ULL(0x2) 665 #define TCR_PS_BITS_4TB ULL(0x3) 666 #define TCR_PS_BITS_16TB ULL(0x4) 667 #define TCR_PS_BITS_256TB ULL(0x5) 668 669 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 670 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 671 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 672 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 673 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 674 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 675 676 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 677 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 678 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 679 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 680 681 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 682 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 683 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 684 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 685 686 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 687 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 688 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 689 690 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 691 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 692 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 693 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 694 695 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 696 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 697 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 698 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 699 700 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 701 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 702 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 703 704 #define TCR_TG0_SHIFT U(14) 705 #define TCR_TG0_MASK ULL(3) 706 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 707 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 708 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 709 710 #define TCR_TG1_SHIFT U(30) 711 #define TCR_TG1_MASK ULL(3) 712 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 713 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 714 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 715 716 #define TCR_EPD0_BIT (ULL(1) << 7) 717 #define TCR_EPD1_BIT (ULL(1) << 23) 718 719 #define MODE_SP_SHIFT U(0x0) 720 #define MODE_SP_MASK U(0x1) 721 #define MODE_SP_EL0 U(0x0) 722 #define MODE_SP_ELX U(0x1) 723 724 #define MODE_RW_SHIFT U(0x4) 725 #define MODE_RW_MASK U(0x1) 726 #define MODE_RW_64 U(0x0) 727 #define MODE_RW_32 U(0x1) 728 729 #define MODE_EL_SHIFT U(0x2) 730 #define MODE_EL_MASK U(0x3) 731 #define MODE_EL_WIDTH U(0x2) 732 #define MODE_EL3 U(0x3) 733 #define MODE_EL2 U(0x2) 734 #define MODE_EL1 U(0x1) 735 #define MODE_EL0 U(0x0) 736 737 #define MODE32_SHIFT U(0) 738 #define MODE32_MASK U(0xf) 739 #define MODE32_usr U(0x0) 740 #define MODE32_fiq U(0x1) 741 #define MODE32_irq U(0x2) 742 #define MODE32_svc U(0x3) 743 #define MODE32_mon U(0x6) 744 #define MODE32_abt U(0x7) 745 #define MODE32_hyp U(0xa) 746 #define MODE32_und U(0xb) 747 #define MODE32_sys U(0xf) 748 749 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 750 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 751 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 752 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 753 754 #define SPSR_64(el, sp, daif) \ 755 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 756 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 757 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 758 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 759 (~(SPSR_SSBS_BIT_AARCH64))) 760 761 #define SPSR_MODE32(mode, isa, endian, aif) \ 762 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 763 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 764 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 765 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 766 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 767 (~(SPSR_SSBS_BIT_AARCH32))) 768 769 /* 770 * TTBR Definitions 771 */ 772 #define TTBR_CNP_BIT ULL(0x1) 773 774 /* 775 * CTR_EL0 definitions 776 */ 777 #define CTR_CWG_SHIFT U(24) 778 #define CTR_CWG_MASK U(0xf) 779 #define CTR_ERG_SHIFT U(20) 780 #define CTR_ERG_MASK U(0xf) 781 #define CTR_DMINLINE_SHIFT U(16) 782 #define CTR_DMINLINE_MASK U(0xf) 783 #define CTR_L1IP_SHIFT U(14) 784 #define CTR_L1IP_MASK U(0x3) 785 #define CTR_IMINLINE_SHIFT U(0) 786 #define CTR_IMINLINE_MASK U(0xf) 787 788 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 789 790 /* Physical timer control register bit fields shifts and masks */ 791 #define CNTP_CTL_ENABLE_SHIFT U(0) 792 #define CNTP_CTL_IMASK_SHIFT U(1) 793 #define CNTP_CTL_ISTATUS_SHIFT U(2) 794 795 #define CNTP_CTL_ENABLE_MASK U(1) 796 #define CNTP_CTL_IMASK_MASK U(1) 797 #define CNTP_CTL_ISTATUS_MASK U(1) 798 799 /* Physical timer control macros */ 800 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 801 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 802 803 /* Exception Syndrome register bits and bobs */ 804 #define ESR_EC_SHIFT U(26) 805 #define ESR_EC_MASK U(0x3f) 806 #define ESR_EC_LENGTH U(6) 807 #define ESR_ISS_SHIFT U(0) 808 #define ESR_ISS_LENGTH U(25) 809 #define EC_UNKNOWN U(0x0) 810 #define EC_WFE_WFI U(0x1) 811 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 812 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 813 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 814 #define EC_AARCH32_CP14_LDC_STC U(0x6) 815 #define EC_FP_SIMD U(0x7) 816 #define EC_AARCH32_CP10_MRC U(0x8) 817 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 818 #define EC_ILLEGAL U(0xe) 819 #define EC_AARCH32_SVC U(0x11) 820 #define EC_AARCH32_HVC U(0x12) 821 #define EC_AARCH32_SMC U(0x13) 822 #define EC_AARCH64_SVC U(0x15) 823 #define EC_AARCH64_HVC U(0x16) 824 #define EC_AARCH64_SMC U(0x17) 825 #define EC_AARCH64_SYS U(0x18) 826 #define EC_IABORT_LOWER_EL U(0x20) 827 #define EC_IABORT_CUR_EL U(0x21) 828 #define EC_PC_ALIGN U(0x22) 829 #define EC_DABORT_LOWER_EL U(0x24) 830 #define EC_DABORT_CUR_EL U(0x25) 831 #define EC_SP_ALIGN U(0x26) 832 #define EC_AARCH32_FP U(0x28) 833 #define EC_AARCH64_FP U(0x2c) 834 #define EC_SERROR U(0x2f) 835 #define EC_BRK U(0x3c) 836 837 /* 838 * External Abort bit in Instruction and Data Aborts synchronous exception 839 * syndromes. 840 */ 841 #define ESR_ISS_EABORT_EA_BIT U(9) 842 843 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 844 845 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 846 #define RMR_RESET_REQUEST_SHIFT U(0x1) 847 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 848 849 /******************************************************************************* 850 * Definitions of register offsets, fields and macros for CPU system 851 * instructions. 852 ******************************************************************************/ 853 854 #define TLBI_ADDR_SHIFT U(12) 855 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 856 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 857 858 /******************************************************************************* 859 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 860 * system level implementation of the Generic Timer. 861 ******************************************************************************/ 862 #define CNTCTLBASE_CNTFRQ U(0x0) 863 #define CNTNSAR U(0x4) 864 #define CNTNSAR_NS_SHIFT(x) (x) 865 866 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 867 #define CNTACR_RPCT_SHIFT U(0x0) 868 #define CNTACR_RVCT_SHIFT U(0x1) 869 #define CNTACR_RFRQ_SHIFT U(0x2) 870 #define CNTACR_RVOFF_SHIFT U(0x3) 871 #define CNTACR_RWVT_SHIFT U(0x4) 872 #define CNTACR_RWPT_SHIFT U(0x5) 873 874 /******************************************************************************* 875 * Definitions of register offsets and fields in the CNTBaseN Frame of the 876 * system level implementation of the Generic Timer. 877 ******************************************************************************/ 878 /* Physical Count register. */ 879 #define CNTPCT_LO U(0x0) 880 /* Counter Frequency register. */ 881 #define CNTBASEN_CNTFRQ U(0x10) 882 /* Physical Timer CompareValue register. */ 883 #define CNTP_CVAL_LO U(0x20) 884 /* Physical Timer Control register. */ 885 #define CNTP_CTL U(0x2c) 886 887 /* PMCR_EL0 definitions */ 888 #define PMCR_EL0_RESET_VAL U(0x0) 889 #define PMCR_EL0_N_SHIFT U(11) 890 #define PMCR_EL0_N_MASK U(0x1f) 891 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 892 #define PMCR_EL0_LP_BIT (U(1) << 7) 893 #define PMCR_EL0_LC_BIT (U(1) << 6) 894 #define PMCR_EL0_DP_BIT (U(1) << 5) 895 #define PMCR_EL0_X_BIT (U(1) << 4) 896 #define PMCR_EL0_D_BIT (U(1) << 3) 897 #define PMCR_EL0_C_BIT (U(1) << 2) 898 #define PMCR_EL0_P_BIT (U(1) << 1) 899 #define PMCR_EL0_E_BIT (U(1) << 0) 900 901 /******************************************************************************* 902 * Definitions for system register interface to SVE 903 ******************************************************************************/ 904 #define ZCR_EL3 S3_6_C1_C2_0 905 #define ZCR_EL2 S3_4_C1_C2_0 906 907 /* ZCR_EL3 definitions */ 908 #define ZCR_EL3_LEN_MASK U(0xf) 909 910 /* ZCR_EL2 definitions */ 911 #define ZCR_EL2_LEN_MASK U(0xf) 912 913 /******************************************************************************* 914 * Definitions of MAIR encodings for device and normal memory 915 ******************************************************************************/ 916 /* 917 * MAIR encodings for device memory attributes. 918 */ 919 #define MAIR_DEV_nGnRnE ULL(0x0) 920 #define MAIR_DEV_nGnRE ULL(0x4) 921 #define MAIR_DEV_nGRE ULL(0x8) 922 #define MAIR_DEV_GRE ULL(0xc) 923 924 /* 925 * MAIR encodings for normal memory attributes. 926 * 927 * Cache Policy 928 * WT: Write Through 929 * WB: Write Back 930 * NC: Non-Cacheable 931 * 932 * Transient Hint 933 * NTR: Non-Transient 934 * TR: Transient 935 * 936 * Allocation Policy 937 * RA: Read Allocate 938 * WA: Write Allocate 939 * RWA: Read and Write Allocate 940 * NA: No Allocation 941 */ 942 #define MAIR_NORM_WT_TR_WA ULL(0x1) 943 #define MAIR_NORM_WT_TR_RA ULL(0x2) 944 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 945 #define MAIR_NORM_NC ULL(0x4) 946 #define MAIR_NORM_WB_TR_WA ULL(0x5) 947 #define MAIR_NORM_WB_TR_RA ULL(0x6) 948 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 949 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 950 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 951 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 952 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 953 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 954 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 955 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 956 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 957 958 #define MAIR_NORM_OUTER_SHIFT U(4) 959 960 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 961 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 962 963 /* PAR_EL1 fields */ 964 #define PAR_F_SHIFT U(0) 965 #define PAR_F_MASK ULL(0x1) 966 #define PAR_ADDR_SHIFT U(12) 967 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 968 969 /******************************************************************************* 970 * Definitions for system register interface to SPE 971 ******************************************************************************/ 972 #define PMBLIMITR_EL1 S3_0_C9_C10_0 973 974 /******************************************************************************* 975 * Definitions for system register interface to MPAM 976 ******************************************************************************/ 977 #define MPAMIDR_EL1 S3_0_C10_C4_4 978 #define MPAM2_EL2 S3_4_C10_C5_0 979 #define MPAMHCR_EL2 S3_4_C10_C4_0 980 #define MPAM3_EL3 S3_6_C10_C5_0 981 982 /******************************************************************************* 983 * Definitions for system register interface to AMU for FEAT_AMUv1 984 ******************************************************************************/ 985 #define AMCR_EL0 S3_3_C13_C2_0 986 #define AMCFGR_EL0 S3_3_C13_C2_1 987 #define AMCGCR_EL0 S3_3_C13_C2_2 988 #define AMUSERENR_EL0 S3_3_C13_C2_3 989 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 990 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 991 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 992 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 993 994 /* Activity Monitor Group 0 Event Counter Registers */ 995 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 996 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 997 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 998 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 999 1000 /* Activity Monitor Group 0 Event Type Registers */ 1001 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1002 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1003 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1004 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1005 1006 /* Activity Monitor Group 1 Event Counter Registers */ 1007 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1008 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1009 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1010 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1011 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1012 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1013 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1014 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1015 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1016 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1017 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1018 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1019 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1020 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1021 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1022 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1023 1024 /* Activity Monitor Group 1 Event Type Registers */ 1025 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1026 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1027 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1028 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1029 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1030 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1031 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1032 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1033 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1034 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1035 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1036 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1037 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1038 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1039 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1040 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1041 1042 /* AMCFGR_EL0 definitions */ 1043 #define AMCFGR_EL0_NCG_SHIFT U(28) 1044 #define AMCFGR_EL0_NCG_MASK U(0xf) 1045 #define AMCFGR_EL0_N_SHIFT U(0) 1046 #define AMCFGR_EL0_N_MASK U(0xff) 1047 1048 /* AMCGCR_EL0 definitions */ 1049 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1050 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1051 1052 /* MPAM register definitions */ 1053 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1054 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1055 1056 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1057 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1058 1059 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1060 1061 /******************************************************************************* 1062 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1063 ******************************************************************************/ 1064 1065 /* Definition for register defining which virtual offsets are implemented. */ 1066 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1067 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1068 #define AMCG1IDR_CTR_SHIFT U(0) 1069 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1070 #define AMCG1IDR_VOFF_SHIFT U(16) 1071 1072 /* New bit added to AMCR_EL0 */ 1073 #define AMCR_CG1RZ_BIT (ULL(0x1) << 17) 1074 1075 /* 1076 * Definitions for virtual offset registers for architected activity monitor 1077 * event counters. 1078 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1079 */ 1080 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1081 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1082 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1083 1084 /* 1085 * Definitions for virtual offset registers for auxiliary activity monitor event 1086 * counters. 1087 */ 1088 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1089 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1090 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1091 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1092 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1093 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1094 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1095 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1096 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1097 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1098 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1099 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1100 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1101 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1102 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1103 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1104 1105 /******************************************************************************* 1106 * Realm management extension register definitions 1107 ******************************************************************************/ 1108 1109 /* GPCCR_EL3 definitions */ 1110 #define GPCCR_EL3 S3_6_C2_C1_6 1111 1112 /* Least significant address bits protected by each entry in level 0 GPT */ 1113 #define GPCCR_L0GPTSZ_SHIFT U(20) 1114 #define GPCCR_L0GPTSZ_MASK U(0xF) 1115 #define GPCCR_L0GPTSZ_30BITS U(0x0) 1116 #define GPCCR_L0GPTSZ_34BITS U(0x4) 1117 #define GPCCR_L0GPTSZ_36BITS U(0x6) 1118 #define GPCCR_L0GPTSZ_39BITS U(0x9) 1119 #define SET_GPCCR_L0GPTSZ(x) \ 1120 ((x & GPCCR_L0GPTSZ_MASK) << GPCCR_L0GPTSZ_SHIFT) 1121 1122 /* Granule protection check priority bit definitions */ 1123 #define GPCCR_GPCP_SHIFT U(17) 1124 #define GPCCR_GPCP_BIT (ULL(1) << GPCCR_EL3_GPCP_SHIFT) 1125 1126 /* Granule protection check bit definitions */ 1127 #define GPCCR_GPC_SHIFT U(16) 1128 #define GPCCR_GPC_BIT (ULL(1) << GPCCR_GPC_SHIFT) 1129 1130 /* Physical granule size bit definitions */ 1131 #define GPCCR_PGS_SHIFT U(14) 1132 #define GPCCR_PGS_MASK U(0x3) 1133 #define GPCCR_PGS_4K U(0x0) 1134 #define GPCCR_PGS_16K U(0x2) 1135 #define GPCCR_PGS_64K U(0x1) 1136 #define SET_GPCCR_PGS(x) \ 1137 ((x & GPCCR_PGS_MASK) << GPCCR_PGS_SHIFT) 1138 1139 /* GPT fetch shareability attribute bit definitions */ 1140 #define GPCCR_SH_SHIFT U(12) 1141 #define GPCCR_SH_MASK U(0x3) 1142 #define GPCCR_SH_NS U(0x0) 1143 #define GPCCR_SH_OS U(0x2) 1144 #define GPCCR_SH_IS U(0x3) 1145 #define SET_GPCCR_SH(x) \ 1146 ((x & GPCCR_SH_MASK) << GPCCR_SH_SHIFT) 1147 1148 /* GPT fetch outer cacheability attribute bit definitions */ 1149 #define GPCCR_ORGN_SHIFT U(10) 1150 #define GPCCR_ORGN_MASK U(0x3) 1151 #define GPCCR_ORGN_NC U(0x0) 1152 #define GPCCR_ORGN_WB_RA_WA U(0x1) 1153 #define GPCCR_ORGN_WT_RA_NWA U(0x2) 1154 #define GPCCR_ORGN_WB_RA_NWA U(0x3) 1155 #define SET_GPCCR_ORGN(x) \ 1156 ((x & GPCCR_ORGN_MASK) << GPCCR_ORGN_SHIFT) 1157 1158 /* GPT fetch inner cacheability attribute bit definitions */ 1159 #define GPCCR_IRGN_SHIFT U(8) 1160 #define GPCCR_IRGN_MASK U(0x3) 1161 #define GPCCR_IRGN_NC U(0x0) 1162 #define GPCCR_IRGN_WB_RA_WA U(0x1) 1163 #define GPCCR_IRGN_WT_RA_NWA U(0x2) 1164 #define GPCCR_IRGN_WB_RA_NWA U(0x3) 1165 #define SET_GPCCR_IRGN(x) \ 1166 ((x & GPCCR_IRGN_MASK) << GPCCR_IRGN_SHIFT) 1167 1168 /* Protected physical address size bit definitions */ 1169 #define GPCCR_PPS_SHIFT U(0) 1170 #define GPCCR_PPS_MASK U(0x7) 1171 #define GPCCR_PPS_4GB U(0x0) 1172 #define GPCCR_PPS_64GB U(0x1) 1173 #define GPCCR_PPS_1TB U(0x2) 1174 #define GPCCR_PPS_4TB U(0x3) 1175 #define GPCCR_PPS_16TB U(0x4) 1176 #define GPCCR_PPS_256TB U(0x5) 1177 #define GPCCR_PPS_4PB U(0x6) 1178 #define SET_GPCCR_PPS(x) \ 1179 ((x & GPCCR_PPS_MASK) << GPCCR_PPS_SHIFT) 1180 1181 /* GPTBR_EL3 definitions */ 1182 #define GPTBR_EL3 S3_6_C2_C1_4 1183 1184 /* Base Address for the GPT bit definitions */ 1185 #define GPTBR_BADDR_SHIFT U(0) 1186 #define GPTBR_BADDR_VAL_SHIFT U(12) 1187 #define GPTBR_BADDR_MASK ULL(0xffffffffff) 1188 1189 /******************************************************************************* 1190 * RAS system registers 1191 ******************************************************************************/ 1192 #define DISR_EL1 S3_0_C12_C1_1 1193 #define DISR_A_BIT U(31) 1194 1195 #define ERRIDR_EL1 S3_0_C5_C3_0 1196 #define ERRIDR_MASK U(0xffff) 1197 1198 #define ERRSELR_EL1 S3_0_C5_C3_1 1199 1200 /* System register access to Standard Error Record registers */ 1201 #define ERXFR_EL1 S3_0_C5_C4_0 1202 #define ERXCTLR_EL1 S3_0_C5_C4_1 1203 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1204 #define ERXADDR_EL1 S3_0_C5_C4_3 1205 #define ERXPFGF_EL1 S3_0_C5_C4_4 1206 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1207 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1208 #define ERXMISC0_EL1 S3_0_C5_C5_0 1209 #define ERXMISC1_EL1 S3_0_C5_C5_1 1210 1211 #define ERXCTLR_ED_BIT (U(1) << 0) 1212 #define ERXCTLR_UE_BIT (U(1) << 4) 1213 1214 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1215 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1216 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1217 1218 /******************************************************************************* 1219 * Armv8.3 Pointer Authentication Registers 1220 ******************************************************************************/ 1221 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1222 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1223 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1224 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1225 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1226 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1227 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1228 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1229 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1230 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1231 1232 /******************************************************************************* 1233 * Armv8.4 Data Independent Timing Registers 1234 ******************************************************************************/ 1235 #define DIT S3_3_C4_C2_5 1236 #define DIT_BIT BIT(24) 1237 1238 /******************************************************************************* 1239 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1240 ******************************************************************************/ 1241 #define SSBS S3_3_C4_C2_6 1242 1243 /******************************************************************************* 1244 * Armv8.5 - Memory Tagging Extension Registers 1245 ******************************************************************************/ 1246 #define TFSRE0_EL1 S3_0_C5_C6_1 1247 #define TFSR_EL1 S3_0_C5_C6_0 1248 #define RGSR_EL1 S3_0_C1_C0_5 1249 #define GCR_EL1 S3_0_C1_C0_6 1250 1251 /******************************************************************************* 1252 * FEAT_HCX - Extended Hypervisor Configuration Register 1253 ******************************************************************************/ 1254 #define HCRX_EL2 S3_4_C1_C2_2 1255 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1256 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1257 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1258 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1259 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1260 1261 /******************************************************************************* 1262 * Definitions for DynamicIQ Shared Unit registers 1263 ******************************************************************************/ 1264 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1265 1266 /* CLUSTERPWRDN_EL1 register definitions */ 1267 #define DSU_CLUSTER_PWR_OFF 0 1268 #define DSU_CLUSTER_PWR_ON 1 1269 #define DSU_CLUSTER_PWR_MASK U(1) 1270 1271 #endif /* ARCH_H */ 1272