1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* -------------------------------------------------- 25 * Errata Workaround for Cortex-A710 Erratum 1987031. 26 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 27 * open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a710_1987031_wa 34 /* Check revision. */ 35 mov x17, x30 36 bl check_errata_1987031 37 cbz x0, 1f 38 39 /* Apply instruction patching sequence */ 40 ldr x0,=0x6 41 msr S3_6_c15_c8_0,x0 42 ldr x0,=0xF3A08002 43 msr S3_6_c15_c8_2,x0 44 ldr x0,=0xFFF0F7FE 45 msr S3_6_c15_c8_3,x0 46 ldr x0,=0x40000001003ff 47 msr S3_6_c15_c8_1,x0 48 ldr x0,=0x7 49 msr S3_6_c15_c8_0,x0 50 ldr x0,=0xBF200000 51 msr S3_6_c15_c8_2,x0 52 ldr x0,=0xFFEF0000 53 msr S3_6_c15_c8_3,x0 54 ldr x0,=0x40000001003f3 55 msr S3_6_c15_c8_1,x0 56 isb 571: 58 ret x17 59endfunc errata_a710_1987031_wa 60 61func check_errata_1987031 62 /* Applies to r0p0, r1p0 and r2p0 */ 63 mov x1, #0x20 64 b cpu_rev_var_ls 65endfunc check_errata_1987031 66 67/* -------------------------------------------------- 68 * Errata Workaround for Cortex-A710 Erratum 2081180. 69 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 70 * It is still open. 71 * Inputs: 72 * x0: variant[4:7] and revision[0:3] of current cpu. 73 * Shall clobber: x0-x17 74 * -------------------------------------------------- 75 */ 76func errata_a710_2081180_wa 77 /* Check revision. */ 78 mov x17, x30 79 bl check_errata_2081180 80 cbz x0, 1f 81 82 /* Apply instruction patching sequence */ 83 ldr x0,=0x3 84 msr S3_6_c15_c8_0,x0 85 ldr x0,=0xF3A08002 86 msr S3_6_c15_c8_2,x0 87 ldr x0,=0xFFF0F7FE 88 msr S3_6_c15_c8_3,x0 89 ldr x0,=0x10002001003FF 90 msr S3_6_c15_c8_1,x0 91 ldr x0,=0x4 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xBF200000 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFEF0000 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003F3 98 msr S3_6_c15_c8_1,x0 99 isb 1001: 101 ret x17 102endfunc errata_a710_2081180_wa 103 104func check_errata_2081180 105 /* Applies to r0p0, r1p0 and r2p0 */ 106 mov x1, #0x20 107 b cpu_rev_var_ls 108endfunc check_errata_2081180 109 110/* --------------------------------------------------------------------- 111 * Errata Workaround for Cortex-A710 Erratum 2055002. 112 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 113 * Inputs: 114 * x0: variant[4:7] and revision[0:3] of current cpu. 115 * Shall clobber: x0-x17 116 * --------------------------------------------------------------------- 117 */ 118func errata_a710_2055002_wa 119 /* Compare x0 against revision r2p0 */ 120 mov x17, x30 121 bl check_errata_2055002 122 cbz x0, 1f 123 mrs x1, CORTEX_A710_CPUACTLR_EL1 124 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 125 msr CORTEX_A710_CPUACTLR_EL1, x1 1261: 127 ret x17 128endfunc errata_a710_2055002_wa 129 130func check_errata_2055002 131 /* Applies to r1p0, r2p0 */ 132 mov x1, #0x20 133 b cpu_rev_var_ls 134endfunc check_errata_2055002 135 136/* ------------------------------------------------------------- 137 * Errata Workaround for Cortex-A710 Erratum 2017096. 138 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 139 * Inputs: 140 * x0: variant[4:7] and revision[0:3] of current cpu. 141 * Shall clobber: x0-x17 142 * ------------------------------------------------------------- 143 */ 144func errata_a710_2017096_wa 145 /* Compare x0 against revision r0p0 to r2p0 */ 146 mov x17, x30 147 bl check_errata_2017096 148 cbz x0, 1f 149 mrs x1, CORTEX_A710_CPUECTLR_EL1 150 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 151 msr CORTEX_A710_CPUECTLR_EL1, x1 152 1531: 154 ret x17 155endfunc errata_a710_2017096_wa 156 157func check_errata_2017096 158 /* Applies to r0p0, r1p0, r2p0 */ 159 mov x1, #0x20 160 b cpu_rev_var_ls 161endfunc check_errata_2017096 162 163 164/* --------------------------------------------------------------------- 165 * Errata Workaround for Cortex-A710 Erratum 2083908. 166 * This applies to revision r2p0 of Cortex-A710 and is still open. 167 * Inputs: 168 * x0: variant[4:7] and revision[0:3] of current cpu. 169 * Shall clobber: x0-x17 170 * --------------------------------------------------------------------- 171 */ 172func errata_a710_2083908_wa 173 /* Compare x0 against revision r2p0 */ 174 mov x17, x30 175 bl check_errata_2083908 176 cbz x0, 1f 177 mrs x1, CORTEX_A710_CPUACTLR5_EL1 178 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 179 msr CORTEX_A710_CPUACTLR5_EL1, x1 1801: 181 ret x17 182endfunc errata_a710_2083908_wa 183 184func check_errata_2083908 185 /* Applies to r2p0 */ 186 mov x1, #CPU_REV(2, 0) 187 mov x2, #CPU_REV(2, 0) 188 b cpu_rev_var_range 189endfunc check_errata_2083908 190 191 /* ---------------------------------------------------- 192 * HW will do the cache maintenance while powering down 193 * ---------------------------------------------------- 194 */ 195func cortex_a710_core_pwr_dwn 196 /* --------------------------------------------------- 197 * Enable CPU power down bit in power control register 198 * --------------------------------------------------- 199 */ 200 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 201 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 202 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 203 isb 204 ret 205endfunc cortex_a710_core_pwr_dwn 206 207#if REPORT_ERRATA 208 /* 209 * Errata printing function for Cortex-A710. Must follow AAPCS. 210 */ 211func cortex_a710_errata_report 212 stp x8, x30, [sp, #-16]! 213 214 bl cpu_get_rev_var 215 mov x8, x0 216 217 /* 218 * Report all errata. The revision-variant information is passed to 219 * checking functions of each errata. 220 */ 221 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 222 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 223 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 224 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 225 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 226 227 ldp x8, x30, [sp], #16 228 ret 229endfunc cortex_a710_errata_report 230#endif 231 232func cortex_a710_reset_func 233 mov x19, x30 234 235 /* Disable speculative loads */ 236 msr SSBS, xzr 237 238 bl cpu_get_rev_var 239 mov x18, x0 240 241#if ERRATA_A710_1987031 242 mov x0, x18 243 bl errata_a710_1987031_wa 244#endif 245 246#if ERRATA_A710_2081180 247 mov x0, x18 248 bl errata_a710_2081180_wa 249#endif 250 251#if ERRATA_A710_2055002 252 mov x0, x18 253 bl errata_a710_2055002_wa 254#endif 255 256#if ERRATA_A710_2017096 257 mov x0, x18 258 bl errata_a710_2017096_wa 259#endif 260 261#if ERRATA_A710_2083908 262 mov x0, x18 263 bl errata_a710_2083908_wa 264#endif 265 isb 266 ret x19 267endfunc cortex_a710_reset_func 268 269 /* --------------------------------------------- 270 * This function provides Cortex-A710 specific 271 * register information for crash reporting. 272 * It needs to return with x6 pointing to 273 * a list of register names in ascii and 274 * x8 - x15 having values of registers to be 275 * reported. 276 * --------------------------------------------- 277 */ 278.section .rodata.cortex_a710_regs, "aS" 279cortex_a710_regs: /* The ascii list of register names to be reported */ 280 .asciz "cpuectlr_el1", "" 281 282func cortex_a710_cpu_reg_dump 283 adr x6, cortex_a710_regs 284 mrs x8, CORTEX_A710_CPUECTLR_EL1 285 ret 286endfunc cortex_a710_cpu_reg_dump 287 288declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 289 cortex_a710_reset_func, \ 290 cortex_a710_core_pwr_dwn 291