1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``BL2_AT_EL3``: This is an optional build option that enables the use of 56 BL2 at EL3 execution level. 57 58- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 60 61- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 62 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 63 the RW sections in RAM, while leaving the RO sections in place. This option 64 enable this use-case. For now, this option is only supported when BL2_AT_EL3 65 is set to '1'. 66 67- ``BL31``: This is an optional build option which specifies the path to 68 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 69 be built. 70 71- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 72 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 73 this file name will be used to save the key. 74 75- ``BL32``: This is an optional build option which specifies the path to 76 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 77 be built. 78 79- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 80 Trusted OS Extra1 image for the ``fip`` target. 81 82- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 83 Trusted OS Extra2 image for the ``fip`` target. 84 85- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 86 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 87 this file name will be used to save the key. 88 89- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 90 ``fip`` target in case TF-A BL2 is used. 91 92- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 93 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 94 this file name will be used to save the key. 95 96- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 97 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 98 If enabled, it is needed to use a compiler that supports the option 99 ``-mbranch-protection``. Selects the branch protection features to use: 100- 0: Default value turns off all types of branch protection 101- 1: Enables all types of branch protection features 102- 2: Return address signing to its standard level 103- 3: Extend the signing to include leaf functions 104- 4: Turn on branch target identification mechanism 105 106 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 107 and resulting PAuth/BTI features. 108 109 +-------+--------------+-------+-----+ 110 | Value | GCC option | PAuth | BTI | 111 +=======+==============+=======+=====+ 112 | 0 | none | N | N | 113 +-------+--------------+-------+-----+ 114 | 1 | standard | Y | Y | 115 +-------+--------------+-------+-----+ 116 | 2 | pac-ret | Y | N | 117 +-------+--------------+-------+-----+ 118 | 3 | pac-ret+leaf | Y | N | 119 +-------+--------------+-------+-----+ 120 | 4 | bti | N | Y | 121 +-------+--------------+-------+-----+ 122 123 This option defaults to 0 and this is an experimental feature. 124 Note that Pointer Authentication is enabled for Non-secure world 125 irrespective of the value of this option if the CPU supports it. 126 127- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 128 compilation of each build. It must be set to a C string (including quotes 129 where applicable). Defaults to a string that contains the time and date of 130 the compilation. 131 132- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 133 build to be uniquely identified. Defaults to the current git commit id. 134 135- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 136 137- ``CFLAGS``: Extra user options appended on the compiler's command line in 138 addition to the options set by the build system. 139 140- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 141 release several CPUs out of reset. It can take either 0 (several CPUs may be 142 brought up) or 1 (only one CPU will ever be brought up during cold reset). 143 Default is 0. If the platform always brings up a single CPU, there is no 144 need to distinguish between primary and secondary CPUs and the boot path can 145 be optimised. The ``plat_is_my_cpu_primary()`` and 146 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 147 to be implemented in this case. 148 149- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 150 Defaults to ``tbbr``. 151 152- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 153 register state when an unexpected exception occurs during execution of 154 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 155 this is only enabled for a debug build of the firmware. 156 157- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 158 certificate generation tool to create new keys in case no valid keys are 159 present or specified. Allowed options are '0' or '1'. Default is '1'. 160 161- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 162 the AArch32 system registers to be included when saving and restoring the 163 CPU context. The option must be set to 0 for AArch64-only platforms (that 164 is on hardware that does not implement AArch32, or at least not at EL1 and 165 higher ELs). Default value is 1. 166 167- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 168 operations when entering/exiting an EL2 execution context. This is of primary 169 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 171 ``SPMD_SPM_AT_SEL2`` is set. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 178 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 179 execution context. Default value is 0. 180 181- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 182 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 183 registers to be included when saving and restoring the CPU context as 184 part of world switch. Default value is 0 and this is an experimental feature. 185 Note that Pointer Authentication is enabled for Non-secure world irrespective 186 of the value of this flag if the CPU supports it. 187 188- ``DEBUG``: Chooses between a debug and release build. It can take either 0 189 (release) or 1 (debug) as values. 0 is the default. 190 191- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 192 authenticated decryption algorithm to be used to decrypt firmware/s during 193 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 194 this flag is ``none`` to disable firmware decryption which is an optional 195 feature as per TBBR. Also, it is an experimental feature. 196 197- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 198 of the binary image. If set to 1, then only the ELF image is built. 199 0 is the default. 200 201- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 202 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 203 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 204 check the latest Arm ARM. 205 206- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 207 Board Boot authentication at runtime. This option is meant to be enabled only 208 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 209 flag has to be enabled. 0 is the default. 210 211- ``E``: Boolean option to make warnings into errors. Default is 1. 212 213- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 214 the normal boot flow. It must specify the entry point address of the EL3 215 payload. Please refer to the "Booting an EL3 payload" section for more 216 details. 217 218- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 219 This is an optional architectural feature available on v8.4 onwards. Some 220 v8.2 implementations also implement an AMU and this option can be used to 221 enable this feature on those systems as well. Default is 0. 222 223- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 224 are compiled out. For debug builds, this option defaults to 1, and calls to 225 ``assert()`` are left in place. For release builds, this option defaults to 0 226 and calls to ``assert()`` function are compiled out. This option can be set 227 independently of ``DEBUG``. It can also be used to hide any auxiliary code 228 that is only required for the assertion and does not fit in the assertion 229 itself. 230 231- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 232 dumps or not. It is supported in both AArch64 and AArch32. However, in 233 AArch32 the format of the frame records are not defined in the AAPCS and they 234 are defined by the implementation. This implementation of backtrace only 235 supports the format used by GCC when T32 interworking is disabled. For this 236 reason enabling this option in AArch32 will force the compiler to only 237 generate A32 code. This option is enabled by default only in AArch64 debug 238 builds, but this behaviour can be overridden in each platform's Makefile or 239 in the build command line. 240 241- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 242 support in GCC for TF-A. This option is currently only supported for 243 AArch64. Default is 0. 244 245- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 246 feature. MPAM is an optional Armv8.4 extension that enables various memory 247 system components and resources to define partitions; software running at 248 various ELs can assign themselves to desired partition to control their 249 performance aspects. 250 251 When this option is set to ``1``, EL3 allows lower ELs to access their own 252 MPAM registers without trapping into EL3. This option doesn't make use of 253 partitioning in EL3, however. Platform initialisation code should configure 254 and use partitions in EL3 as required. This option defaults to ``0``. 255 256- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 257 support within generic code in TF-A. This option is currently only supported 258 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 259 (SP_min) for AARCH32. Default is 0. 260 261- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 262 Measurement Framework(PMF). Default is 0. 263 264- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 265 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 266 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 267 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 268 software. 269 270- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 271 instrumentation which injects timestamp collection points into TF-A to 272 allow runtime performance to be measured. Currently, only PSCI is 273 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 274 as well. Default is 0. 275 276- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 277 extensions. This is an optional architectural feature for AArch64. 278 The default is 1 but is automatically disabled when the target architecture 279 is AArch32. 280 281- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 282 (SVE) for the Non-secure world only. SVE is an optional architectural feature 283 for AArch64. Note that when SVE is enabled for the Non-secure world, access 284 to SIMD and floating-point functionality from the Secure world is disabled by 285 default and controlled with ENABLE_SVE_FOR_SWD. 286 This is to avoid corruption of the Non-secure world data in the Z-registers 287 which are aliased by the SIMD and FP registers. The build option is not 288 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 289 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 290 1. The default is 1 but is automatically disabled when the target 291 architecture is AArch32. 292 293- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 294 SVE is an optional architectural feature for AArch64. Note that this option 295 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 296 automatically disabled when the target architecture is AArch32. 297 298- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 299 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 300 default value is set to "none". "strong" is the recommended stack protection 301 level if this feature is desired. "none" disables the stack protection. For 302 all values other than "none", the ``plat_get_stack_protector_canary()`` 303 platform hook needs to be implemented. The value is passed as the last 304 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 305 306- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 307 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 308 experimental. 309 310- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 311 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 312 experimental. 313 314- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 315 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 316 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 317 318- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 319 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 320 build flag which is marked as experimental. 321 322- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 323 deprecated platform APIs, helper functions or drivers within Trusted 324 Firmware as error. It can take the value 1 (flag the use of deprecated 325 APIs as error) or 0. The default is 0. 326 327- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 328 targeted at EL3. When set ``0`` (default), no exceptions are expected or 329 handled at EL3, and a panic will result. This is supported only for AArch64 330 builds. 331 332- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 333 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 334 Default value is 40 (LOG_LEVEL_INFO). 335 336- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 337 injection from lower ELs, and this build option enables lower ELs to use 338 Error Records accessed via System Registers to inject faults. This is 339 applicable only to AArch64 builds. 340 341 This feature is intended for testing purposes only, and is advisable to keep 342 disabled for production images. 343 344- ``FIP_NAME``: This is an optional build option which specifies the FIP 345 filename for the ``fip`` target. Default is ``fip.bin``. 346 347- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 348 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 349 350- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 351 352 :: 353 354 0: Encryption is done with Secret Symmetric Key (SSK) which is common 355 for a class of devices. 356 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 357 unique per device. 358 359 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 360 experimental. 361 362- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 363 tool to create certificates as per the Chain of Trust described in 364 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 365 include the certificates in the FIP and FWU_FIP. Default value is '0'. 366 367 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 368 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 369 the corresponding certificates, and to include those certificates in the 370 FIP and FWU_FIP. 371 372 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 373 images will not include support for Trusted Board Boot. The FIP will still 374 include the corresponding certificates. This FIP can be used to verify the 375 Chain of Trust on the host machine through other mechanisms. 376 377 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 378 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 379 will not include the corresponding certificates, causing a boot failure. 380 381- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 382 inherent support for specific EL3 type interrupts. Setting this build option 383 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 384 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 385 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 386 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 387 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 388 the Secure Payload interrupts needs to be synchronously handed over to Secure 389 EL1 for handling. The default value of this option is ``0``, which means the 390 Group 0 interrupts are assumed to be handled by Secure EL1. 391 392- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 393 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 394 ``0`` (default), these exceptions will be trapped in the current exception 395 level (or in EL1 if the current exception level is EL0). 396 397- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 398 software operations are required for CPUs to enter and exit coherency. 399 However, newer systems exist where CPUs' entry to and exit from coherency 400 is managed in hardware. Such systems require software to only initiate these 401 operations, and the rest is managed in hardware, minimizing active software 402 management. In such systems, this boolean option enables TF-A to carry out 403 build and run-time optimizations during boot and power management operations. 404 This option defaults to 0 and if it is enabled, then it implies 405 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 406 407 If this flag is disabled while the platform which TF-A is compiled for 408 includes cores that manage coherency in hardware, then a compilation error is 409 generated. This is based on the fact that a system cannot have, at the same 410 time, cores that manage coherency in hardware and cores that don't. In other 411 words, a platform cannot have, at the same time, cores that require 412 ``HW_ASSISTED_COHERENCY=1`` and cores that require 413 ``HW_ASSISTED_COHERENCY=0``. 414 415 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 416 translation library (xlat tables v2) must be used; version 1 of translation 417 library is not supported. 418 419- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 420 bottom, higher addresses at the top. This build flag can be set to '1' to 421 invert this behavior. Lower addresses will be printed at the top and higher 422 addresses at the bottom. 423 424- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 425 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 426 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 427 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 428 images. 429 430- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 431 used for generating the PKCS keys and subsequent signing of the certificate. 432 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 433 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 434 compliant and is retained only for compatibility. The default value of this 435 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 436 437- ``KEY_SIZE``: This build flag enables the user to select the key size for 438 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 439 depend on the chosen algorithm and the cryptographic module. 440 441 +-----------+------------------------------------+ 442 | KEY_ALG | Possible key sizes | 443 +===========+====================================+ 444 | rsa | 1024 , 2048 (default), 3072, 4096* | 445 +-----------+------------------------------------+ 446 | ecdsa | unavailable | 447 +-----------+------------------------------------+ 448 449 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 450 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 451 452- ``HASH_ALG``: This build flag enables the user to select the secure hash 453 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 454 The default value of this flag is ``sha256``. 455 456- ``LDFLAGS``: Extra user options appended to the linkers' command line in 457 addition to the one set by the build system. 458 459- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 460 output compiled into the build. This should be one of the following: 461 462 :: 463 464 0 (LOG_LEVEL_NONE) 465 10 (LOG_LEVEL_ERROR) 466 20 (LOG_LEVEL_NOTICE) 467 30 (LOG_LEVEL_WARNING) 468 40 (LOG_LEVEL_INFO) 469 50 (LOG_LEVEL_VERBOSE) 470 471 All log output up to and including the selected log level is compiled into 472 the build. The default value is 40 in debug builds and 20 in release builds. 473 474- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 475 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well 476 in order to provide trust that the code taking the measurements and recording 477 them has not been tampered with. 478 479 This option defaults to 0 and is an experimental feature in the stage of 480 development. 481 482- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 483 specifies the file that contains the Non-Trusted World private key in PEM 484 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 485 486- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 487 optional. It is only needed if the platform makefile specifies that it 488 is required in order to build the ``fwu_fip`` target. 489 490- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 491 contents upon world switch. It can take either 0 (don't save and restore) or 492 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 493 wants the timer registers to be saved and restored. 494 495- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 496 for the BL image. It can be either 0 (include) or 1 (remove). The default 497 value is 0. 498 499- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 500 the underlying hardware is not a full PL011 UART but a minimally compliant 501 generic UART, which is a subset of the PL011. The driver will not access 502 any register that is not part of the SBSA generic UART specification. 503 Default value is 0 (a full PL011 compliant UART is present). 504 505- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 506 must be subdirectory of any depth under ``plat/``, and must contain a 507 platform makefile named ``platform.mk``. For example, to build TF-A for the 508 Arm Juno board, select PLAT=juno. 509 510- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 511 instead of the normal boot flow. When defined, it must specify the entry 512 point address for the preloaded BL33 image. This option is incompatible with 513 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 514 over ``PRELOADED_BL33_BASE``. 515 516- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 517 vector address can be programmed or is fixed on the platform. It can take 518 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 519 programmable reset address, it is expected that a CPU will start executing 520 code directly at the right address, both on a cold and warm reset. In this 521 case, there is no need to identify the entrypoint on boot and the boot path 522 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 523 does not need to be implemented in this case. 524 525- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 526 possible for the PSCI power-state parameter: original and extended State-ID 527 formats. This flag if set to 1, configures the generic PSCI layer to use the 528 extended format. The default value of this flag is 0, which means by default 529 the original power-state format is used by the PSCI implementation. This flag 530 should be specified by the platform makefile and it governs the return value 531 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 532 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 533 set to 1 as well. 534 535- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 536 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 537 or later CPUs. 538 539 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 540 set to ``1``. 541 542 This option is disabled by default. 543 544- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 545 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 546 entrypoint) or 1 (CPU reset to BL31 entrypoint). 547 The default value is 0. 548 549- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 550 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 551 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 552 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 553 554- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 555 file that contains the ROT private key in PEM format and enforces public key 556 hash generation. If ``SAVE_KEYS=1``, this 557 file name will be used to save the key. 558 559- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 560 certificate generation tool to save the keys used to establish the Chain of 561 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 562 563- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 564 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 565 target. 566 567- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 568 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 569 this file name will be used to save the key. 570 571- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 572 optional. It is only needed if the platform makefile specifies that it 573 is required in order to build the ``fwu_fip`` target. 574 575- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 576 Delegated Exception Interface to BL31 image. This defaults to ``0``. 577 578 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 579 set to ``1``. 580 581- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 582 isolated on separate memory pages. This is a trade-off between security and 583 memory usage. See "Isolating code and read-only data on separate memory 584 pages" section in :ref:`Firmware Design`. This flag is disabled by default 585 and affects all BL images. 586 587- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 588 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 589 allocated in RAM discontiguous from the loaded firmware image. When set, the 590 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 591 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 592 sections are placed in RAM immediately following the loaded firmware image. 593 594- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 595 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 596 UEFI+ACPI this can provide a certain amount of OS forward compatibility 597 with newer platforms that aren't ECAM compliant. 598 599- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 600 This build option is only valid if ``ARCH=aarch64``. The value should be 601 the path to the directory containing the SPD source, relative to 602 ``services/spd/``; the directory is expected to contain a makefile called 603 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 604 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 605 cannot be enabled when the ``SPM_MM`` option is enabled. 606 607- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 608 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 609 execution in BL1 just before handing over to BL31. At this point, all 610 firmware images have been loaded in memory, and the MMU and caches are 611 turned off. Refer to the "Debugging options" section for more details. 612 613- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 614 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 615 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 616 extension. This is the default when enabling the SPM Dispatcher. When 617 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 618 state. This latter configuration supports pre-Armv8.4 platforms (aka not 619 implementing the Armv8.4-SecEL2 extension). 620 621- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 622 Partition Manager (SPM) implementation. The default value is ``0`` 623 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 624 enabled (``SPD=spmd``). 625 626- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 627 description of secure partitions. The build system will parse this file and 628 package all secure partition blobs into the FIP. This file is not 629 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 630 631- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 632 secure interrupts (caught through the FIQ line). Platforms can enable 633 this directive if they need to handle such interruption. When enabled, 634 the FIQ are handled in monitor mode and non secure world is not allowed 635 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 636 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 637 638- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 639 Boot feature. When set to '1', BL1 and BL2 images include support to load 640 and verify the certificates and images in a FIP, and BL1 includes support 641 for the Firmware Update. The default value is '0'. Generation and inclusion 642 of certificates in the FIP and FWU_FIP depends upon the value of the 643 ``GENERATE_COT`` option. 644 645 .. warning:: 646 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 647 already exist in disk, they will be overwritten without further notice. 648 649- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 650 specifies the file that contains the Trusted World private key in PEM 651 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 652 653- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 654 synchronous, (see "Initializing a BL32 Image" section in 655 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 656 synchronous method) or 1 (BL32 is initialized using asynchronous method). 657 Default is 0. 658 659- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 660 routing model which routes non-secure interrupts asynchronously from TSP 661 to EL3 causing immediate preemption of TSP. The EL3 is responsible 662 for saving and restoring the TSP context in this routing model. The 663 default routing model (when the value is 0) is to route non-secure 664 interrupts to TSP allowing it to save its context and hand over 665 synchronously to EL3 via an SMC. 666 667 .. note:: 668 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 669 must also be set to ``1``. 670 671- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 672 linker. When the ``LINKER`` build variable points to the armlink linker, 673 this flag is enabled automatically. To enable support for armlink, platforms 674 will have to provide a scatter file for the BL image. Currently, Tegra 675 platforms use the armlink support to compile BL3-1 images. 676 677- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 678 memory region in the BL memory map or not (see "Use of Coherent memory in 679 TF-A" section in :ref:`Firmware Design`). It can take the value 1 680 (Coherent memory region is included) or 0 (Coherent memory region is 681 excluded). Default is 1. 682 683- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 684 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 685 Default is 0. 686 687- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 688 firmware configuration framework. This will move the io_policies into a 689 configuration device tree, instead of static structure in the code base. 690 This is currently an experimental feature. 691 692- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 693 at runtime using fconf. If this flag is enabled, COT descriptors are 694 statically captured in tb_fw_config file in the form of device tree nodes 695 and properties. Currently, COT descriptors used by BL2 are moved to the 696 device tree and COT descriptors used by BL1 are retained in the code 697 base statically. This is currently an experimental feature. 698 699- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 700 runtime using firmware configuration framework. The platform specific SDEI 701 shared and private events configuration is retrieved from device tree rather 702 than static C structures at compile time. This is currently an experimental 703 feature and is only supported if SDEI_SUPPORT build flag is enabled. 704 705- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 706 and Group1 secure interrupts using the firmware configuration framework. The 707 platform specific secure interrupt property descriptor is retrieved from 708 device tree in runtime rather than depending on static C structure at compile 709 time. This is currently an experimental feature. 710 711- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 712 This feature creates a library of functions to be placed in ROM and thus 713 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 714 is 0. 715 716- ``V``: Verbose build. If assigned anything other than 0, the build commands 717 are printed. Default is 0. 718 719- ``VERSION_STRING``: String used in the log output for each TF-A image. 720 Defaults to a string formed by concatenating the version number, build type 721 and build string. 722 723- ``W``: Warning level. Some compiler warning options of interest have been 724 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 725 each level enabling more warning options. Default is 0. 726 727- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 728 the CPU after warm boot. This is applicable for platforms which do not 729 require interconnect programming to enable cache coherency (eg: single 730 cluster platforms). If this option is enabled, then warm boot path 731 enables D-caches immediately after enabling MMU. This option defaults to 0. 732 733- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 734 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 735 default value of this flag is ``no``. Note this option must be enabled only 736 for ARM architecture greater than Armv8.5-A. 737 738- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 739 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 740 The default value of this flag is ``0``. 741 742 ``AT`` speculative errata workaround disables stage1 page table walk for 743 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 744 produces either the correct result or failure without TLB allocation. 745 746 This boolean option enables errata for all below CPUs. 747 748 +---------+--------------+-------------------------+ 749 | Errata | CPU | Workaround Define | 750 +=========+==============+=========================+ 751 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 752 +---------+--------------+-------------------------+ 753 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 754 +---------+--------------+-------------------------+ 755 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 756 +---------+--------------+-------------------------+ 757 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 758 +---------+--------------+-------------------------+ 759 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 760 +---------+--------------+-------------------------+ 761 762 .. note:: 763 This option is enabled by build only if platform sets any of above defines 764 mentioned in ’Workaround Define' column in the table. 765 If this option is enabled for the EL3 software then EL2 software also must 766 implement this workaround due to the behaviour of the errata mentioned 767 in new SDEN document which will get published soon. 768 769- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 770 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 771 This flag is disabled by default. 772 773- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 774 path on the host machine which is used to build certificate generation and 775 firmware encryption tool. 776 777- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 778 functions that wait for an arbitrary time length (udelay and mdelay). The 779 default value is 0. 780 781- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer 782 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 783 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 784 feature for AArch64. The default is 0 and it is automatically disabled when 785 the target architecture is AArch32. 786 787- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 788 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 789 but unused). This feature is available if trace unit such as ETMv4.x, and 790 ETE(extending ETM feature) is implemented. This flag is disabled by default. 791 792- ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers 793 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 794 if FEAT_TRF is implemented. This flag is disabled by default. 795 796GICv3 driver options 797-------------------- 798 799GICv3 driver files are included using directive: 800 801``include drivers/arm/gic/v3/gicv3.mk`` 802 803The driver can be configured with the following options set in the platform 804makefile: 805 806- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 807 Enabling this option will add runtime detection support for the 808 GIC-600, so is safe to select even for a GIC500 implementation. 809 This option defaults to 0. 810 811- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 812 for GIC-600 AE. Enabling this option will introduce support to initialize 813 the FMU. Platforms should call the init function during boot to enable the 814 FMU and its safety mechanisms. This option defaults to 0. 815 816- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 817 functionality. This option defaults to 0 818 819- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 820 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 821 functions. This is required for FVP platform which need to simulate GIC save 822 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 823 824- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 825 This option defaults to 0. 826 827- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 828 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 829 830Debugging options 831----------------- 832 833To compile a debug version and make the build more verbose use 834 835.. code:: shell 836 837 make PLAT=<platform> DEBUG=1 V=1 all 838 839AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 840example DS-5) might not support this and may need an older version of DWARF 841symbols to be emitted by GCC. This can be achieved by using the 842``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 843version to 2 is recommended for DS-5 versions older than 5.16. 844 845When debugging logic problems it might also be useful to disable all compiler 846optimizations by using ``-O0``. 847 848.. warning:: 849 Using ``-O0`` could cause output images to be larger and base addresses 850 might need to be recalculated (see the **Memory layout on Arm development 851 platforms** section in the :ref:`Firmware Design`). 852 853Extra debug options can be passed to the build system by setting ``CFLAGS`` or 854``LDFLAGS``: 855 856.. code:: shell 857 858 CFLAGS='-O0 -gdwarf-2' \ 859 make PLAT=<platform> DEBUG=1 V=1 all 860 861Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 862ignored as the linker is called directly. 863 864It is also possible to introduce an infinite loop to help in debugging the 865post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 866``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 867section. In this case, the developer may take control of the target using a 868debugger when indicated by the console output. When using DS-5, the following 869commands can be used: 870 871:: 872 873 # Stop target execution 874 interrupt 875 876 # 877 # Prepare your debugging environment, e.g. set breakpoints 878 # 879 880 # Jump over the debug loop 881 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 882 883 # Resume execution 884 continue 885 886Firmware update options 887----------------------- 888 889- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 890 in defining the firmware update metadata structure. This flag is by default 891 set to '2'. 892 893- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 894 firmware bank. Each firmware bank must have the same number of images as per 895 the `PSA FW update specification`_. 896 This flag is used in defining the firmware update metadata structure. This 897 flag is by default set to '1'. 898 899- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 900 `PSA FW update specification`_. The default value is 0, and this is an 901 experimental feature. 902 PSA firmware update implementation has some limitations, such as BL2 is 903 not part of the protocol-updatable images, if BL2 needs to be updated, then 904 it should be done through another platform-defined mechanism, and it assumes 905 that the platform's hardware supports CRC32 instructions. 906 907-------------- 908 909*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* 910 911.. _DEN0115: https://developer.arm.com/docs/den0115/latest 912.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 913 914