1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``BL2_AT_EL3``: This is an optional build option that enables the use of 56 BL2 at EL3 execution level. 57 58- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 59 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 60 the RW sections in RAM, while leaving the RO sections in place. This option 61 enable this use-case. For now, this option is only supported when BL2_AT_EL3 62 is set to '1'. 63 64- ``BL31``: This is an optional build option which specifies the path to 65 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 66 be built. 67 68- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 69 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 70 this file name will be used to save the key. 71 72- ``BL32``: This is an optional build option which specifies the path to 73 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 74 be built. 75 76- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 77 Trusted OS Extra1 image for the ``fip`` target. 78 79- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 80 Trusted OS Extra2 image for the ``fip`` target. 81 82- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 83 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 84 this file name will be used to save the key. 85 86- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 87 ``fip`` target in case TF-A BL2 is used. 88 89- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 90 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 91 this file name will be used to save the key. 92 93- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 94 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 95 If enabled, it is needed to use a compiler that supports the option 96 ``-mbranch-protection``. Selects the branch protection features to use: 97- 0: Default value turns off all types of branch protection 98- 1: Enables all types of branch protection features 99- 2: Return address signing to its standard level 100- 3: Extend the signing to include leaf functions 101- 4: Turn on branch target identification mechanism 102 103 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 104 and resulting PAuth/BTI features. 105 106 +-------+--------------+-------+-----+ 107 | Value | GCC option | PAuth | BTI | 108 +=======+==============+=======+=====+ 109 | 0 | none | N | N | 110 +-------+--------------+-------+-----+ 111 | 1 | standard | Y | Y | 112 +-------+--------------+-------+-----+ 113 | 2 | pac-ret | Y | N | 114 +-------+--------------+-------+-----+ 115 | 3 | pac-ret+leaf | Y | N | 116 +-------+--------------+-------+-----+ 117 | 4 | bti | N | Y | 118 +-------+--------------+-------+-----+ 119 120 This option defaults to 0 and this is an experimental feature. 121 Note that Pointer Authentication is enabled for Non-secure world 122 irrespective of the value of this option if the CPU supports it. 123 124- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 125 compilation of each build. It must be set to a C string (including quotes 126 where applicable). Defaults to a string that contains the time and date of 127 the compilation. 128 129- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 130 build to be uniquely identified. Defaults to the current git commit id. 131 132- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 133 134- ``CFLAGS``: Extra user options appended on the compiler's command line in 135 addition to the options set by the build system. 136 137- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 138 release several CPUs out of reset. It can take either 0 (several CPUs may be 139 brought up) or 1 (only one CPU will ever be brought up during cold reset). 140 Default is 0. If the platform always brings up a single CPU, there is no 141 need to distinguish between primary and secondary CPUs and the boot path can 142 be optimised. The ``plat_is_my_cpu_primary()`` and 143 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 144 to be implemented in this case. 145 146- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 147 Defaults to ``tbbr``. 148 149- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 150 register state when an unexpected exception occurs during execution of 151 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 152 this is only enabled for a debug build of the firmware. 153 154- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 155 certificate generation tool to create new keys in case no valid keys are 156 present or specified. Allowed options are '0' or '1'. Default is '1'. 157 158- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 159 the AArch32 system registers to be included when saving and restoring the 160 CPU context. The option must be set to 0 for AArch64-only platforms (that 161 is on hardware that does not implement AArch32, or at least not at EL1 and 162 higher ELs). Default value is 1. 163 164- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 165 operations when entering/exiting an EL2 execution context. This is of primary 166 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 167 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 168 ``SPMD_SPM_AT_SEL2`` is set. 169 170- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 171 registers to be included when saving and restoring the CPU context. Default 172 is 0. 173 174- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 175 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 176 execution context. Default value is 0. 177 178- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 179 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 180 registers to be included when saving and restoring the CPU context as 181 part of world switch. Default value is 0 and this is an experimental feature. 182 Note that Pointer Authentication is enabled for Non-secure world irrespective 183 of the value of this flag if the CPU supports it. 184 185- ``DEBUG``: Chooses between a debug and release build. It can take either 0 186 (release) or 1 (debug) as values. 0 is the default. 187 188- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 189 authenticated decryption algorithm to be used to decrypt firmware/s during 190 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 191 this flag is ``none`` to disable firmware decryption which is an optional 192 feature as per TBBR. Also, it is an experimental feature. 193 194- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 195 of the binary image. If set to 1, then only the ELF image is built. 196 0 is the default. 197 198- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 199 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 200 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 201 check the latest Arm ARM. 202 203- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 204 Board Boot authentication at runtime. This option is meant to be enabled only 205 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 206 flag has to be enabled. 0 is the default. 207 208- ``E``: Boolean option to make warnings into errors. Default is 1. 209 210- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 211 the normal boot flow. It must specify the entry point address of the EL3 212 payload. Please refer to the "Booting an EL3 payload" section for more 213 details. 214 215- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 216 This is an optional architectural feature available on v8.4 onwards. Some 217 v8.2 implementations also implement an AMU and this option can be used to 218 enable this feature on those systems as well. Default is 0. 219 220- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 221 are compiled out. For debug builds, this option defaults to 1, and calls to 222 ``assert()`` are left in place. For release builds, this option defaults to 0 223 and calls to ``assert()`` function are compiled out. This option can be set 224 independently of ``DEBUG``. It can also be used to hide any auxiliary code 225 that is only required for the assertion and does not fit in the assertion 226 itself. 227 228- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 229 dumps or not. It is supported in both AArch64 and AArch32. However, in 230 AArch32 the format of the frame records are not defined in the AAPCS and they 231 are defined by the implementation. This implementation of backtrace only 232 supports the format used by GCC when T32 interworking is disabled. For this 233 reason enabling this option in AArch32 will force the compiler to only 234 generate A32 code. This option is enabled by default only in AArch64 debug 235 builds, but this behaviour can be overridden in each platform's Makefile or 236 in the build command line. 237 238- ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow 239 access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as 240 adding HCRX_EL2 to the EL2 context save/restore operations. 241 242- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 243 support in GCC for TF-A. This option is currently only supported for 244 AArch64. Default is 0. 245 246- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 247 feature. MPAM is an optional Armv8.4 extension that enables various memory 248 system components and resources to define partitions; software running at 249 various ELs can assign themselves to desired partition to control their 250 performance aspects. 251 252 When this option is set to ``1``, EL3 allows lower ELs to access their own 253 MPAM registers without trapping into EL3. This option doesn't make use of 254 partitioning in EL3, however. Platform initialisation code should configure 255 and use partitions in EL3 as required. This option defaults to ``0``. 256 257- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 258 support within generic code in TF-A. This option is currently only supported 259 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 260 (SP_min) for AARCH32. Default is 0. 261 262- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 263 Measurement Framework(PMF). Default is 0. 264 265- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 266 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 267 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 268 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 269 software. 270 271- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 272 instrumentation which injects timestamp collection points into TF-A to 273 allow runtime performance to be measured. Currently, only PSCI is 274 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 275 as well. Default is 0. 276 277- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 278 extensions. This is an optional architectural feature for AArch64. 279 The default is 1 but is automatically disabled when the target architecture 280 is AArch32. 281 282- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 283 (SVE) for the Non-secure world only. SVE is an optional architectural feature 284 for AArch64. Note that when SVE is enabled for the Non-secure world, access 285 to SIMD and floating-point functionality from the Secure world is disabled by 286 default and controlled with ENABLE_SVE_FOR_SWD. 287 This is to avoid corruption of the Non-secure world data in the Z-registers 288 which are aliased by the SIMD and FP registers. The build option is not 289 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 290 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 291 1. The default is 1 but is automatically disabled when the target 292 architecture is AArch32. 293 294- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 295 SVE is an optional architectural feature for AArch64. Note that this option 296 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 297 automatically disabled when the target architecture is AArch32. 298 299- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 300 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 301 default value is set to "none". "strong" is the recommended stack protection 302 level if this feature is desired. "none" disables the stack protection. For 303 all values other than "none", the ``plat_get_stack_protector_canary()`` 304 platform hook needs to be implemented. The value is passed as the last 305 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 306 307- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 308 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 309 experimental. 310 311- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 312 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 313 experimental. 314 315- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 316 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 317 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 318 319- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 320 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 321 build flag which is marked as experimental. 322 323- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 324 deprecated platform APIs, helper functions or drivers within Trusted 325 Firmware as error. It can take the value 1 (flag the use of deprecated 326 APIs as error) or 0. The default is 0. 327 328- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 329 targeted at EL3. When set ``0`` (default), no exceptions are expected or 330 handled at EL3, and a panic will result. This is supported only for AArch64 331 builds. 332 333- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 334 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 335 Default value is 40 (LOG_LEVEL_INFO). 336 337- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 338 injection from lower ELs, and this build option enables lower ELs to use 339 Error Records accessed via System Registers to inject faults. This is 340 applicable only to AArch64 builds. 341 342 This feature is intended for testing purposes only, and is advisable to keep 343 disabled for production images. 344 345- ``FIP_NAME``: This is an optional build option which specifies the FIP 346 filename for the ``fip`` target. Default is ``fip.bin``. 347 348- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 349 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 350 351- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 352 353 :: 354 355 0: Encryption is done with Secret Symmetric Key (SSK) which is common 356 for a class of devices. 357 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 358 unique per device. 359 360 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 361 experimental. 362 363- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 364 tool to create certificates as per the Chain of Trust described in 365 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 366 include the certificates in the FIP and FWU_FIP. Default value is '0'. 367 368 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 369 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 370 the corresponding certificates, and to include those certificates in the 371 FIP and FWU_FIP. 372 373 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 374 images will not include support for Trusted Board Boot. The FIP will still 375 include the corresponding certificates. This FIP can be used to verify the 376 Chain of Trust on the host machine through other mechanisms. 377 378 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 379 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 380 will not include the corresponding certificates, causing a boot failure. 381 382- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 383 inherent support for specific EL3 type interrupts. Setting this build option 384 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 385 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 386 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 387 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 388 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 389 the Secure Payload interrupts needs to be synchronously handed over to Secure 390 EL1 for handling. The default value of this option is ``0``, which means the 391 Group 0 interrupts are assumed to be handled by Secure EL1. 392 393- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 394 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 395 ``0`` (default), these exceptions will be trapped in the current exception 396 level (or in EL1 if the current exception level is EL0). 397 398- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 399 software operations are required for CPUs to enter and exit coherency. 400 However, newer systems exist where CPUs' entry to and exit from coherency 401 is managed in hardware. Such systems require software to only initiate these 402 operations, and the rest is managed in hardware, minimizing active software 403 management. In such systems, this boolean option enables TF-A to carry out 404 build and run-time optimizations during boot and power management operations. 405 This option defaults to 0 and if it is enabled, then it implies 406 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 407 408 If this flag is disabled while the platform which TF-A is compiled for 409 includes cores that manage coherency in hardware, then a compilation error is 410 generated. This is based on the fact that a system cannot have, at the same 411 time, cores that manage coherency in hardware and cores that don't. In other 412 words, a platform cannot have, at the same time, cores that require 413 ``HW_ASSISTED_COHERENCY=1`` and cores that require 414 ``HW_ASSISTED_COHERENCY=0``. 415 416 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 417 translation library (xlat tables v2) must be used; version 1 of translation 418 library is not supported. 419 420- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 421 bottom, higher addresses at the top. This build flag can be set to '1' to 422 invert this behavior. Lower addresses will be printed at the top and higher 423 addresses at the bottom. 424 425- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 426 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 427 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 428 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 429 images. 430 431- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 432 used for generating the PKCS keys and subsequent signing of the certificate. 433 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 434 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 435 compliant and is retained only for compatibility. The default value of this 436 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 437 438- ``KEY_SIZE``: This build flag enables the user to select the key size for 439 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 440 depend on the chosen algorithm and the cryptographic module. 441 442 +-----------+------------------------------------+ 443 | KEY_ALG | Possible key sizes | 444 +===========+====================================+ 445 | rsa | 1024 , 2048 (default), 3072, 4096* | 446 +-----------+------------------------------------+ 447 | ecdsa | unavailable | 448 +-----------+------------------------------------+ 449 450 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 451 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 452 453- ``HASH_ALG``: This build flag enables the user to select the secure hash 454 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 455 The default value of this flag is ``sha256``. 456 457- ``LDFLAGS``: Extra user options appended to the linkers' command line in 458 addition to the one set by the build system. 459 460- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 461 output compiled into the build. This should be one of the following: 462 463 :: 464 465 0 (LOG_LEVEL_NONE) 466 10 (LOG_LEVEL_ERROR) 467 20 (LOG_LEVEL_NOTICE) 468 30 (LOG_LEVEL_WARNING) 469 40 (LOG_LEVEL_INFO) 470 50 (LOG_LEVEL_VERBOSE) 471 472 All log output up to and including the selected log level is compiled into 473 the build. The default value is 40 in debug builds and 20 in release builds. 474 475- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 476 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well 477 in order to provide trust that the code taking the measurements and recording 478 them has not been tampered with. 479 480 This option defaults to 0 and is an experimental feature in the stage of 481 development. 482 483- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 484 specifies the file that contains the Non-Trusted World private key in PEM 485 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 486 487- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 488 optional. It is only needed if the platform makefile specifies that it 489 is required in order to build the ``fwu_fip`` target. 490 491- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 492 contents upon world switch. It can take either 0 (don't save and restore) or 493 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 494 wants the timer registers to be saved and restored. 495 496- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 497 for the BL image. It can be either 0 (include) or 1 (remove). The default 498 value is 0. 499 500- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 501 the underlying hardware is not a full PL011 UART but a minimally compliant 502 generic UART, which is a subset of the PL011. The driver will not access 503 any register that is not part of the SBSA generic UART specification. 504 Default value is 0 (a full PL011 compliant UART is present). 505 506- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 507 must be subdirectory of any depth under ``plat/``, and must contain a 508 platform makefile named ``platform.mk``. For example, to build TF-A for the 509 Arm Juno board, select PLAT=juno. 510 511- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 512 instead of the normal boot flow. When defined, it must specify the entry 513 point address for the preloaded BL33 image. This option is incompatible with 514 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 515 over ``PRELOADED_BL33_BASE``. 516 517- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 518 vector address can be programmed or is fixed on the platform. It can take 519 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 520 programmable reset address, it is expected that a CPU will start executing 521 code directly at the right address, both on a cold and warm reset. In this 522 case, there is no need to identify the entrypoint on boot and the boot path 523 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 524 does not need to be implemented in this case. 525 526- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 527 possible for the PSCI power-state parameter: original and extended State-ID 528 formats. This flag if set to 1, configures the generic PSCI layer to use the 529 extended format. The default value of this flag is 0, which means by default 530 the original power-state format is used by the PSCI implementation. This flag 531 should be specified by the platform makefile and it governs the return value 532 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 533 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 534 set to 1 as well. 535 536- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 537 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 538 or later CPUs. 539 540 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 541 set to ``1``. 542 543 This option is disabled by default. 544 545- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 546 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 547 entrypoint) or 1 (CPU reset to BL31 entrypoint). 548 The default value is 0. 549 550- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 551 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 552 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 553 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 554 555- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 556 file that contains the ROT private key in PEM format and enforces public key 557 hash generation. If ``SAVE_KEYS=1``, this 558 file name will be used to save the key. 559 560- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 561 certificate generation tool to save the keys used to establish the Chain of 562 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 563 564- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 565 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 566 target. 567 568- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 569 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 570 this file name will be used to save the key. 571 572- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 573 optional. It is only needed if the platform makefile specifies that it 574 is required in order to build the ``fwu_fip`` target. 575 576- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 577 Delegated Exception Interface to BL31 image. This defaults to ``0``. 578 579 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 580 set to ``1``. 581 582- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 583 isolated on separate memory pages. This is a trade-off between security and 584 memory usage. See "Isolating code and read-only data on separate memory 585 pages" section in :ref:`Firmware Design`. This flag is disabled by default 586 and affects all BL images. 587 588- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 589 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 590 allocated in RAM discontiguous from the loaded firmware image. When set, the 591 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 592 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 593 sections are placed in RAM immediately following the loaded firmware image. 594 595- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 596 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 597 UEFI+ACPI this can provide a certain amount of OS forward compatibility 598 with newer platforms that aren't ECAM compliant. 599 600- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 601 This build option is only valid if ``ARCH=aarch64``. The value should be 602 the path to the directory containing the SPD source, relative to 603 ``services/spd/``; the directory is expected to contain a makefile called 604 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 605 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 606 cannot be enabled when the ``SPM_MM`` option is enabled. 607 608- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 609 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 610 execution in BL1 just before handing over to BL31. At this point, all 611 firmware images have been loaded in memory, and the MMU and caches are 612 turned off. Refer to the "Debugging options" section for more details. 613 614- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 615 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 616 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 617 extension. This is the default when enabling the SPM Dispatcher. When 618 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 619 state. This latter configuration supports pre-Armv8.4 platforms (aka not 620 implementing the Armv8.4-SecEL2 extension). 621 622- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 623 Partition Manager (SPM) implementation. The default value is ``0`` 624 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 625 enabled (``SPD=spmd``). 626 627- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 628 description of secure partitions. The build system will parse this file and 629 package all secure partition blobs into the FIP. This file is not 630 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 631 632- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 633 secure interrupts (caught through the FIQ line). Platforms can enable 634 this directive if they need to handle such interruption. When enabled, 635 the FIQ are handled in monitor mode and non secure world is not allowed 636 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 637 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 638 639- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 640 Boot feature. When set to '1', BL1 and BL2 images include support to load 641 and verify the certificates and images in a FIP, and BL1 includes support 642 for the Firmware Update. The default value is '0'. Generation and inclusion 643 of certificates in the FIP and FWU_FIP depends upon the value of the 644 ``GENERATE_COT`` option. 645 646 .. warning:: 647 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 648 already exist in disk, they will be overwritten without further notice. 649 650- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 651 specifies the file that contains the Trusted World private key in PEM 652 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 653 654- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 655 synchronous, (see "Initializing a BL32 Image" section in 656 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 657 synchronous method) or 1 (BL32 is initialized using asynchronous method). 658 Default is 0. 659 660- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 661 routing model which routes non-secure interrupts asynchronously from TSP 662 to EL3 causing immediate preemption of TSP. The EL3 is responsible 663 for saving and restoring the TSP context in this routing model. The 664 default routing model (when the value is 0) is to route non-secure 665 interrupts to TSP allowing it to save its context and hand over 666 synchronously to EL3 via an SMC. 667 668 .. note:: 669 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 670 must also be set to ``1``. 671 672- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 673 linker. When the ``LINKER`` build variable points to the armlink linker, 674 this flag is enabled automatically. To enable support for armlink, platforms 675 will have to provide a scatter file for the BL image. Currently, Tegra 676 platforms use the armlink support to compile BL3-1 images. 677 678- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 679 memory region in the BL memory map or not (see "Use of Coherent memory in 680 TF-A" section in :ref:`Firmware Design`). It can take the value 1 681 (Coherent memory region is included) or 0 (Coherent memory region is 682 excluded). Default is 1. 683 684- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 685 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 686 Default is 0. 687 688- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 689 firmware configuration framework. This will move the io_policies into a 690 configuration device tree, instead of static structure in the code base. 691 This is currently an experimental feature. 692 693- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 694 at runtime using fconf. If this flag is enabled, COT descriptors are 695 statically captured in tb_fw_config file in the form of device tree nodes 696 and properties. Currently, COT descriptors used by BL2 are moved to the 697 device tree and COT descriptors used by BL1 are retained in the code 698 base statically. This is currently an experimental feature. 699 700- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 701 runtime using firmware configuration framework. The platform specific SDEI 702 shared and private events configuration is retrieved from device tree rather 703 than static C structures at compile time. This is currently an experimental 704 feature and is only supported if SDEI_SUPPORT build flag is enabled. 705 706- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 707 and Group1 secure interrupts using the firmware configuration framework. The 708 platform specific secure interrupt property descriptor is retrieved from 709 device tree in runtime rather than depending on static C structure at compile 710 time. This is currently an experimental feature. 711 712- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 713 This feature creates a library of functions to be placed in ROM and thus 714 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 715 is 0. 716 717- ``V``: Verbose build. If assigned anything other than 0, the build commands 718 are printed. Default is 0. 719 720- ``VERSION_STRING``: String used in the log output for each TF-A image. 721 Defaults to a string formed by concatenating the version number, build type 722 and build string. 723 724- ``W``: Warning level. Some compiler warning options of interest have been 725 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 726 each level enabling more warning options. Default is 0. 727 728- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 729 the CPU after warm boot. This is applicable for platforms which do not 730 require interconnect programming to enable cache coherency (eg: single 731 cluster platforms). If this option is enabled, then warm boot path 732 enables D-caches immediately after enabling MMU. This option defaults to 0. 733 734- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 735 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 736 default value of this flag is ``no``. Note this option must be enabled only 737 for ARM architecture greater than Armv8.5-A. 738 739- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 740 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 741 The default value of this flag is ``0``. 742 743 ``AT`` speculative errata workaround disables stage1 page table walk for 744 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 745 produces either the correct result or failure without TLB allocation. 746 747 This boolean option enables errata for all below CPUs. 748 749 +---------+--------------+-------------------------+ 750 | Errata | CPU | Workaround Define | 751 +=========+==============+=========================+ 752 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 753 +---------+--------------+-------------------------+ 754 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 755 +---------+--------------+-------------------------+ 756 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 757 +---------+--------------+-------------------------+ 758 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 759 +---------+--------------+-------------------------+ 760 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 761 +---------+--------------+-------------------------+ 762 763 .. note:: 764 This option is enabled by build only if platform sets any of above defines 765 mentioned in ’Workaround Define' column in the table. 766 If this option is enabled for the EL3 software then EL2 software also must 767 implement this workaround due to the behaviour of the errata mentioned 768 in new SDEN document which will get published soon. 769 770- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 771 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 772 This flag is disabled by default. 773 774- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 775 path on the host machine which is used to build certificate generation and 776 firmware encryption tool. 777 778- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 779 functions that wait for an arbitrary time length (udelay and mdelay). The 780 default value is 0. 781 782- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer 783 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 784 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 785 feature for AArch64. The default is 0 and it is automatically disabled when 786 the target architecture is AArch32. 787 788- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 789 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 790 but unused). This feature is available if trace unit such as ETMv4.x, and 791 ETE(extending ETM feature) is implemented. This flag is disabled by default. 792 793- ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers 794 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 795 if FEAT_TRF is implemented. This flag is disabled by default. 796 797GICv3 driver options 798-------------------- 799 800GICv3 driver files are included using directive: 801 802``include drivers/arm/gic/v3/gicv3.mk`` 803 804The driver can be configured with the following options set in the platform 805makefile: 806 807- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 808 Enabling this option will add runtime detection support for the 809 GIC-600, so is safe to select even for a GIC500 implementation. 810 This option defaults to 0. 811 812- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 813 for GIC-600 AE. Enabling this option will introduce support to initialize 814 the FMU. Platforms should call the init function during boot to enable the 815 FMU and its safety mechanisms. This option defaults to 0. 816 817- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 818 functionality. This option defaults to 0 819 820- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 821 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 822 functions. This is required for FVP platform which need to simulate GIC save 823 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 824 825- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 826 This option defaults to 0. 827 828- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 829 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 830 831Debugging options 832----------------- 833 834To compile a debug version and make the build more verbose use 835 836.. code:: shell 837 838 make PLAT=<platform> DEBUG=1 V=1 all 839 840AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 841example DS-5) might not support this and may need an older version of DWARF 842symbols to be emitted by GCC. This can be achieved by using the 843``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 844version to 2 is recommended for DS-5 versions older than 5.16. 845 846When debugging logic problems it might also be useful to disable all compiler 847optimizations by using ``-O0``. 848 849.. warning:: 850 Using ``-O0`` could cause output images to be larger and base addresses 851 might need to be recalculated (see the **Memory layout on Arm development 852 platforms** section in the :ref:`Firmware Design`). 853 854Extra debug options can be passed to the build system by setting ``CFLAGS`` or 855``LDFLAGS``: 856 857.. code:: shell 858 859 CFLAGS='-O0 -gdwarf-2' \ 860 make PLAT=<platform> DEBUG=1 V=1 all 861 862Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 863ignored as the linker is called directly. 864 865It is also possible to introduce an infinite loop to help in debugging the 866post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 867``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 868section. In this case, the developer may take control of the target using a 869debugger when indicated by the console output. When using DS-5, the following 870commands can be used: 871 872:: 873 874 # Stop target execution 875 interrupt 876 877 # 878 # Prepare your debugging environment, e.g. set breakpoints 879 # 880 881 # Jump over the debug loop 882 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 883 884 # Resume execution 885 continue 886 887Firmware update options 888----------------------- 889 890- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 891 in defining the firmware update metadata structure. This flag is by default 892 set to '2'. 893 894- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 895 firmware bank. Each firmware bank must have the same number of images as per 896 the `PSA FW update specification`_. 897 This flag is used in defining the firmware update metadata structure. This 898 flag is by default set to '1'. 899 900- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 901 `PSA FW update specification`_. The default value is 0, and this is an 902 experimental feature. 903 PSA firmware update implementation has some limitations, such as BL2 is 904 not part of the protocol-updatable images, if BL2 needs to be updated, then 905 it should be done through another platform-defined mechanism, and it assumes 906 that the platform's hardware supports CRC32 instructions. 907 908-------------- 909 910*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* 911 912.. _DEN0115: https://developer.arm.com/docs/den0115/latest 913.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 914 915