1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/sys_reg_trace.h> 26 #include <lib/extensions/trbe.h> 27 #include <lib/extensions/twed.h> 28 #include <lib/utils.h> 29 30 static void enable_extensions_secure(cpu_context_t *ctx); 31 32 /******************************************************************************* 33 * Context management library initialisation routine. This library is used by 34 * runtime services to share pointers to 'cpu_context' structures for the secure 35 * and non-secure states. Management of the structures and their associated 36 * memory is not done by the context management library e.g. the PSCI service 37 * manages the cpu context used for entry from and exit to the non-secure state. 38 * The Secure payload dispatcher service manages the context(s) corresponding to 39 * the secure state. It also uses this library to get access to the non-secure 40 * state cpu context pointers. 41 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 42 * which will used for programming an entry into a lower EL. The same context 43 * will used to save state upon exception entry from that EL. 44 ******************************************************************************/ 45 void __init cm_init(void) 46 { 47 /* 48 * The context management library has only global data to intialize, but 49 * that will be done when the BSS is zeroed out 50 */ 51 } 52 53 /******************************************************************************* 54 * The following function initializes the cpu_context 'ctx' for 55 * first use, and sets the initial entrypoint state as specified by the 56 * entry_point_info structure. 57 * 58 * The security state to initialize is determined by the SECURE attribute 59 * of the entry_point_info. 60 * 61 * The EE and ST attributes are used to configure the endianness and secure 62 * timer availability for the new execution context. 63 * 64 * To prepare the register state for entry call cm_prepare_el3_exit() and 65 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 66 * cm_el1_sysregs_context_restore(). 67 ******************************************************************************/ 68 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 69 { 70 unsigned int security_state; 71 u_register_t scr_el3; 72 el3_state_t *state; 73 gp_regs_t *gp_regs; 74 u_register_t sctlr_elx, actlr_elx; 75 76 assert(ctx != NULL); 77 78 security_state = GET_SECURITY_STATE(ep->h.attr); 79 80 /* Clear any residual register values from the context */ 81 zeromem(ctx, sizeof(*ctx)); 82 83 /* 84 * SCR_EL3 was initialised during reset sequence in macro 85 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 86 * affect the next EL. 87 * 88 * The following fields are initially set to zero and then updated to 89 * the required value depending on the state of the SPSR_EL3 and the 90 * Security state and entrypoint attributes of the next EL. 91 */ 92 scr_el3 = read_scr(); 93 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 94 SCR_ST_BIT | SCR_HCE_BIT); 95 /* 96 * SCR_NS: Set the security state of the next EL. 97 */ 98 if (security_state != SECURE) 99 scr_el3 |= SCR_NS_BIT; 100 /* 101 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 102 * Exception level as specified by SPSR. 103 */ 104 if (GET_RW(ep->spsr) == MODE_RW_64) 105 scr_el3 |= SCR_RW_BIT; 106 /* 107 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 108 * Secure timer registers to EL3, from AArch64 state only, if specified 109 * by the entrypoint attributes. 110 */ 111 if (EP_GET_ST(ep->h.attr) != 0U) 112 scr_el3 |= SCR_ST_BIT; 113 114 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 115 /* 116 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 117 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 118 */ 119 scr_el3 |= SCR_TERR_BIT; 120 #endif 121 122 #if !HANDLE_EA_EL3_FIRST 123 /* 124 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 125 * to EL3 when executing at a lower EL. When executing at EL3, External 126 * Aborts are taken to EL3. 127 */ 128 scr_el3 &= ~SCR_EA_BIT; 129 #endif 130 131 #if FAULT_INJECTION_SUPPORT 132 /* Enable fault injection from lower ELs */ 133 scr_el3 |= SCR_FIEN_BIT; 134 #endif 135 136 #if !CTX_INCLUDE_PAUTH_REGS 137 /* 138 * If the pointer authentication registers aren't saved during world 139 * switches the value of the registers can be leaked from the Secure to 140 * the Non-secure world. To prevent this, rather than enabling pointer 141 * authentication everywhere, we only enable it in the Non-secure world. 142 * 143 * If the Secure world wants to use pointer authentication, 144 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 145 */ 146 if (security_state == NON_SECURE) 147 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 148 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 149 150 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 151 /* Get Memory Tagging Extension support level */ 152 unsigned int mte = get_armv8_5_mte_support(); 153 #endif 154 /* 155 * Enable MTE support. Support is enabled unilaterally for the normal 156 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 157 * set. 158 */ 159 #if CTX_INCLUDE_MTE_REGS 160 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 161 scr_el3 |= SCR_ATA_BIT; 162 #else 163 /* 164 * When MTE is only implemented at EL0, it can be enabled 165 * across both worlds as no MTE registers are used. 166 */ 167 if ((mte == MTE_IMPLEMENTED_EL0) || 168 /* 169 * When MTE is implemented at all ELs, it can be only enabled 170 * in Non-Secure world without register saving. 171 */ 172 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 173 (security_state == NON_SECURE))) { 174 scr_el3 |= SCR_ATA_BIT; 175 } 176 #endif /* CTX_INCLUDE_MTE_REGS */ 177 178 #ifdef IMAGE_BL31 179 /* 180 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 181 * indicated by the interrupt routing model for BL31. 182 */ 183 scr_el3 |= get_scr_el3_from_routing_model(security_state); 184 #endif 185 186 /* Save the initialized value of CPTR_EL3 register */ 187 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 188 if (security_state == SECURE) { 189 enable_extensions_secure(ctx); 190 } 191 192 /* 193 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 194 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 195 * next mode is Hyp. 196 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 197 * same conditions as HVC instructions and when the processor supports 198 * ARMv8.6-FGT. 199 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 200 * CNTPOFF_EL2 register under the same conditions as HVC instructions 201 * and when the processor supports ECV. 202 */ 203 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 204 || ((GET_RW(ep->spsr) != MODE_RW_64) 205 && (GET_M32(ep->spsr) == MODE32_hyp))) { 206 scr_el3 |= SCR_HCE_BIT; 207 208 if (is_armv8_6_fgt_present()) { 209 scr_el3 |= SCR_FGTEN_BIT; 210 } 211 212 if (get_armv8_6_ecv_support() 213 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 214 scr_el3 |= SCR_ECVEN_BIT; 215 } 216 } 217 218 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 219 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 220 if (GET_RW(ep->spsr) != MODE_RW_64) { 221 ERROR("S-EL2 can not be used in AArch32."); 222 panic(); 223 } 224 225 scr_el3 |= SCR_EEL2_BIT; 226 } 227 228 /* 229 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 230 * and EL2, when clear, this bit traps accesses from EL2 so we set it 231 * to 1 when EL2 is present. 232 */ 233 if (is_armv8_6_feat_amuv1p1_present() && 234 (el_implemented(2) != EL_IMPL_NONE)) { 235 scr_el3 |= SCR_AMVOFFEN_BIT; 236 } 237 238 /* 239 * Initialise SCTLR_EL1 to the reset value corresponding to the target 240 * execution state setting all fields rather than relying of the hw. 241 * Some fields have architecturally UNKNOWN reset values and these are 242 * set to zero. 243 * 244 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 245 * 246 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 247 * required by PSCI specification) 248 */ 249 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 250 if (GET_RW(ep->spsr) == MODE_RW_64) 251 sctlr_elx |= SCTLR_EL1_RES1; 252 else { 253 /* 254 * If the target execution state is AArch32 then the following 255 * fields need to be set. 256 * 257 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 258 * instructions are not trapped to EL1. 259 * 260 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 261 * instructions are not trapped to EL1. 262 * 263 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 264 * CP15DMB, CP15DSB, and CP15ISB instructions. 265 */ 266 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 267 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 268 } 269 270 #if ERRATA_A75_764081 271 /* 272 * If workaround of errata 764081 for Cortex-A75 is used then set 273 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 274 */ 275 sctlr_elx |= SCTLR_IESB_BIT; 276 #endif 277 278 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 279 if (is_armv8_6_twed_present()) { 280 uint32_t delay = plat_arm_set_twedel_scr_el3(); 281 282 if (delay != TWED_DISABLED) { 283 /* Make sure delay value fits */ 284 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 285 286 /* Set delay in SCR_EL3 */ 287 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 288 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 289 << SCR_TWEDEL_SHIFT); 290 291 /* Enable WFE delay */ 292 scr_el3 |= SCR_TWEDEn_BIT; 293 } 294 } 295 296 /* 297 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 298 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 299 * are not part of the stored cpu_context. 300 */ 301 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 302 303 /* 304 * Base the context ACTLR_EL1 on the current value, as it is 305 * implementation defined. The context restore process will write 306 * the value from the context to the actual register and can cause 307 * problems for processor cores that don't expect certain bits to 308 * be zero. 309 */ 310 actlr_elx = read_actlr_el1(); 311 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 312 313 /* 314 * Populate EL3 state so that we've the right context 315 * before doing ERET 316 */ 317 state = get_el3state_ctx(ctx); 318 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 319 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 320 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 321 322 /* 323 * Store the X0-X7 value from the entrypoint into the context 324 * Use memcpy as we are in control of the layout of the structures 325 */ 326 gp_regs = get_gpregs_ctx(ctx); 327 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 328 } 329 330 /******************************************************************************* 331 * Enable architecture extensions on first entry to Non-secure world. 332 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 333 * it is zero. 334 ******************************************************************************/ 335 static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 336 { 337 #if IMAGE_BL31 338 #if ENABLE_SPE_FOR_LOWER_ELS 339 spe_enable(el2_unused); 340 #endif 341 342 #if ENABLE_AMU 343 amu_enable(el2_unused, ctx); 344 #endif 345 346 #if ENABLE_SVE_FOR_NS 347 sve_enable(ctx); 348 #endif 349 350 #if ENABLE_MPAM_FOR_LOWER_ELS 351 mpam_enable(el2_unused); 352 #endif 353 354 #if ENABLE_TRBE_FOR_NS 355 trbe_enable(); 356 #endif /* ENABLE_TRBE_FOR_NS */ 357 358 #if ENABLE_SYS_REG_TRACE_FOR_NS 359 sys_reg_trace_enable(ctx); 360 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 361 362 #endif 363 } 364 365 /******************************************************************************* 366 * Enable architecture extensions on first entry to Secure world. 367 ******************************************************************************/ 368 static void enable_extensions_secure(cpu_context_t *ctx) 369 { 370 #if IMAGE_BL31 371 #if ENABLE_SVE_FOR_SWD 372 sve_enable(ctx); 373 #endif 374 #endif 375 } 376 377 /******************************************************************************* 378 * The following function initializes the cpu_context for a CPU specified by 379 * its `cpu_idx` for first use, and sets the initial entrypoint state as 380 * specified by the entry_point_info structure. 381 ******************************************************************************/ 382 void cm_init_context_by_index(unsigned int cpu_idx, 383 const entry_point_info_t *ep) 384 { 385 cpu_context_t *ctx; 386 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 387 cm_setup_context(ctx, ep); 388 } 389 390 /******************************************************************************* 391 * The following function initializes the cpu_context for the current CPU 392 * for first use, and sets the initial entrypoint state as specified by the 393 * entry_point_info structure. 394 ******************************************************************************/ 395 void cm_init_my_context(const entry_point_info_t *ep) 396 { 397 cpu_context_t *ctx; 398 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 399 cm_setup_context(ctx, ep); 400 } 401 402 /******************************************************************************* 403 * Prepare the CPU system registers for first entry into secure or normal world 404 * 405 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 406 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 407 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 408 * For all entries, the EL1 registers are initialized from the cpu_context 409 ******************************************************************************/ 410 void cm_prepare_el3_exit(uint32_t security_state) 411 { 412 u_register_t sctlr_elx, scr_el3, mdcr_el2; 413 cpu_context_t *ctx = cm_get_context(security_state); 414 bool el2_unused = false; 415 uint64_t hcr_el2 = 0U; 416 417 assert(ctx != NULL); 418 419 if (security_state == NON_SECURE) { 420 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 421 CTX_SCR_EL3); 422 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 423 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 424 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 425 CTX_SCTLR_EL1); 426 sctlr_elx &= SCTLR_EE_BIT; 427 sctlr_elx |= SCTLR_EL2_RES1; 428 #if ERRATA_A75_764081 429 /* 430 * If workaround of errata 764081 for Cortex-A75 is used 431 * then set SCTLR_EL2.IESB to enable Implicit Error 432 * Synchronization Barrier. 433 */ 434 sctlr_elx |= SCTLR_IESB_BIT; 435 #endif 436 write_sctlr_el2(sctlr_elx); 437 } else if (el_implemented(2) != EL_IMPL_NONE) { 438 el2_unused = true; 439 440 /* 441 * EL2 present but unused, need to disable safely. 442 * SCTLR_EL2 can be ignored in this case. 443 * 444 * Set EL2 register width appropriately: Set HCR_EL2 445 * field to match SCR_EL3.RW. 446 */ 447 if ((scr_el3 & SCR_RW_BIT) != 0U) 448 hcr_el2 |= HCR_RW_BIT; 449 450 /* 451 * For Armv8.3 pointer authentication feature, disable 452 * traps to EL2 when accessing key registers or using 453 * pointer authentication instructions from lower ELs. 454 */ 455 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 456 457 write_hcr_el2(hcr_el2); 458 459 /* 460 * Initialise CPTR_EL2 setting all fields rather than 461 * relying on the hw. All fields have architecturally 462 * UNKNOWN reset values. 463 * 464 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 465 * accesses to the CPACR_EL1 or CPACR from both 466 * Execution states do not trap to EL2. 467 * 468 * CPTR_EL2.TTA: Set to zero so that Non-secure System 469 * register accesses to the trace registers from both 470 * Execution states do not trap to EL2. 471 * If PE trace unit System registers are not implemented 472 * then this bit is reserved, and must be set to zero. 473 * 474 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 475 * to SIMD and floating-point functionality from both 476 * Execution states do not trap to EL2. 477 */ 478 write_cptr_el2(CPTR_EL2_RESET_VAL & 479 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 480 | CPTR_EL2_TFP_BIT)); 481 482 /* 483 * Initialise CNTHCTL_EL2. All fields are 484 * architecturally UNKNOWN on reset and are set to zero 485 * except for field(s) listed below. 486 * 487 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 488 * Hyp mode of Non-secure EL0 and EL1 accesses to the 489 * physical timer registers. 490 * 491 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 492 * Hyp mode of Non-secure EL0 and EL1 accesses to the 493 * physical counter registers. 494 */ 495 write_cnthctl_el2(CNTHCTL_RESET_VAL | 496 EL1PCEN_BIT | EL1PCTEN_BIT); 497 498 /* 499 * Initialise CNTVOFF_EL2 to zero as it resets to an 500 * architecturally UNKNOWN value. 501 */ 502 write_cntvoff_el2(0); 503 504 /* 505 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 506 * MPIDR_EL1 respectively. 507 */ 508 write_vpidr_el2(read_midr_el1()); 509 write_vmpidr_el2(read_mpidr_el1()); 510 511 /* 512 * Initialise VTTBR_EL2. All fields are architecturally 513 * UNKNOWN on reset. 514 * 515 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 516 * 2 address translation is disabled, cache maintenance 517 * operations depend on the VMID. 518 * 519 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 520 * translation is disabled. 521 */ 522 write_vttbr_el2(VTTBR_RESET_VAL & 523 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 524 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 525 526 /* 527 * Initialise MDCR_EL2, setting all fields rather than 528 * relying on hw. Some fields are architecturally 529 * UNKNOWN on reset. 530 * 531 * MDCR_EL2.HLP: Set to one so that event counter 532 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 533 * occurs on the increment that changes 534 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 535 * implemented. This bit is RES0 in versions of the 536 * architecture earlier than ARMv8.5, setting it to 1 537 * doesn't have any effect on them. 538 * 539 * MDCR_EL2.TTRF: Set to zero so that access to Trace 540 * Filter Control register TRFCR_EL1 at EL1 is not 541 * trapped to EL2. This bit is RES0 in versions of 542 * the architecture earlier than ARMv8.4. 543 * 544 * MDCR_EL2.HPMD: Set to one so that event counting is 545 * prohibited at EL2. This bit is RES0 in versions of 546 * the architecture earlier than ARMv8.1, setting it 547 * to 1 doesn't have any effect on them. 548 * 549 * MDCR_EL2.TPMS: Set to zero so that accesses to 550 * Statistical Profiling control registers from EL1 551 * do not trap to EL2. This bit is RES0 when SPE is 552 * not implemented. 553 * 554 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 555 * EL1 System register accesses to the Debug ROM 556 * registers are not trapped to EL2. 557 * 558 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 559 * System register accesses to the powerdown debug 560 * registers are not trapped to EL2. 561 * 562 * MDCR_EL2.TDA: Set to zero so that System register 563 * accesses to the debug registers do not trap to EL2. 564 * 565 * MDCR_EL2.TDE: Set to zero so that debug exceptions 566 * are not routed to EL2. 567 * 568 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 569 * Monitors. 570 * 571 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 572 * EL1 accesses to all Performance Monitors registers 573 * are not trapped to EL2. 574 * 575 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 576 * and EL1 accesses to the PMCR_EL0 or PMCR are not 577 * trapped to EL2. 578 * 579 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 580 * architecturally-defined reset value. 581 * 582 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 583 * owning exception level is NS-EL1 and, tracing is 584 * prohibited at NS-EL2. These bits are RES0 when 585 * FEAT_TRBE is not implemented. 586 */ 587 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 588 MDCR_EL2_HPMD) | 589 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 590 >> PMCR_EL0_N_SHIFT)) & 591 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 592 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 593 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 594 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 595 MDCR_EL2_TPMCR_BIT | 596 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 597 598 write_mdcr_el2(mdcr_el2); 599 600 /* 601 * Initialise HSTR_EL2. All fields are architecturally 602 * UNKNOWN on reset. 603 * 604 * HSTR_EL2.T<n>: Set all these fields to zero so that 605 * Non-secure EL0 or EL1 accesses to System registers 606 * do not trap to EL2. 607 */ 608 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 609 /* 610 * Initialise CNTHP_CTL_EL2. All fields are 611 * architecturally UNKNOWN on reset. 612 * 613 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 614 * physical timer and prevent timer interrupts. 615 */ 616 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 617 ~(CNTHP_CTL_ENABLE_BIT)); 618 } 619 enable_extensions_nonsecure(el2_unused, ctx); 620 } 621 622 cm_el1_sysregs_context_restore(security_state); 623 cm_set_next_eret_context(security_state); 624 } 625 626 #if CTX_INCLUDE_EL2_REGS 627 /******************************************************************************* 628 * Save EL2 sysreg context 629 ******************************************************************************/ 630 void cm_el2_sysregs_context_save(uint32_t security_state) 631 { 632 u_register_t scr_el3 = read_scr(); 633 634 /* 635 * Always save the non-secure EL2 context, only save the 636 * S-EL2 context if S-EL2 is enabled. 637 */ 638 if ((security_state == NON_SECURE) || 639 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 640 cpu_context_t *ctx; 641 642 ctx = cm_get_context(security_state); 643 assert(ctx != NULL); 644 645 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 646 } 647 } 648 649 /******************************************************************************* 650 * Restore EL2 sysreg context 651 ******************************************************************************/ 652 void cm_el2_sysregs_context_restore(uint32_t security_state) 653 { 654 u_register_t scr_el3 = read_scr(); 655 656 /* 657 * Always restore the non-secure EL2 context, only restore the 658 * S-EL2 context if S-EL2 is enabled. 659 */ 660 if ((security_state == NON_SECURE) || 661 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 662 cpu_context_t *ctx; 663 664 ctx = cm_get_context(security_state); 665 assert(ctx != NULL); 666 667 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 668 } 669 } 670 #endif /* CTX_INCLUDE_EL2_REGS */ 671 672 /******************************************************************************* 673 * The next four functions are used by runtime services to save and restore 674 * EL1 context on the 'cpu_context' structure for the specified security 675 * state. 676 ******************************************************************************/ 677 void cm_el1_sysregs_context_save(uint32_t security_state) 678 { 679 cpu_context_t *ctx; 680 681 ctx = cm_get_context(security_state); 682 assert(ctx != NULL); 683 684 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 685 686 #if IMAGE_BL31 687 if (security_state == SECURE) 688 PUBLISH_EVENT(cm_exited_secure_world); 689 else 690 PUBLISH_EVENT(cm_exited_normal_world); 691 #endif 692 } 693 694 void cm_el1_sysregs_context_restore(uint32_t security_state) 695 { 696 cpu_context_t *ctx; 697 698 ctx = cm_get_context(security_state); 699 assert(ctx != NULL); 700 701 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 702 703 #if IMAGE_BL31 704 if (security_state == SECURE) 705 PUBLISH_EVENT(cm_entering_secure_world); 706 else 707 PUBLISH_EVENT(cm_entering_normal_world); 708 #endif 709 } 710 711 /******************************************************************************* 712 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 713 * given security state with the given entrypoint 714 ******************************************************************************/ 715 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 716 { 717 cpu_context_t *ctx; 718 el3_state_t *state; 719 720 ctx = cm_get_context(security_state); 721 assert(ctx != NULL); 722 723 /* Populate EL3 state so that ERET jumps to the correct entry */ 724 state = get_el3state_ctx(ctx); 725 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 726 } 727 728 /******************************************************************************* 729 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 730 * pertaining to the given security state 731 ******************************************************************************/ 732 void cm_set_elr_spsr_el3(uint32_t security_state, 733 uintptr_t entrypoint, uint32_t spsr) 734 { 735 cpu_context_t *ctx; 736 el3_state_t *state; 737 738 ctx = cm_get_context(security_state); 739 assert(ctx != NULL); 740 741 /* Populate EL3 state so that ERET jumps to the correct entry */ 742 state = get_el3state_ctx(ctx); 743 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 744 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 745 } 746 747 /******************************************************************************* 748 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 749 * pertaining to the given security state using the value and bit position 750 * specified in the parameters. It preserves all other bits. 751 ******************************************************************************/ 752 void cm_write_scr_el3_bit(uint32_t security_state, 753 uint32_t bit_pos, 754 uint32_t value) 755 { 756 cpu_context_t *ctx; 757 el3_state_t *state; 758 u_register_t scr_el3; 759 760 ctx = cm_get_context(security_state); 761 assert(ctx != NULL); 762 763 /* Ensure that the bit position is a valid one */ 764 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 765 766 /* Ensure that the 'value' is only a bit wide */ 767 assert(value <= 1U); 768 769 /* 770 * Get the SCR_EL3 value from the cpu context, clear the desired bit 771 * and set it to its new value. 772 */ 773 state = get_el3state_ctx(ctx); 774 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 775 scr_el3 &= ~(1UL << bit_pos); 776 scr_el3 |= (u_register_t)value << bit_pos; 777 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 778 } 779 780 /******************************************************************************* 781 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 782 * given security state. 783 ******************************************************************************/ 784 u_register_t cm_get_scr_el3(uint32_t security_state) 785 { 786 cpu_context_t *ctx; 787 el3_state_t *state; 788 789 ctx = cm_get_context(security_state); 790 assert(ctx != NULL); 791 792 /* Populate EL3 state so that ERET jumps to the correct entry */ 793 state = get_el3state_ctx(ctx); 794 return read_ctx_reg(state, CTX_SCR_EL3); 795 } 796 797 /******************************************************************************* 798 * This function is used to program the context that's used for exception 799 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 800 * the required security state 801 ******************************************************************************/ 802 void cm_set_next_eret_context(uint32_t security_state) 803 { 804 cpu_context_t *ctx; 805 806 ctx = cm_get_context(security_state); 807 assert(ctx != NULL); 808 809 cm_set_next_context(ctx); 810 } 811