1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* -------------------------------------------------- 25 * Errata Workaround for Cortex-A710 Erratum 1987031. 26 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 27 * open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a710_1987031_wa 34 /* Check revision. */ 35 mov x17, x30 36 bl check_errata_1987031 37 cbz x0, 1f 38 39 /* Apply instruction patching sequence */ 40 ldr x0,=0x6 41 msr S3_6_c15_c8_0,x0 42 ldr x0,=0xF3A08002 43 msr S3_6_c15_c8_2,x0 44 ldr x0,=0xFFF0F7FE 45 msr S3_6_c15_c8_3,x0 46 ldr x0,=0x40000001003ff 47 msr S3_6_c15_c8_1,x0 48 ldr x0,=0x7 49 msr S3_6_c15_c8_0,x0 50 ldr x0,=0xBF200000 51 msr S3_6_c15_c8_2,x0 52 ldr x0,=0xFFEF0000 53 msr S3_6_c15_c8_3,x0 54 ldr x0,=0x40000001003f3 55 msr S3_6_c15_c8_1,x0 56 isb 571: 58 ret x17 59endfunc errata_a710_1987031_wa 60 61func check_errata_1987031 62 /* Applies to r0p0, r1p0 and r2p0 */ 63 mov x1, #0x20 64 b cpu_rev_var_ls 65endfunc check_errata_1987031 66 67/* -------------------------------------------------- 68 * Errata Workaround for Cortex-A710 Erratum 2081180. 69 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 70 * It is still open. 71 * Inputs: 72 * x0: variant[4:7] and revision[0:3] of current cpu. 73 * Shall clobber: x0-x17 74 * -------------------------------------------------- 75 */ 76func errata_a710_2081180_wa 77 /* Check revision. */ 78 mov x17, x30 79 bl check_errata_2081180 80 cbz x0, 1f 81 82 /* Apply instruction patching sequence */ 83 ldr x0,=0x3 84 msr S3_6_c15_c8_0,x0 85 ldr x0,=0xF3A08002 86 msr S3_6_c15_c8_2,x0 87 ldr x0,=0xFFF0F7FE 88 msr S3_6_c15_c8_3,x0 89 ldr x0,=0x10002001003FF 90 msr S3_6_c15_c8_1,x0 91 ldr x0,=0x4 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xBF200000 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFEF0000 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003F3 98 msr S3_6_c15_c8_1,x0 99 isb 1001: 101 ret x17 102endfunc errata_a710_2081180_wa 103 104func check_errata_2081180 105 /* Applies to r0p0, r1p0 and r2p0 */ 106 mov x1, #0x20 107 b cpu_rev_var_ls 108endfunc check_errata_2081180 109 110 /* ---------------------------------------------------- 111 * HW will do the cache maintenance while powering down 112 * ---------------------------------------------------- 113 */ 114func cortex_a710_core_pwr_dwn 115 /* --------------------------------------------------- 116 * Enable CPU power down bit in power control register 117 * --------------------------------------------------- 118 */ 119 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 120 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 121 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 122 isb 123 ret 124endfunc cortex_a710_core_pwr_dwn 125 126 /* 127 * Errata printing function for Cortex A710. Must follow AAPCS. 128 */ 129#if REPORT_ERRATA 130func cortex_a710_errata_report 131 stp x8, x30, [sp, #-16]! 132 133 bl cpu_get_rev_var 134 mov x8, x0 135 136 /* 137 * Report all errata. The revision-variant information is passed to 138 * checking functions of each errata. 139 */ 140 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 141 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 142 143 ldp x8, x30, [sp], #16 144 ret 145endfunc cortex_a710_errata_report 146#endif 147 148func cortex_a710_reset_func 149 mov x19, x30 150 151 /* Disable speculative loads */ 152 msr SSBS, xzr 153 154 bl cpu_get_rev_var 155 mov x18, x0 156 157#if ERRATA_A710_1987031 158 mov x0, x18 159 bl errata_a710_1987031_wa 160#endif 161 162#if ERRATA_A710_2081180 163 mov x0, x18 164 bl errata_a710_2081180_wa 165#endif 166 167 isb 168 ret x19 169endfunc cortex_a710_reset_func 170 171 /* --------------------------------------------- 172 * This function provides Cortex-A710 specific 173 * register information for crash reporting. 174 * It needs to return with x6 pointing to 175 * a list of register names in ascii and 176 * x8 - x15 having values of registers to be 177 * reported. 178 * --------------------------------------------- 179 */ 180.section .rodata.cortex_a710_regs, "aS" 181cortex_a710_regs: /* The ascii list of register names to be reported */ 182 .asciz "cpuectlr_el1", "" 183 184func cortex_a710_cpu_reg_dump 185 adr x6, cortex_a710_regs 186 mrs x8, CORTEX_A710_CPUECTLR_EL1 187 ret 188endfunc cortex_a710_cpu_reg_dump 189 190declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 191 cortex_a710_reset_func, \ 192 cortex_a710_core_pwr_dwn 193