1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 U(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 168 #define ID_AA64PFR0_GIC_SHIFT U(24) 169 #define ID_AA64PFR0_GIC_WIDTH U(4) 170 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 171 #define ID_AA64PFR0_SVE_SHIFT U(32) 172 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 173 #define ID_AA64PFR0_SVE_LENGTH U(4) 174 #define ID_AA64PFR0_SEL2_SHIFT U(36) 175 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 176 #define ID_AA64PFR0_MPAM_SHIFT U(40) 177 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 178 #define ID_AA64PFR0_DIT_SHIFT U(48) 179 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 180 #define ID_AA64PFR0_DIT_LENGTH U(4) 181 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 182 #define ID_AA64PFR0_CSV2_SHIFT U(56) 183 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 184 #define ID_AA64PFR0_CSV2_LENGTH U(4) 185 186 /* Exception level handling */ 187 #define EL_IMPL_NONE ULL(0) 188 #define EL_IMPL_A64ONLY ULL(1) 189 #define EL_IMPL_A64_A32 ULL(2) 190 191 /* ID_AA64DFR0_EL1.TraceVer definitions */ 192 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 193 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 194 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 195 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 196 197 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 198 #define ID_AA64DFR0_PMS_SHIFT U(32) 199 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 200 201 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 202 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 203 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 204 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 205 206 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 207 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 208 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 209 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 210 211 /* ID_AA64ISAR0_EL1 definitions */ 212 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 213 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 214 215 /* ID_AA64ISAR1_EL1 definitions */ 216 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 217 #define ID_AA64ISAR1_GPI_SHIFT U(28) 218 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 219 #define ID_AA64ISAR1_GPA_SHIFT U(24) 220 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 221 #define ID_AA64ISAR1_API_SHIFT U(8) 222 #define ID_AA64ISAR1_API_MASK ULL(0xf) 223 #define ID_AA64ISAR1_APA_SHIFT U(4) 224 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 225 226 /* ID_AA64MMFR0_EL1 definitions */ 227 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 228 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 229 230 #define PARANGE_0000 U(32) 231 #define PARANGE_0001 U(36) 232 #define PARANGE_0010 U(40) 233 #define PARANGE_0011 U(42) 234 #define PARANGE_0100 U(44) 235 #define PARANGE_0101 U(48) 236 #define PARANGE_0110 U(52) 237 238 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 239 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 240 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 241 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 242 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 243 244 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 245 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 246 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 247 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 248 249 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 250 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 251 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 252 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 253 254 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 255 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 256 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 257 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 258 259 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 260 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 261 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 262 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 263 264 /* ID_AA64MMFR1_EL1 definitions */ 265 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 266 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 267 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 268 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 269 270 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 271 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 272 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 273 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 274 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 275 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 276 277 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 278 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 279 280 /* ID_AA64MMFR2_EL1 definitions */ 281 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 282 283 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 284 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 285 286 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 287 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 288 289 /* ID_AA64PFR1_EL1 definitions */ 290 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 291 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 292 293 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 294 295 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 296 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 297 298 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 299 300 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 301 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 302 303 /* Memory Tagging Extension is not implemented */ 304 #define MTE_UNIMPLEMENTED U(0) 305 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 306 #define MTE_IMPLEMENTED_EL0 U(1) 307 /* FEAT_MTE2: Full MTE is implemented */ 308 #define MTE_IMPLEMENTED_ELX U(2) 309 /* 310 * FEAT_MTE3: MTE is implemented with support for 311 * asymmetric Tag Check Fault handling 312 */ 313 #define MTE_IMPLEMENTED_ASY U(3) 314 315 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 316 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 317 318 /* ID_PFR1_EL1 definitions */ 319 #define ID_PFR1_VIRTEXT_SHIFT U(12) 320 #define ID_PFR1_VIRTEXT_MASK U(0xf) 321 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 322 & ID_PFR1_VIRTEXT_MASK) 323 324 /* SCTLR definitions */ 325 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 326 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 327 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 328 329 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 330 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 331 332 #define SCTLR_AARCH32_EL1_RES1 \ 333 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 334 (U(1) << 4) | (U(1) << 3)) 335 336 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 337 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 338 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 339 340 #define SCTLR_M_BIT (ULL(1) << 0) 341 #define SCTLR_A_BIT (ULL(1) << 1) 342 #define SCTLR_C_BIT (ULL(1) << 2) 343 #define SCTLR_SA_BIT (ULL(1) << 3) 344 #define SCTLR_SA0_BIT (ULL(1) << 4) 345 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 346 #define SCTLR_nAA_BIT (ULL(1) << 6) 347 #define SCTLR_ITD_BIT (ULL(1) << 7) 348 #define SCTLR_SED_BIT (ULL(1) << 8) 349 #define SCTLR_UMA_BIT (ULL(1) << 9) 350 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 351 #define SCTLR_EOS_BIT (ULL(1) << 11) 352 #define SCTLR_I_BIT (ULL(1) << 12) 353 #define SCTLR_EnDB_BIT (ULL(1) << 13) 354 #define SCTLR_DZE_BIT (ULL(1) << 14) 355 #define SCTLR_UCT_BIT (ULL(1) << 15) 356 #define SCTLR_NTWI_BIT (ULL(1) << 16) 357 #define SCTLR_NTWE_BIT (ULL(1) << 18) 358 #define SCTLR_WXN_BIT (ULL(1) << 19) 359 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 360 #define SCTLR_IESB_BIT (ULL(1) << 21) 361 #define SCTLR_EIS_BIT (ULL(1) << 22) 362 #define SCTLR_SPAN_BIT (ULL(1) << 23) 363 #define SCTLR_E0E_BIT (ULL(1) << 24) 364 #define SCTLR_EE_BIT (ULL(1) << 25) 365 #define SCTLR_UCI_BIT (ULL(1) << 26) 366 #define SCTLR_EnDA_BIT (ULL(1) << 27) 367 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 368 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 369 #define SCTLR_EnIB_BIT (ULL(1) << 30) 370 #define SCTLR_EnIA_BIT (ULL(1) << 31) 371 #define SCTLR_BT0_BIT (ULL(1) << 35) 372 #define SCTLR_BT1_BIT (ULL(1) << 36) 373 #define SCTLR_BT_BIT (ULL(1) << 36) 374 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 375 #define SCTLR_TCF0_SHIFT U(38) 376 #define SCTLR_TCF0_MASK ULL(3) 377 378 /* Tag Check Faults in EL0 have no effect on the PE */ 379 #define SCTLR_TCF0_NO_EFFECT U(0) 380 /* Tag Check Faults in EL0 cause a synchronous exception */ 381 #define SCTLR_TCF0_SYNC U(1) 382 /* Tag Check Faults in EL0 are asynchronously accumulated */ 383 #define SCTLR_TCF0_ASYNC U(2) 384 /* 385 * Tag Check Faults in EL0 cause a synchronous exception on reads, 386 * and are asynchronously accumulated on writes 387 */ 388 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 389 390 #define SCTLR_TCF_SHIFT U(40) 391 #define SCTLR_TCF_MASK ULL(3) 392 393 /* Tag Check Faults in EL1 have no effect on the PE */ 394 #define SCTLR_TCF_NO_EFFECT U(0) 395 /* Tag Check Faults in EL1 cause a synchronous exception */ 396 #define SCTLR_TCF_SYNC U(1) 397 /* Tag Check Faults in EL1 are asynchronously accumulated */ 398 #define SCTLR_TCF_ASYNC U(2) 399 /* 400 * Tag Check Faults in EL1 cause a synchronous exception on reads, 401 * and are asynchronously accumulated on writes 402 */ 403 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 404 405 #define SCTLR_ATA0_BIT (ULL(1) << 42) 406 #define SCTLR_ATA_BIT (ULL(1) << 43) 407 #define SCTLR_DSSBS_SHIFT U(44) 408 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 409 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 410 #define SCTLR_TWEDEL_SHIFT U(46) 411 #define SCTLR_TWEDEL_MASK ULL(0xf) 412 #define SCTLR_EnASR_BIT (ULL(1) << 54) 413 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 414 #define SCTLR_EnALS_BIT (ULL(1) << 56) 415 #define SCTLR_EPAN_BIT (ULL(1) << 57) 416 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 417 418 /* CPACR_EL1 definitions */ 419 #define CPACR_EL1_FPEN(x) ((x) << 20) 420 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 421 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 422 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 423 424 /* SCR definitions */ 425 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 426 #define SCR_TWEDEL_SHIFT U(30) 427 #define SCR_TWEDEL_MASK ULL(0xf) 428 #define SCR_AMVOFFEN_BIT (UL(1) << 35) 429 #define SCR_TWEDEn_BIT (UL(1) << 29) 430 #define SCR_ECVEN_BIT (UL(1) << 28) 431 #define SCR_FGTEN_BIT (UL(1) << 27) 432 #define SCR_ATA_BIT (UL(1) << 26) 433 #define SCR_FIEN_BIT (UL(1) << 21) 434 #define SCR_EEL2_BIT (UL(1) << 18) 435 #define SCR_API_BIT (UL(1) << 17) 436 #define SCR_APK_BIT (UL(1) << 16) 437 #define SCR_TERR_BIT (UL(1) << 15) 438 #define SCR_TWE_BIT (UL(1) << 13) 439 #define SCR_TWI_BIT (UL(1) << 12) 440 #define SCR_ST_BIT (UL(1) << 11) 441 #define SCR_RW_BIT (UL(1) << 10) 442 #define SCR_SIF_BIT (UL(1) << 9) 443 #define SCR_HCE_BIT (UL(1) << 8) 444 #define SCR_SMD_BIT (UL(1) << 7) 445 #define SCR_EA_BIT (UL(1) << 3) 446 #define SCR_FIQ_BIT (UL(1) << 2) 447 #define SCR_IRQ_BIT (UL(1) << 1) 448 #define SCR_NS_BIT (UL(1) << 0) 449 #define SCR_VALID_BIT_MASK U(0x2f8f) 450 #define SCR_RESET_VAL SCR_RES1_BITS 451 452 /* MDCR_EL3 definitions */ 453 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 454 #define MDCR_MPMX_BIT (ULL(1) << 35) 455 #define MDCR_MCCD_BIT (ULL(1) << 34) 456 #define MDCR_NSTB(x) ((x) << 24) 457 #define MDCR_NSTB_EL1 ULL(0x3) 458 #define MDCR_NSTBE (ULL(1) << 26) 459 #define MDCR_MTPME_BIT (ULL(1) << 28) 460 #define MDCR_TDCC_BIT (ULL(1) << 27) 461 #define MDCR_SCCD_BIT (ULL(1) << 23) 462 #define MDCR_EPMAD_BIT (ULL(1) << 21) 463 #define MDCR_EDAD_BIT (ULL(1) << 20) 464 #define MDCR_TTRF_BIT (ULL(1) << 19) 465 #define MDCR_STE_BIT (ULL(1) << 18) 466 #define MDCR_SPME_BIT (ULL(1) << 17) 467 #define MDCR_SDD_BIT (ULL(1) << 16) 468 #define MDCR_SPD32(x) ((x) << 14) 469 #define MDCR_SPD32_LEGACY ULL(0x0) 470 #define MDCR_SPD32_DISABLE ULL(0x2) 471 #define MDCR_SPD32_ENABLE ULL(0x3) 472 #define MDCR_NSPB(x) ((x) << 12) 473 #define MDCR_NSPB_EL1 ULL(0x3) 474 #define MDCR_TDOSA_BIT (ULL(1) << 10) 475 #define MDCR_TDA_BIT (ULL(1) << 9) 476 #define MDCR_TPM_BIT (ULL(1) << 6) 477 #define MDCR_EL3_RESET_VAL ULL(0x0) 478 479 /* MDCR_EL2 definitions */ 480 #define MDCR_EL2_MTPME (U(1) << 28) 481 #define MDCR_EL2_HLP (U(1) << 26) 482 #define MDCR_EL2_E2TB(x) ((x) << 24) 483 #define MDCR_EL2_E2TB_EL1 U(0x3) 484 #define MDCR_EL2_HCCD (U(1) << 23) 485 #define MDCR_EL2_TTRF (U(1) << 19) 486 #define MDCR_EL2_HPMD (U(1) << 17) 487 #define MDCR_EL2_TPMS (U(1) << 14) 488 #define MDCR_EL2_E2PB(x) ((x) << 12) 489 #define MDCR_EL2_E2PB_EL1 U(0x3) 490 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 491 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 492 #define MDCR_EL2_TDA_BIT (U(1) << 9) 493 #define MDCR_EL2_TDE_BIT (U(1) << 8) 494 #define MDCR_EL2_HPME_BIT (U(1) << 7) 495 #define MDCR_EL2_TPM_BIT (U(1) << 6) 496 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 497 #define MDCR_EL2_RESET_VAL U(0x0) 498 499 /* HSTR_EL2 definitions */ 500 #define HSTR_EL2_RESET_VAL U(0x0) 501 #define HSTR_EL2_T_MASK U(0xff) 502 503 /* CNTHP_CTL_EL2 definitions */ 504 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 505 #define CNTHP_CTL_RESET_VAL U(0x0) 506 507 /* VTTBR_EL2 definitions */ 508 #define VTTBR_RESET_VAL ULL(0x0) 509 #define VTTBR_VMID_MASK ULL(0xff) 510 #define VTTBR_VMID_SHIFT U(48) 511 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 512 #define VTTBR_BADDR_SHIFT U(0) 513 514 /* HCR definitions */ 515 #define HCR_AMVOFFEN_BIT (ULL(1) << 51) 516 #define HCR_API_BIT (ULL(1) << 41) 517 #define HCR_APK_BIT (ULL(1) << 40) 518 #define HCR_E2H_BIT (ULL(1) << 34) 519 #define HCR_TGE_BIT (ULL(1) << 27) 520 #define HCR_RW_SHIFT U(31) 521 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 522 #define HCR_AMO_BIT (ULL(1) << 5) 523 #define HCR_IMO_BIT (ULL(1) << 4) 524 #define HCR_FMO_BIT (ULL(1) << 3) 525 526 /* ISR definitions */ 527 #define ISR_A_SHIFT U(8) 528 #define ISR_I_SHIFT U(7) 529 #define ISR_F_SHIFT U(6) 530 531 /* CNTHCTL_EL2 definitions */ 532 #define CNTHCTL_RESET_VAL U(0x0) 533 #define EVNTEN_BIT (U(1) << 2) 534 #define EL1PCEN_BIT (U(1) << 1) 535 #define EL1PCTEN_BIT (U(1) << 0) 536 537 /* CNTKCTL_EL1 definitions */ 538 #define EL0PTEN_BIT (U(1) << 9) 539 #define EL0VTEN_BIT (U(1) << 8) 540 #define EL0PCTEN_BIT (U(1) << 0) 541 #define EL0VCTEN_BIT (U(1) << 1) 542 #define EVNTEN_BIT (U(1) << 2) 543 #define EVNTDIR_BIT (U(1) << 3) 544 #define EVNTI_SHIFT U(4) 545 #define EVNTI_MASK U(0xf) 546 547 /* CPTR_EL3 definitions */ 548 #define TCPAC_BIT (U(1) << 31) 549 #define TAM_BIT (U(1) << 30) 550 #define TTA_BIT (U(1) << 20) 551 #define TFP_BIT (U(1) << 10) 552 #define CPTR_EZ_BIT (U(1) << 8) 553 #define CPTR_EL3_RESET_VAL (TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT)) 554 555 /* CPTR_EL2 definitions */ 556 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 557 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 558 #define CPTR_EL2_TAM_BIT (U(1) << 30) 559 #define CPTR_EL2_TTA_BIT (U(1) << 20) 560 #define CPTR_EL2_TFP_BIT (U(1) << 10) 561 #define CPTR_EL2_TZ_BIT (U(1) << 8) 562 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 563 564 /* CPSR/SPSR definitions */ 565 #define DAIF_FIQ_BIT (U(1) << 0) 566 #define DAIF_IRQ_BIT (U(1) << 1) 567 #define DAIF_ABT_BIT (U(1) << 2) 568 #define DAIF_DBG_BIT (U(1) << 3) 569 #define SPSR_DAIF_SHIFT U(6) 570 #define SPSR_DAIF_MASK U(0xf) 571 572 #define SPSR_AIF_SHIFT U(6) 573 #define SPSR_AIF_MASK U(0x7) 574 575 #define SPSR_E_SHIFT U(9) 576 #define SPSR_E_MASK U(0x1) 577 #define SPSR_E_LITTLE U(0x0) 578 #define SPSR_E_BIG U(0x1) 579 580 #define SPSR_T_SHIFT U(5) 581 #define SPSR_T_MASK U(0x1) 582 #define SPSR_T_ARM U(0x0) 583 #define SPSR_T_THUMB U(0x1) 584 585 #define SPSR_M_SHIFT U(4) 586 #define SPSR_M_MASK U(0x1) 587 #define SPSR_M_AARCH64 U(0x0) 588 #define SPSR_M_AARCH32 U(0x1) 589 590 #define SPSR_EL_SHIFT U(2) 591 #define SPSR_EL_WIDTH U(2) 592 593 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 594 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 595 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 596 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 597 598 #define SPSR_PAN_BIT BIT_64(22) 599 600 #define SPSR_DIT_BIT BIT(24) 601 602 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 603 604 #define DISABLE_ALL_EXCEPTIONS \ 605 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 606 607 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 608 609 /* 610 * RMR_EL3 definitions 611 */ 612 #define RMR_EL3_RR_BIT (U(1) << 1) 613 #define RMR_EL3_AA64_BIT (U(1) << 0) 614 615 /* 616 * HI-VECTOR address for AArch32 state 617 */ 618 #define HI_VECTOR_BASE U(0xFFFF0000) 619 620 /* 621 * TCR defintions 622 */ 623 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 624 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 625 #define TCR_EL1_IPS_SHIFT U(32) 626 #define TCR_EL2_PS_SHIFT U(16) 627 #define TCR_EL3_PS_SHIFT U(16) 628 629 #define TCR_TxSZ_MIN ULL(16) 630 #define TCR_TxSZ_MAX ULL(39) 631 #define TCR_TxSZ_MAX_TTST ULL(48) 632 633 #define TCR_T0SZ_SHIFT U(0) 634 #define TCR_T1SZ_SHIFT U(16) 635 636 /* (internal) physical address size bits in EL3/EL1 */ 637 #define TCR_PS_BITS_4GB ULL(0x0) 638 #define TCR_PS_BITS_64GB ULL(0x1) 639 #define TCR_PS_BITS_1TB ULL(0x2) 640 #define TCR_PS_BITS_4TB ULL(0x3) 641 #define TCR_PS_BITS_16TB ULL(0x4) 642 #define TCR_PS_BITS_256TB ULL(0x5) 643 644 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 645 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 646 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 647 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 648 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 649 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 650 651 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 652 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 653 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 654 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 655 656 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 657 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 658 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 659 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 660 661 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 662 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 663 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 664 665 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 666 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 667 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 668 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 669 670 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 671 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 672 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 673 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 674 675 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 676 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 677 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 678 679 #define TCR_TG0_SHIFT U(14) 680 #define TCR_TG0_MASK ULL(3) 681 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 682 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 683 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 684 685 #define TCR_TG1_SHIFT U(30) 686 #define TCR_TG1_MASK ULL(3) 687 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 688 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 689 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 690 691 #define TCR_EPD0_BIT (ULL(1) << 7) 692 #define TCR_EPD1_BIT (ULL(1) << 23) 693 694 #define MODE_SP_SHIFT U(0x0) 695 #define MODE_SP_MASK U(0x1) 696 #define MODE_SP_EL0 U(0x0) 697 #define MODE_SP_ELX U(0x1) 698 699 #define MODE_RW_SHIFT U(0x4) 700 #define MODE_RW_MASK U(0x1) 701 #define MODE_RW_64 U(0x0) 702 #define MODE_RW_32 U(0x1) 703 704 #define MODE_EL_SHIFT U(0x2) 705 #define MODE_EL_MASK U(0x3) 706 #define MODE_EL_WIDTH U(0x2) 707 #define MODE_EL3 U(0x3) 708 #define MODE_EL2 U(0x2) 709 #define MODE_EL1 U(0x1) 710 #define MODE_EL0 U(0x0) 711 712 #define MODE32_SHIFT U(0) 713 #define MODE32_MASK U(0xf) 714 #define MODE32_usr U(0x0) 715 #define MODE32_fiq U(0x1) 716 #define MODE32_irq U(0x2) 717 #define MODE32_svc U(0x3) 718 #define MODE32_mon U(0x6) 719 #define MODE32_abt U(0x7) 720 #define MODE32_hyp U(0xa) 721 #define MODE32_und U(0xb) 722 #define MODE32_sys U(0xf) 723 724 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 725 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 726 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 727 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 728 729 #define SPSR_64(el, sp, daif) \ 730 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 731 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 732 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 733 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 734 (~(SPSR_SSBS_BIT_AARCH64))) 735 736 #define SPSR_MODE32(mode, isa, endian, aif) \ 737 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 738 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 739 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 740 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 741 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 742 (~(SPSR_SSBS_BIT_AARCH32))) 743 744 /* 745 * TTBR Definitions 746 */ 747 #define TTBR_CNP_BIT ULL(0x1) 748 749 /* 750 * CTR_EL0 definitions 751 */ 752 #define CTR_CWG_SHIFT U(24) 753 #define CTR_CWG_MASK U(0xf) 754 #define CTR_ERG_SHIFT U(20) 755 #define CTR_ERG_MASK U(0xf) 756 #define CTR_DMINLINE_SHIFT U(16) 757 #define CTR_DMINLINE_MASK U(0xf) 758 #define CTR_L1IP_SHIFT U(14) 759 #define CTR_L1IP_MASK U(0x3) 760 #define CTR_IMINLINE_SHIFT U(0) 761 #define CTR_IMINLINE_MASK U(0xf) 762 763 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 764 765 /* Physical timer control register bit fields shifts and masks */ 766 #define CNTP_CTL_ENABLE_SHIFT U(0) 767 #define CNTP_CTL_IMASK_SHIFT U(1) 768 #define CNTP_CTL_ISTATUS_SHIFT U(2) 769 770 #define CNTP_CTL_ENABLE_MASK U(1) 771 #define CNTP_CTL_IMASK_MASK U(1) 772 #define CNTP_CTL_ISTATUS_MASK U(1) 773 774 /* Physical timer control macros */ 775 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 776 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 777 778 /* Exception Syndrome register bits and bobs */ 779 #define ESR_EC_SHIFT U(26) 780 #define ESR_EC_MASK U(0x3f) 781 #define ESR_EC_LENGTH U(6) 782 #define ESR_ISS_SHIFT U(0) 783 #define ESR_ISS_LENGTH U(25) 784 #define EC_UNKNOWN U(0x0) 785 #define EC_WFE_WFI U(0x1) 786 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 787 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 788 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 789 #define EC_AARCH32_CP14_LDC_STC U(0x6) 790 #define EC_FP_SIMD U(0x7) 791 #define EC_AARCH32_CP10_MRC U(0x8) 792 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 793 #define EC_ILLEGAL U(0xe) 794 #define EC_AARCH32_SVC U(0x11) 795 #define EC_AARCH32_HVC U(0x12) 796 #define EC_AARCH32_SMC U(0x13) 797 #define EC_AARCH64_SVC U(0x15) 798 #define EC_AARCH64_HVC U(0x16) 799 #define EC_AARCH64_SMC U(0x17) 800 #define EC_AARCH64_SYS U(0x18) 801 #define EC_IABORT_LOWER_EL U(0x20) 802 #define EC_IABORT_CUR_EL U(0x21) 803 #define EC_PC_ALIGN U(0x22) 804 #define EC_DABORT_LOWER_EL U(0x24) 805 #define EC_DABORT_CUR_EL U(0x25) 806 #define EC_SP_ALIGN U(0x26) 807 #define EC_AARCH32_FP U(0x28) 808 #define EC_AARCH64_FP U(0x2c) 809 #define EC_SERROR U(0x2f) 810 #define EC_BRK U(0x3c) 811 812 /* 813 * External Abort bit in Instruction and Data Aborts synchronous exception 814 * syndromes. 815 */ 816 #define ESR_ISS_EABORT_EA_BIT U(9) 817 818 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 819 820 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 821 #define RMR_RESET_REQUEST_SHIFT U(0x1) 822 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 823 824 /******************************************************************************* 825 * Definitions of register offsets, fields and macros for CPU system 826 * instructions. 827 ******************************************************************************/ 828 829 #define TLBI_ADDR_SHIFT U(12) 830 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 831 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 832 833 /******************************************************************************* 834 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 835 * system level implementation of the Generic Timer. 836 ******************************************************************************/ 837 #define CNTCTLBASE_CNTFRQ U(0x0) 838 #define CNTNSAR U(0x4) 839 #define CNTNSAR_NS_SHIFT(x) (x) 840 841 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 842 #define CNTACR_RPCT_SHIFT U(0x0) 843 #define CNTACR_RVCT_SHIFT U(0x1) 844 #define CNTACR_RFRQ_SHIFT U(0x2) 845 #define CNTACR_RVOFF_SHIFT U(0x3) 846 #define CNTACR_RWVT_SHIFT U(0x4) 847 #define CNTACR_RWPT_SHIFT U(0x5) 848 849 /******************************************************************************* 850 * Definitions of register offsets and fields in the CNTBaseN Frame of the 851 * system level implementation of the Generic Timer. 852 ******************************************************************************/ 853 /* Physical Count register. */ 854 #define CNTPCT_LO U(0x0) 855 /* Counter Frequency register. */ 856 #define CNTBASEN_CNTFRQ U(0x10) 857 /* Physical Timer CompareValue register. */ 858 #define CNTP_CVAL_LO U(0x20) 859 /* Physical Timer Control register. */ 860 #define CNTP_CTL U(0x2c) 861 862 /* PMCR_EL0 definitions */ 863 #define PMCR_EL0_RESET_VAL U(0x0) 864 #define PMCR_EL0_N_SHIFT U(11) 865 #define PMCR_EL0_N_MASK U(0x1f) 866 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 867 #define PMCR_EL0_LP_BIT (U(1) << 7) 868 #define PMCR_EL0_LC_BIT (U(1) << 6) 869 #define PMCR_EL0_DP_BIT (U(1) << 5) 870 #define PMCR_EL0_X_BIT (U(1) << 4) 871 #define PMCR_EL0_D_BIT (U(1) << 3) 872 #define PMCR_EL0_C_BIT (U(1) << 2) 873 #define PMCR_EL0_P_BIT (U(1) << 1) 874 #define PMCR_EL0_E_BIT (U(1) << 0) 875 876 /******************************************************************************* 877 * Definitions for system register interface to SVE 878 ******************************************************************************/ 879 #define ZCR_EL3 S3_6_C1_C2_0 880 #define ZCR_EL2 S3_4_C1_C2_0 881 882 /* ZCR_EL3 definitions */ 883 #define ZCR_EL3_LEN_MASK U(0xf) 884 885 /* ZCR_EL2 definitions */ 886 #define ZCR_EL2_LEN_MASK U(0xf) 887 888 /******************************************************************************* 889 * Definitions of MAIR encodings for device and normal memory 890 ******************************************************************************/ 891 /* 892 * MAIR encodings for device memory attributes. 893 */ 894 #define MAIR_DEV_nGnRnE ULL(0x0) 895 #define MAIR_DEV_nGnRE ULL(0x4) 896 #define MAIR_DEV_nGRE ULL(0x8) 897 #define MAIR_DEV_GRE ULL(0xc) 898 899 /* 900 * MAIR encodings for normal memory attributes. 901 * 902 * Cache Policy 903 * WT: Write Through 904 * WB: Write Back 905 * NC: Non-Cacheable 906 * 907 * Transient Hint 908 * NTR: Non-Transient 909 * TR: Transient 910 * 911 * Allocation Policy 912 * RA: Read Allocate 913 * WA: Write Allocate 914 * RWA: Read and Write Allocate 915 * NA: No Allocation 916 */ 917 #define MAIR_NORM_WT_TR_WA ULL(0x1) 918 #define MAIR_NORM_WT_TR_RA ULL(0x2) 919 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 920 #define MAIR_NORM_NC ULL(0x4) 921 #define MAIR_NORM_WB_TR_WA ULL(0x5) 922 #define MAIR_NORM_WB_TR_RA ULL(0x6) 923 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 924 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 925 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 926 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 927 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 928 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 929 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 930 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 931 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 932 933 #define MAIR_NORM_OUTER_SHIFT U(4) 934 935 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 936 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 937 938 /* PAR_EL1 fields */ 939 #define PAR_F_SHIFT U(0) 940 #define PAR_F_MASK ULL(0x1) 941 #define PAR_ADDR_SHIFT U(12) 942 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 943 944 /******************************************************************************* 945 * Definitions for system register interface to SPE 946 ******************************************************************************/ 947 #define PMBLIMITR_EL1 S3_0_C9_C10_0 948 949 /******************************************************************************* 950 * Definitions for system register interface to MPAM 951 ******************************************************************************/ 952 #define MPAMIDR_EL1 S3_0_C10_C4_4 953 #define MPAM2_EL2 S3_4_C10_C5_0 954 #define MPAMHCR_EL2 S3_4_C10_C4_0 955 #define MPAM3_EL3 S3_6_C10_C5_0 956 957 /******************************************************************************* 958 * Definitions for system register interface to AMU for FEAT_AMUv1 959 ******************************************************************************/ 960 #define AMCR_EL0 S3_3_C13_C2_0 961 #define AMCFGR_EL0 S3_3_C13_C2_1 962 #define AMCGCR_EL0 S3_3_C13_C2_2 963 #define AMUSERENR_EL0 S3_3_C13_C2_3 964 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 965 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 966 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 967 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 968 969 /* Activity Monitor Group 0 Event Counter Registers */ 970 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 971 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 972 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 973 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 974 975 /* Activity Monitor Group 0 Event Type Registers */ 976 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 977 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 978 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 979 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 980 981 /* Activity Monitor Group 1 Event Counter Registers */ 982 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 983 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 984 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 985 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 986 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 987 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 988 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 989 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 990 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 991 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 992 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 993 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 994 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 995 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 996 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 997 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 998 999 /* Activity Monitor Group 1 Event Type Registers */ 1000 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1001 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1002 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1003 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1004 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1005 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1006 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1007 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1008 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1009 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1010 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1011 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1012 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1013 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1014 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1015 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1016 1017 /* AMCFGR_EL0 definitions */ 1018 #define AMCFGR_EL0_NCG_SHIFT U(28) 1019 #define AMCFGR_EL0_NCG_MASK U(0xf) 1020 #define AMCFGR_EL0_N_SHIFT U(0) 1021 #define AMCFGR_EL0_N_MASK U(0xff) 1022 1023 /* AMCGCR_EL0 definitions */ 1024 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1025 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1026 1027 /* MPAM register definitions */ 1028 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1029 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1030 1031 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1032 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1033 1034 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1035 1036 /******************************************************************************* 1037 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1038 ******************************************************************************/ 1039 1040 /* Definition for register defining which virtual offsets are implemented. */ 1041 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1042 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1043 #define AMCG1IDR_CTR_SHIFT U(0) 1044 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1045 #define AMCG1IDR_VOFF_SHIFT U(16) 1046 1047 /* New bit added to AMCR_EL0 */ 1048 #define AMCR_CG1RZ_BIT (ULL(0x1) << 17) 1049 1050 /* 1051 * Definitions for virtual offset registers for architected activity monitor 1052 * event counters. 1053 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1054 */ 1055 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1056 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1057 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1058 1059 /* 1060 * Definitions for virtual offset registers for auxiliary activity monitor event 1061 * counters. 1062 */ 1063 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1064 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1065 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1066 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1067 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1068 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1069 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1070 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1071 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1072 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1073 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1074 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1075 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1076 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1077 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1078 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1079 1080 /******************************************************************************* 1081 * RAS system registers 1082 ******************************************************************************/ 1083 #define DISR_EL1 S3_0_C12_C1_1 1084 #define DISR_A_BIT U(31) 1085 1086 #define ERRIDR_EL1 S3_0_C5_C3_0 1087 #define ERRIDR_MASK U(0xffff) 1088 1089 #define ERRSELR_EL1 S3_0_C5_C3_1 1090 1091 /* System register access to Standard Error Record registers */ 1092 #define ERXFR_EL1 S3_0_C5_C4_0 1093 #define ERXCTLR_EL1 S3_0_C5_C4_1 1094 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1095 #define ERXADDR_EL1 S3_0_C5_C4_3 1096 #define ERXPFGF_EL1 S3_0_C5_C4_4 1097 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1098 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1099 #define ERXMISC0_EL1 S3_0_C5_C5_0 1100 #define ERXMISC1_EL1 S3_0_C5_C5_1 1101 1102 #define ERXCTLR_ED_BIT (U(1) << 0) 1103 #define ERXCTLR_UE_BIT (U(1) << 4) 1104 1105 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1106 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1107 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1108 1109 /******************************************************************************* 1110 * Armv8.3 Pointer Authentication Registers 1111 ******************************************************************************/ 1112 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1113 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1114 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1115 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1116 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1117 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1118 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1119 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1120 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1121 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1122 1123 /******************************************************************************* 1124 * Armv8.4 Data Independent Timing Registers 1125 ******************************************************************************/ 1126 #define DIT S3_3_C4_C2_5 1127 #define DIT_BIT BIT(24) 1128 1129 /******************************************************************************* 1130 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1131 ******************************************************************************/ 1132 #define SSBS S3_3_C4_C2_6 1133 1134 /******************************************************************************* 1135 * Armv8.5 - Memory Tagging Extension Registers 1136 ******************************************************************************/ 1137 #define TFSRE0_EL1 S3_0_C5_C6_1 1138 #define TFSR_EL1 S3_0_C5_C6_0 1139 #define RGSR_EL1 S3_0_C1_C0_5 1140 #define GCR_EL1 S3_0_C1_C0_6 1141 1142 /******************************************************************************* 1143 * Definitions for DynamicIQ Shared Unit registers 1144 ******************************************************************************/ 1145 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1146 1147 /* CLUSTERPWRDN_EL1 register definitions */ 1148 #define DSU_CLUSTER_PWR_OFF 0 1149 #define DSU_CLUSTER_PWR_ON 1 1150 #define DSU_CLUSTER_PWR_MASK U(1) 1151 1152 #endif /* ARCH_H */ 1153