1# 2# Copyright (c) 2016-2021, ARM Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# BL2 image is stored in XIP memory, for now, this option is only supported 36# when BL2_AT_EL3 is 1. 37BL2_IN_XIP_MEM := 0 38 39# Do dcache invalidate upon BL2 entry at EL3 40BL2_INV_DCACHE := 1 41 42# Select the branch protection features to use. 43BRANCH_PROTECTION := 0 44 45# By default, consider that the platform may release several CPUs out of reset. 46# The platform Makefile is free to override this value. 47COLD_BOOT_SINGLE_CPU := 0 48 49# Flag to compile in coreboot support code. Exclude by default. The coreboot 50# Makefile system will set this when compiling TF as part of a coreboot image. 51COREBOOT := 0 52 53# For Chain of Trust 54CREATE_KEYS := 1 55 56# Build flag to include AArch32 registers in cpu context save and restore during 57# world switch. This flag must be set to 0 for AArch64-only platforms. 58CTX_INCLUDE_AARCH32_REGS := 1 59 60# Include FP registers in cpu context 61CTX_INCLUDE_FPREGS := 0 62 63# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 64# must be set to 1 if the platform wants to use this feature in the Secure 65# world. It is not needed to use it in the Non-secure world. 66CTX_INCLUDE_PAUTH_REGS := 0 67 68# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 69# This must be set to 1 if architecture implements Nested Virtualization 70# Extension and platform wants to use this feature in the Secure world 71CTX_INCLUDE_NEVE_REGS := 0 72 73# Debug build 74DEBUG := 0 75 76# By default disable authenticated decryption support. 77DECRYPTION_SUPPORT := none 78 79# Build platform 80DEFAULT_PLAT := fvp 81 82# Disable the generation of the binary image (ELF only). 83DISABLE_BIN_GENERATION := 0 84 85# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 86# compatibility. 87DISABLE_MTPMU := 0 88 89# Enable capability to disable authentication dynamically. Only meant for 90# development platforms. 91DYN_DISABLE_AUTH := 0 92 93# Build option to enable MPAM for lower ELs 94ENABLE_MPAM_FOR_LOWER_ELS := 0 95 96# Flag to Enable Position Independant support (PIE) 97ENABLE_PIE := 0 98 99# Flag to enable Performance Measurement Framework 100ENABLE_PMF := 0 101 102# Flag to enable PSCI STATs functionality 103ENABLE_PSCI_STAT := 0 104 105# Flag to enable runtime instrumentation using PMF 106ENABLE_RUNTIME_INSTRUMENTATION := 0 107 108# Flag to enable stack corruption protection 109ENABLE_STACK_PROTECTOR := 0 110 111# Flag to enable exception handling in EL3 112EL3_EXCEPTION_HANDLING := 0 113 114# Flag to enable Branch Target Identification. 115# Internal flag not meant for direct setting. 116# Use BRANCH_PROTECTION to enable BTI. 117ENABLE_BTI := 0 118 119# Flag to enable Pointer Authentication. 120# Internal flag not meant for direct setting. 121# Use BRANCH_PROTECTION to enable PAUTH. 122ENABLE_PAUTH := 0 123 124# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 125ENABLE_FEAT_HCX := 0 126 127# By default BL31 encryption disabled 128ENCRYPT_BL31 := 0 129 130# By default BL32 encryption disabled 131ENCRYPT_BL32 := 0 132 133# Default dummy firmware encryption key 134ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 135 136# Default dummy nonce for firmware encryption 137ENC_NONCE := 1234567890abcdef12345678 138 139# Build flag to treat usage of deprecated platform and framework APIs as error. 140ERROR_DEPRECATED := 0 141 142# Fault injection support 143FAULT_INJECTION_SUPPORT := 0 144 145# Byte alignment that each component in FIP is aligned to 146FIP_ALIGN := 0 147 148# Default FIP file name 149FIP_NAME := fip.bin 150 151# Default FWU_FIP file name 152FWU_FIP_NAME := fwu_fip.bin 153 154# By default firmware encryption with SSK 155FW_ENC_STATUS := 0 156 157# For Chain of Trust 158GENERATE_COT := 0 159 160# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 161# default, they are for Secure EL1. 162GICV2_G0_FOR_EL3 := 0 163 164# Route External Aborts to EL3. Disabled by default; External Aborts are handled 165# by lower ELs. 166HANDLE_EA_EL3_FIRST := 0 167 168# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 169# The default value is sha256. 170HASH_ALG := sha256 171 172# Whether system coherency is managed in hardware, without explicit software 173# operations. 174HW_ASSISTED_COHERENCY := 0 175 176# Set the default algorithm for the generation of Trusted Board Boot keys 177KEY_ALG := rsa 178 179# Set the default key size in case KEY_ALG is rsa 180ifeq ($(KEY_ALG),rsa) 181KEY_SIZE := 2048 182endif 183 184# Option to build TF with Measured Boot support 185MEASURED_BOOT := 0 186 187# NS timer register save and restore 188NS_TIMER_SWITCH := 0 189 190# Include lib/libc in the final image 191OVERRIDE_LIBC := 0 192 193# Build PL011 UART driver in minimal generic UART mode 194PL011_GENERIC_UART := 0 195 196# By default, consider that the platform's reset address is not programmable. 197# The platform Makefile is free to override this value. 198PROGRAMMABLE_RESET_ADDRESS := 0 199 200# Flag used to choose the power state format: Extended State-ID or Original 201PSCI_EXTENDED_STATE_ID := 0 202 203# Enable RAS support 204RAS_EXTENSION := 0 205 206# By default, BL1 acts as the reset handler, not BL31 207RESET_TO_BL31 := 0 208 209# For Chain of Trust 210SAVE_KEYS := 0 211 212# Software Delegated Exception support 213SDEI_SUPPORT := 0 214 215# True Random Number firmware Interface 216TRNG_SUPPORT := 0 217 218# SMCCC PCI support 219SMC_PCI_SUPPORT := 0 220 221# Whether code and read-only data should be put on separate memory pages. The 222# platform Makefile is free to override this value. 223SEPARATE_CODE_AND_RODATA := 0 224 225# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 226# separate memory region, which may be discontiguous from the rest of BL31. 227SEPARATE_NOBITS_REGION := 0 228 229# If the BL31 image initialisation code is recalimed after use for the secondary 230# cores stack 231RECLAIM_INIT_CODE := 0 232 233# SPD choice 234SPD := none 235 236# Enable the Management Mode (MM)-based Secure Partition Manager implementation 237SPM_MM := 0 238 239# Use SPM at S-EL2 as a default config for SPMD 240SPMD_SPM_AT_SEL2 := 1 241 242# Flag to introduce an infinite loop in BL1 just before it exits into the next 243# image. This is meant to help debugging the post-BL2 phase. 244SPIN_ON_BL1_EXIT := 0 245 246# Flags to build TF with Trusted Boot support 247TRUSTED_BOARD_BOOT := 0 248 249# Build option to choose whether Trusted Firmware uses Coherent memory or not. 250USE_COHERENT_MEM := 1 251 252# Build option to add debugfs support 253USE_DEBUGFS := 0 254 255# Build option to fconf based io 256ARM_IO_IN_DTB := 0 257 258# Build option to support SDEI through fconf 259SDEI_IN_FCONF := 0 260 261# Build option to support Secure Interrupt descriptors through fconf 262SEC_INT_DESC_IN_FCONF := 0 263 264# Build option to choose whether Trusted Firmware uses library at ROM 265USE_ROMLIB := 0 266 267# Build option to choose whether the xlat tables of BL images can be read-only. 268# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 269# which is the per BL-image option that actually enables the read-only tables 270# API. The reason for having this additional option is to have a common high 271# level makefile where we can check for incompatible features/build options. 272ALLOW_RO_XLAT_TABLES := 0 273 274# Chain of trust. 275COT := tbbr 276 277# Use tbbr_oid.h instead of platform_oid.h 278USE_TBBR_DEFS := 1 279 280# Build verbosity 281V := 0 282 283# Whether to enable D-Cache early during warm boot. This is usually 284# applicable for platforms wherein interconnect programming is not 285# required to enable cache coherency after warm reset (eg: single cluster 286# platforms). 287WARMBOOT_ENABLE_DCACHE_EARLY := 0 288 289# Build option to enable/disable the Statistical Profiling Extensions 290ENABLE_SPE_FOR_LOWER_ELS := 1 291 292# SPE is only supported on AArch64 so disable it on AArch32. 293ifeq (${ARCH},aarch32) 294 override ENABLE_SPE_FOR_LOWER_ELS := 0 295endif 296 297# Include Memory Tagging Extension registers in cpu context. This must be set 298# to 1 if the platform wants to use this feature in the Secure world and MTE is 299# enabled at ELX. 300CTX_INCLUDE_MTE_REGS := 0 301 302ENABLE_AMU := 0 303AMU_RESTRICT_COUNTERS := 0 304 305# By default, enable Scalable Vector Extension if implemented only for Non-secure 306# lower ELs 307# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 308ifneq (${ARCH},aarch32) 309 ENABLE_SVE_FOR_NS := 1 310 ENABLE_SVE_FOR_SWD := 0 311else 312 override ENABLE_SVE_FOR_NS := 0 313 override ENABLE_SVE_FOR_SWD := 0 314endif 315 316SANITIZE_UB := off 317 318# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 319# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 320# Default: disabled 321USE_SPINLOCK_CAS := 0 322 323# Enable Link Time Optimization 324ENABLE_LTO := 0 325 326# Build flag to include EL2 registers in cpu context save and restore during 327# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 328# Default is 0. 329CTX_INCLUDE_EL2_REGS := 0 330 331# Enable Memory tag extension which is supported for architecture greater 332# than Armv8.5-A 333# By default it is set to "no" 334SUPPORT_STACK_MEMTAG := no 335 336# Select workaround for AT speculative behaviour. 337ERRATA_SPECULATIVE_AT := 0 338 339# Trap RAS error record access from lower EL 340RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 341 342# Build option to create cot descriptors using fconf 343COT_DESC_IN_DTB := 0 344 345# Build option to provide openssl directory path 346OPENSSL_DIR := /usr 347 348# Build option to use the SP804 timer instead of the generic one 349USE_SP804_TIMER := 0 350 351# Build option to define number of firmware banks, used in firmware update 352# metadata structure. 353NR_OF_FW_BANKS := 2 354 355# Build option to define number of images in firmware bank, used in firmware 356# update metadata structure. 357NR_OF_IMAGES_IN_FW_BANK := 1 358 359# Disable Firmware update support by default 360PSA_FWU_SUPPORT := 0 361 362# By default, disable access of trace buffer control registers from NS 363# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 364# if FEAT_TRBE is implemented. 365# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 366# AArch32. 367ifneq (${ARCH},aarch32) 368 ENABLE_TRBE_FOR_NS := 0 369else 370 override ENABLE_TRBE_FOR_NS := 0 371endif 372 373# By default, disable access of trace system registers from NS lower 374# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 375# system register trace is implemented. 376ENABLE_SYS_REG_TRACE_FOR_NS := 0 377 378# By default, disable trace filter control registers access to NS 379# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 380# if FEAT_TRF is implemented. 381ENABLE_TRF_FOR_NS := 0 382